EECS 141 – S02
Lecture 10
Wire Modeling
Combinational Logic
Digital Integrated Circuits
Interconnect
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Last Lecture
Scaling
l Wire parasitics
l
» Capacitance
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1
Today’s Lecture
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Wire modeling
» Resistance
» Ellmore Delay
» Distributed RC line and models
l
Introduction to static CMOS gates
Digital Integrated Circuits
Interconnect
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Administrivia
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Review session
» Monday Feb 25, 6:30-8pm, 277 Cory
l
Office hour Friday Feb 22,
» 10:30-12pm in 511 Cory
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Midterm Exam Tu Feb 26.
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Interconnect
Digital Integrated Circuits
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The Lumped Model
Vo ut
c wire
Driver
Rdriver
Vout
Vin
Clumpe d
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The Lumped RC-Model
The Ellmore Delay
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The Ellmore Delay
RC Chain
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Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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The Distributed RC-line
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Step-response of RC wire as a
function of time and space
2.5
x= L/10
2
voltage (V)
x = L/4
1.5
x = L/2
1
x= L
0.5
0
0
Digital Integrated Circuits
0.5
1
1.5
2
2.5
3
time (nsec)
3.5
Interconnect
4
4.5
5
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RC-Models
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Driving an RC-line
Rs
(rw,cw,L)
Vout
Vin
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Design Rules of Thumb
l
l
rc delays should only be considered when
tpRC >> tpgate of the driving gate
Lcrit >> √ tpgate/0.38rc
rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC
» when not met, the change in the signal is slower
than the propagation delay of the wire
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© MJIrwin, PSU, 2000
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7
COMBINATIONAL
LOGIC
Digital Integrated Circuits
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Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
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Combinational vs. Sequential Logic
In
Logic
In
Circuit
Out
Out
Logic
Circuit
State
(a) Combinational
(b) Sequential
Output = f(In, Previous In)
Output = f(In)
Digital Integrated Circuits
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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Static Complementary CMOS
VDD
PUN
…
In1
In2
InN
F(In1,In2,…InN)
PDN
…
In1
In2
InN
PMOS only
NMOS only
PUN and PDN are dual logic networks
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NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
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Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0 → VDD
VGS
S
CL
CL
VDD → 0
PDN
D
VDD
CL
S
Digital Integrated Circuits
0 → VDD - VTn
VGS
VDD → |VTp|
S
CL
D
Interconnect
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Complementary CMOS Logic Style Construction
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Example Gate: NAND
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Example Gate: NOR
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Complex CMOS Gate
B
A
C
D
OUT = !(D + A • (B + C))
A
D
B
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C
Interconnect
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