Via hole process for GaAs monolithic microwave integrated circuit using two‐step dry
etching
M. S. Chung, H. R. Kim, J. E. Lee, B. K. Kang, and B. M. Kim
Citation: Journal of Vacuum Science & Technology B 11, 159 (1993); doi: 10.1116/1.586696
View online: http://dx.doi.org/10.1116/1.586696
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Published by the AVS: Science & Technology of Materials, Interfaces, and Processing
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Via hole process for GaAs monolithic microwave integrated circuit
using two ..step dry etching
M. S. Chung, H. R. Kim, J. E. Lee, 8. K. Ka.ng, a.nd 8. M. Kim
Pohang Institute of Science and Technology and Research Institute of Industrial Science and Technology,
Pohang, Kyungpook, Korea
(Received 8 May 1992; accepted 25 November 1992)
A fast, reproducible, and reliable via hole dry etching process for GaAs monolithic microwave
inte~rated circuit (~MIC) fabrication is described. The etching process consists of two steps.
Dunn~ the first ~tchmg step, BC1 3/C1 2/ Ar gas mixture is used to achieve a high etch rate and
small lateral etchmg. In the second etching step, CClzF 2 gas is used to achieve a selective etching
of the GaAs substrate with respect to the front side metal layer, which is 500 A thick chromium.
V~a holes are formed from the back side of a 100 fLm thick GaAs substrate and are electroplated
wlt.h gold (~20 pm thick). The resulting via hole profile and surface morphology are
satIsfactory for reprodudble and reliable MMIC via groundings.
I. INTRODUCTION
Via connections are very important for GaAs microwave monolithic integrated circuits (MMI Cs). Via connections provide low inductance groundings for circuit elements, and anow increased circuit complexity due to the
. l·ft
' structures. 1-.3 The via connection proSimp
1 ed
groundmg
cess consists of the via hole etching step and a subsequent
metallization step. Before etching via holes, devices have
already been fabricated on the front side of the wafer, and
then the wafer is thinned to a thickness of - 100 f-lm. Via
hole etching is performed from the back side of the wafer
to contact the grounding pads on the front side. Because
the via hole etching follows all other device fabrication
processes, process reliability and reproducibility are very
important.
Via holes have been etched using either wet etching or
reactive ion etching (RIE) techniques. 3-.6 In the wet etching process, the etching reaction is isotropic and the etched
hole profile and dimensional controls are difficult. In RIE
processes, gas mixtures of BCl]/C12, CC1 2F2> and SiCl¥'CI2
are usually used. In the case of using CChF2 gas only, the
etch rate is too low, requiring 1 or 2 h of etch time to etch
- 100 pm deep vias, 7 and severe polymer deposition problem may exist, resulting in poor process reproducibility.
However, this process can provide excellent etch selectivity
of GaAs substrate with respect to the gold metal pad if a
thin chromium or nickel layer is inserted between the substrate and the pad metal. With other gas mixtures, the etch
rate can be increased significantly by increasing chlorine
content, but the etch selectivity is very poor. Also, the hole
surface morphology tends to be very rough, and the masking layer erodes when the chlori.ne content is too high.
In this article, we will describe a two step dry etching
process which can be applied to fabricate via holes for
MMICs in a fast, reproducible, and reliable way.
II. EXPERIMENT
The front oside of the GaAs substrate is coated initially
with 1l:, 500 A thick chromium layer and subsequently a
2000 A thick gold layer, Then, the back side of the sub159
J. Vac. Sci. Techno!. B 11(2}, Mar!Apr 1993
strate is thinned to -100 Itm by lapping with SiC. After
lapping the substrate, the surface is smoothed and cleaned
with HzS04:HzOz:H20=4:1:1 solution. The front side of
the thinned substrate is attached on a 100 !hm thick glass
plate with wax for the next processes. Vi.a hole mask pattern is made on 5 }-Lm thick AZ1350 photoresist. The patterned resist has been postbaked at 160°C for 30 mi.n to
increase the etch resistance.
A RIE~80 system from Plasma Technology Co. has
been used for via hole etching. The prepared samples are
mounted on a 5 in. silicon wafer to provide good thermal
contact with the radio-frequency Crf) electrode and to
scavenge fluorine atoms which are possibly released either
from Teflon feedthroughs or from fluorine containing polymers deposited on process chamber. The etching gases are
BC1 3/CI 2/ Ar mixture for the first step and CC1 2F 2 for the
second step. The process pressure, the gas flow rate, and
the gas mixture ratio are varied to find an optimum process
condition. After etching via holes, the photoresist masking
layer is removed, and the back side of the substrate and the
via holes are coated with 500 A thick gold. This gold layer
facilitates the subsequent electroplating of gold, which
serves as the ground metaL The resistances of the fabricated via connections are measured from their I-V characteristics. The thicknesses of the substrate and the photoresist mask are measured with a stylus instrument, and the
etched depth and the sidewall profile are examined by optical and scanning electron microscopes (SEM). The
chemical compositions of the etched surfaces are analyzed
with an electron spectroscopy for chemical analysis
(ESCA).
m. RESULTS AND DISCUSSION
The purpose of the first etching step is to shorten the
process time while maintaining good process reproducibility and good sidewall profile. For fast smooth-surfaced
vertical-wall via hole etching, gas mixtures of BC13/Clz,
SiC14/C1 2, and Be1 3/ Ar are commonly used,s Among these
gas mixtures, the BCI 3/Cl1 mixture shows the highest etch
rate but has a tendency to produce rough surfaces at an
0734·211 X!93/020159·06$01 000
@1993 American Vacuum Society
159
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-o--Elch rate
0
5
10
20
15
25
30
35
Etch time (min)
FIG. 1. Etch depth and etch rate vs etch time for a process condition of
BCI 3 = 11.4 seem, C1 2 = 12.3 seem, P= 150 mTorr, power = 110 W, and
T=20·C.
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110
200
100
180
90
160
80
70
C. 60
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The effect of pressure on etch depth and dc self-bias
voltage is shown in Fig. 2. All process conditions except
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---k-- DC self-bias
100
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120
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Pressure (mTorr)
(a)
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120
Figure 1 shows etch rate versus etch time for 100 ttm via
hole patterns at a pressure of 150 mTorr, a rf power of 110
W, a substrate temperature of 20 "C, and gas flow rates for
BCl3 at 11.4 sccm and for C1 2 at 12.3 seem, The etch rate
is higher than 7 /tm/min up to an etched depth of - 40
/tID, and then drops continuously to 4 /lm/min at an
etched depth of 100 /lm. The decrease in etch rate at an
increased etch depth is due to the decrease in effectiveness
of supplying reactive species and of removing etch byproducts.
.&J
40
10
>
HIO
50
20
140
increased Cl2 content, and the BC1 3/ Ar mixture shows the
slowest etch rate but has smooth surface profiles. So, a
BC1 3/C12/ Ar gas mixture is the best candidate for our purpose. A best process condition for the first etching step has
been found experimentally, and the results are summarized
in Figs. 1-8 .
0
160
(c)
(d)
(b)
2. Effect of pressure on etch depth and de self-bias voltage: (a) Etch depth and de self-bias versus pressure; SEM pictures of 100 Jim diameter holes
processed at (b) P=50 mTorr, (c) P= 100 mTorr, and (d) P= ISO mTorr. (BC1 3 = 11.4 seem, C1 2 = 12.3 seem, power= 110 W, '1'=20 'c, and time= 15
min.)
FIG.
J. Vac. ScI. Technol. S, Vol. 11, No.2, Mar/Apr 1993
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Chung et till.: Via hole process for GaAs MMIC
161
161
100~-------------------------------,
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Total flow rate (seem)
(a)
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(b)
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Wiliill!
(c)
FIG. 3. Effect of CI,/BCI 3 flow ratio on etch reaction: Ca) Etch depth vs
CI 2/BCI 3 flow rati; SEM pictures of 100 Itm diam holes processed at
Clz/BCI J flow ratio (b) 0.1 and (el 0.75. (P= 100 mTorr,
BCI 3 +CI 2 =23.7 secm, powef,.dlO W. T=20'C, and time=15 min.)
the process pressure are kept at the same conditions as
those in Fig. 1, and the etch depths are measured at 15
minof process time. When the pressure is increased, the
etch depth is increased but the dc self-bias voltage is decreased. The decrease in de self-bias voltage is due to increased collisional effects in the sheath region,ll and the
J. Vac. ScI. Technol.
FIG. 4. Etch depth vs total flow rate with C1 2:BC1}= 1:3.8.
increase in etch depth is due to an increased excitation of
reactive chlorine at higher pressure. Higher process pressure is preferred because the etch rate is higher. However,
the masking photoresist erodes faster, due to an increased
concentration of reactive chlorine, and etching becomes
less anisotropic at higher pressure due to both an increased
concentration of reactive chlorine and a reduced dc selfbias voltage. These effects are shown in the SEM pictures
of holes in Figs. 2(b)-2(d). The depth and the size of the
hole are 57.5 and 138 {.lm for 50 mTorr, 85.5 and 155.1 {.lm
for 100 mTorr, and 98 and 187.6 J-im for 150 mTorr. The
observed erosion of the masking photoresist is tolerable for
pressure <; 100 mTorr.
To examine the effect of ell/Bel} mixing ratio on etch
reaction, the ratio of flow rates is changed, while keeping
the total flow rate at 23.7 sccm. Figure 3(a) shows etch
depth at 15 min of process time versus el l /Bel 3 flow ratio.
Based on the results of Fig. 2, the process pressure has been
chosen at 100 mTorr. With BCl 3 only, the etch reaction is
very slow and the etch depth is only 6.7 j.tm. As the chlorine content increases, the etch depth is increased up to
80.1 /-tm at C1 2 :BC13 "", 1:4. However, further increase in
C1 2IBC1 3 flow ratio results in only a small increase in etch
depth, and the reason is that the generation of reactive
chlorine is limited by the rf power input. Also, an increased
supply of chlorine tends to make the etch reaction more
chemical,7,9 and the sidewall profile has sharp edges caused
by crystallographic etching. The top of hole is significantly
enlarged, as shown in Figs. 3(b) and 3(c). These problems
can be reduced by increasing either rf power or Bel} content. An increased BCl3 content is preferred because the
masking photoresist erodes raster with increased power.
So, we choose the flow ratio Clz:BC1 3 "", 1:4.
Figure 4 shows the effect of gas residence time on etch
process. The total flow has been changed while keeping the
Cl z/Bel 3 flow ratio at 0.26. The changes on etch depth for
15 min of process time are minor, showing that the gas
residence time is neither too long nor too short at 10-125
scem of total flow rate.
e, Vol. 11, Nc. 2, Mar/Apr 1993
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100
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Chung et al.: Via hole process for GaAs MMIC
162
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15
25
30
35
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Power (W)
(a)
•
Hi
IT
Mlil•
(b)
FIG. 6. Etch depth vs temperature with 100 W of rf power.
the etch depth also increases with power up to 100 W of rf
power (rf power density=O.44 W/cm2 ). Applying more
power results in slower etch rate, because of sputtering
effect of adsorbed reactive species before etching the
substrate. 4 SEM pictures of holes, etched with 50 and 145
W of rf power, are given in Figs. 5(b) and 5(c). At higher
rf power, the holes have smoother surface and better slope
for metallization.
The effect of substrate temperature is shown in Fig. 6.
The etch rate is slowly decreasing with increasing temperature, contrary to the usual etch process. Usually, etch rate
increases with temperature because of increased etch reaction and effectiveness of removal of etch by-products at
higher temperature. A possible explanation may be that the
increase in etch reaction of reactive species is hindered by
the increased formation of surface coating layer of Bel 3
120
---<>- Without Ar
100
E
- - - - With Ar
80
~
s:;
(c)
a.
60
CD
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FIG,S. Effect of rf power: (al Etch depth and de self-bias voltage vs rf
power; SEM pictures of 100 {LID diam holes processed at (b) 50 Wand
(e) 145 W of rf power, (P=lOO mTorr, T=20°C, time=15 min,
Cl2 :BCl}= 1:3,8, and BCl}=37,6 seem,)
,;::.
(,)
W
40
20
OL-&-~
The effect of rf power is shown in Fig. 5. The flow rate
of BCl3 has been increased to 37.6 seem for the intension of
increasing etch anisotropy, while maintaining the ratio
C1 2:BC1 3 = 1:3.8. As shown in Fig. 5(a), the dc self-bias
increases in proportion to the increase of rf power. Due to
an increased excitation of reactive species at higher power,
o
5
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~
15
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~~~~
20
25
__
30
L-~
35
Etch time (min)
FIG. 7, Averaged eteh depth vs time with and without argon. Process
conditions are BC1)=37.6 seem, CI 2 =9.8 seem, P=lOO mTon, power
= 100 W, T= 35 "C, and Ar=O or 10 seem,
J. Vac. Sci. Technol. S, Vol. 11, No.2, Mar/Apr 1993
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163
,
Chung et sl.: Via hole process for GaAs MMIC
12
163
GaAs
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16
,
18
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22
24
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28
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Binding energy (a V)
(a)
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GaAs
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35°C
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(b)
FIG. 8. Cross-sectional SEM pictures of a 100 p.m-deep hole on a GaAs
substrate (a) with Ar (10 seem) and (b) without Ar. (BCI 3 =37.6 secm,
CI 2 =9.8 seem, P= 100 mTorr, power = 100 W, and T=35 'C.)
by-products with temperature. Based on this speculation,
we choose the substrate temperature at 35 °e for better
etch anisotropy.
Based on these results, the best process parameters are
chosen: a pressure of 100 mTorr, a substrate temperature
of 35 °e, flow rates of Bel 3 at 37.6 sccm and of el 2 at 9.8
sccm, and a rf power of 100 W, corresponding to a dc
self-bias voltage of ~ 140 V. Averaged experimental results
at this process condition are given in Fig. 7. At 30 min of
process time, the etched depths are ~ 100 /lm for the
without-argon case and ~ 90 /lm for the with-argon case.
Without argon, the process is very unstable due to an excessive supply of Be1 3, and the observed data are scattered
in the range of - 60% to + 10% of the averaged value,
The process reproducibility can be improved appreciably
by adding 10 seem argon. The added argon gas increases
ion bombardment effects, decreases the chlorine concentration, and increases the de self-bias voltage to 190 V. Because of these effecis, the deviation on the observed etched
depth is less than ± 10% of the averaged value, and the
etched sidewall profiles show a reproducible smoother profile with less undercutting, as shown in Figs. 8 (a) and
8(b).
9. ESCA data of the second step etching with temperature as a
parameter.
FIG.
We use the above process condition for the first etching
step, down to a depth of - 90 Jim to avoid etching of the
metal layers. Then, a selective etching of GaAs substrate
with respect to a thin chromium layer follows. For the
J. Vac. Sci. Techno\. B, Vol. 11, No. 2, Mar/Apr 1993
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164
Chung et afo: Via hole process for GaAs MMIC
164
file and a flat exposed metal bottom surface, as required for
reliable via connections. The via holes are first sputtered
with gold of thickness - 500 A. and then electroplated with
gold to a thickness of - 20 fun. A SEM picture is given in
Fig. 10 (b). Measured resistances of via connections from
their 1-V characteristics are less than several hundred milliohms, showing that the via connections are good enough
for MMIC application.
(a)
IV. SUMMARY
A fast, reproducible, and reliable via hole dry etching
process for GaAs MMIC fabrication is established. Via
holes are formed from the back side of a 100 ILm thick
GaAs substrate. The etching process consists of two steps.
During the first etching step, BCI J:CI 2:Ar=3.8:1:1 gas
mixture is used to achieve high etch rate and small lateral
etching. Other process conditions for the first etching step
are a pressure of 100 mTorr, a rf power of 100 W, a substrate temperature of 35 "C, and an etching time of 25 min.
In the second etching step, CC12F 2 gas alone at 75 sccm is
used to achieve selective etching of the GaAs substrate
with respect to the front side metal layer (chromium) The
conditions for the second etching step are a pressure of 75
mTorr, a rf power of 50 W, a substrate temperature of 5 "C,
and an etching time of 15 min. The fabricated via holes are
electroplated with gold (~20 pm thick) to form the via
connections. The fabricated via hole profile and the hole
surface morphology are satisfactory for reproducible and
reliable MMIC via connections.
0
(b)
ACKNOWLEDGMENTS
FIG. 10. SEM pictures of a two step etched via hole; (a) cross-sectional
view: (b) top view after gold plating. (1st step: BCI 3 :CI2 :Ar=3.8:1:1,
BCJ 3 =37.6 secm, P=lOO mTorr, power=l00 W, T=3S"C, and
time=25 min. 2nd step: CC1 2F 2 =75 sccm, P=75 mTorr, power = 50 W,
T=5"C, time = 15 min.)
This work has been supported partially by Research
Institute of Industrial Science and Technology, and partially by Korea Electronics and Telecommunications Research Institute.
second etching step, only CC1 2F 2 gas is used. The process
conditions are a pressure of 75 mTorr, a substrate temperature of 5°C, a flow rate of 75 seem for CCI2F z• and a rf
power of 50 W corresponding to a dc self-bias voltage of 30
V. These process conditions are chosen to reduce any physical etching while minimizing polymer deposition of
CC1 2F 2 by-products. The substrate temperature is lowered
to suppress the reaction forming GaFJ' as indicated on
chemical analysis (ESCA) data in Fig. 9, which is less
volatile than GaC1 3• 10,ll
A fabricated 100 pm via hole, which has been etched for
25 min in the first step and 15 min in the second step, is
shown in Fig. lO(a). This hole has a smooth sidewall pro-
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J. Vac. ScI. Technol. S, Vol. 11, No.2, Mar/Apr 1993
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