2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, TX, USA, June 6-8, 2004, pp. 277-280
Derivation of Single-Ended CMOS Inverter Ring Oscillator
Close-In Phase Noise from Basic Circuit and Device Properties
Markus Grözing and Manfred Berroth
Institute of Electrical and Optical Communication Engineering
University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
Abstract — A closed-form expression of close-in phase
noise is derived for single-ended CMOS inverter ring
oscillators. Close-in phase noise is expressed depending on the
MOSFETs’ channel length Leff, the oscillator stage number n,
the NMOS and PMOS flicker noise coefficients KFN and KFP
and the peak currents ÎDN and ÎDP that discharge and charge
the node capacitances. Design implications regarding stage
number n and gate length L are derived and verified by
measurements. Further, the dependency of close-in phase
noise on inverter symmetry is investigated. An optimum ratio
of PMOS to NMOS channel width is derived and shown to be
dependent on KFN and KFP. The derived optimum ratio
substantially deviates from the value for waveform symmetry.
This characteristic is also confirmed by measurements.
I. INTRODUCTION
The noise spectrum of an electrical oscillator can be
divided into three regions with the noise power shaped
i3
i2
~ 1/∆f , ~1/∆f and a constant noise floor, respectively [1].
Close to the carrier, phase noise is dominated by
upconverted 1/f-noise and the noise power is shaped
i3
~ 1/∆f . Due to the large 1/f-noise of short-channel
MOSFETs and the lack of passive resonant elements,
i3
CMOS ring oscillators tend to have a wide 1/∆f -region.
This paper concentrates on deriving an expression of phase
noise for this region and on achieving some design
guidelines for CMOS inverter ring oscillators (fig.1).
II. CLOSE-IN PHASE NOISE THEORY
The basic idea is to regard close-in phase noise as a
result of the low frequency fluctuations of the CMOS
inverter propagation delays. The delay fluctuations again
are caused by the fluctuations of the MOSFET drain
currents (due to low-frequency noise), that charge and
discharge the node capacitances.
The rise and fall times of CMOS inverter gates can be
expressed as
C V
C V
(1)
t HL = node DD , t LH = node DD ,
Î DN
Î DP
where ÎDN and ÎDP are the average peaks (average referred
to the time interval tHL or tLH) of the NMOS and PMOS
drain currents iDN and iDP that discharge and charge the
VDD
P1
P2
P3
0V
N1
N2
N3
Fig. 1.
Pn
iDPn
iDNn vn
Nn
Cnode
Single-ended CMOS inverter ring oscillator
node capacitance Cnode, respectively. A rough estimate of
the propagation delays for falling and rising edges is [2]
(2)
t pHL = 1 2 t HL , t pLH = 1 2 t LH .
The cycle time T of a CMOS inverter ring oscillator with n
stages is the sum of all falling- and rising-edge
propagation delays:
T=
n
∑ (t
pHLi
+ t pLHi ) .
(3)
i =1
Now, the effect of low frequency current noise on the
phase deviation φ(t) shall be examined in the time-domain.
Low frequency MOSFET drain current noise can be seen
as a low frequency modulation of the average peak drain
currents ÎDNi(t) and ÎDPi(t):
Î DN , Pi ( t ) = Î DN , P (1 + n IN , Pi ( t ) ) .
(4)
The current ÎDN,P represents the nominal average peak
current of the NMOS or PMOS and nIN,Pi(t) represents the
normalized, time-dependent deviation from the nominal
value in stage i due to low-frequency drain current noise.
Following (1), (2), (4) and using the relation 1/(1+x) ≈ 1-x
for x << 1, the time-dependent “noisy” propagation delay
is
C V
t pHLi ( t ) = node DD (1 − n INi ( t ) ) = t pHL (1 − n INi ( t ) ) . (5)
2 Î DN
The delay tpLHi can be expressed accordingly using ÎDP and
nIPi(t). The time-dependent cycle time reads
T( t ) =
n
∑ (t (1 − n
pHL
i =1
INi
( t ) ) + t pLH (1 − n IPi ( t ) )) .
(6)
The cycle time T(t) can be decomposed into a nominal
value T0 and a time dependant varying value ∆Tcycle(t):
T ( t ) = T0 + ∆Tcycle ( t ) ,
(7)
2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, TX, USA, June 6-8, 2004, pp. 277-280
T0 =
n
∑ (t
+ t pLH ) = n (t pHL + t pLH ) = 2n t p ,
pHL
i =1
∆Tcycle ( t ) = −
n
∑ (t
pHL
i =1
n INi ( t ) + t pLH n IPi ( t ) ) .
(8)
(9)
The time-dependent deviation of the zero-crossing time of
a certain oscillator signal from its nominal value is
t
∆Tcycle ( τ)
∆Tzcro ( t ) =
∆Tcycle ≈
dτ .
(10)
T0
all cycles
0
∑
∫
since t = 0
The corresponding phase deviation is given by
t
φ( t ) = 2π
=−
∆Tzcro ( t ) 2π
= 2 ∆Tcycle ( τ) dτ
T0
T0 0
∫
2π
T02
t
n
∫ ∑ (t
0 i =1
pHL
n INi ( τ) + t pLH n IPi ( τ) )dτ .
(00)
(11)
To deduce a expression of phase noise, an oscillator with
only one noisy NMOS in a certain stage shall be
considered. To simplify the calculations, the power density
spectrum of the normalized low-frequency drain current
noise is at first assumed to have to discrete lines at ± fm:
n 2IN ( ∆f ) = n 2IN (δ(∆f − f m ) + δ(∆f + f m )) .
(14)
The single-sideband phase noise …(fm) of a signal with
phase φ(t) = φPsin(ωmt) was shown to be equal to φP2/4 [3].
Therefore, the normalized NMOS drain current noise with
2
a continuous power spectral density nIN (∆f) causes singlesideband phase noise given by
2
2
2 2
f 02 t pHL 2
φ2 (2 π ) t pHL n IN ( ∆f )
£ ( ∆f ) = P =
=
n IN ( ∆f ) .(15)
4
T04
∆ω2
∆f 2 T02
With (8), (15) and all n NMOS and PMOS noise powers
added, …(∆f) is given by
2

t 2pLH 2
f 1  t pHL 2
∆
+
n IP ( ∆f )  . (16)
£ ( ∆f ) =
n
(
f
)
IN
2
2
2

∆f n  t
tp
 p

Now, (16) shall be transformed to a shape where the
influence of the average peak currents is observable. The
propagation delays tpHL, tpLH and t p can be resubstituted:
2
0
t pHL
C V
C V
= node DD , t pLH = node DD ,
2 Î DN
2 Î DP
tp =
1
2
(t
pHL
+ t pLH ) =
C node VDD
2I D
.
(
(17)
(18)
)
The drain current 1/f noise spectral density SID(∆f) of a
DC-biased MOSFET can be modeled as follows [4]:
KF I AF
(20)
SID ( ∆f ) = EF D 2 .
∆f C ox Leff
Usually, EF = AF = 1 holds and KF is a technology
dependent parameter. The normalized power spectral
2
density nI(∆f) relates SID(∆f) to ID :
S ( ∆f ) 1
KF
.
(21)
n 2I ( ∆f ) = ID 2
=
ID
I D ∆f Cox L2eff
As the currents iDN(t) and iDP(t) in the oscillator can be
approximated as square waves, their normalized power
spectral density nI(∆f) is equal to the DC-case for
∆f << f0. Thus, ID can be replaced by ÎD. With (17) to (21)
and LNeff = LPeff = Leff, (16) reads:
£( ∆f ) =
(12)
The according time-domain normalized noise current is
n IN ( t ) = 2n IN cos(ωm t ) .
(13)
With (11), the corresponding phase deviation is
2 π t pHL 2 n IN
φ( t ) = − 2
sin( ωm t ) = φ P sin( ωm t ) .
ωm
T0
The value I D is equal to the DC-current consumption IDC,
that is governed by the periodic charging of nÂCnode:
−1
C V
−1
I D = 2 Î DN
+ Î −DP1
= node DD = nf 0 C node VDD = I DC .(19)
2t p
f 02 1  I 2DC KFN I 2DC KFP 
1


+ 2
2
2
2


n
Î
Î
∆f
Î DP DP  ∆f C ox L eff
 Î DN DN
3
3


I 
 KFN +  DC  KFP  . (22)

 Î 


 DP 

To do a fair comparison of oscillators with different IDC
and f0, a normalized phase noise value (also called figure
of merit) …norm(∆f) can be calculated and decomposed into
four multipliers M1 to M4:
=
2
1
1  f 0   I DC



∆f C ox L2eff n I DC  ∆f   Î DN

2
 ∆f
£ norm ( ∆f ) = £( ∆f )
 f0
 I DC VDD

 1mW
1
VDD
1
=
⋅
⋅ 2
∆f C ox 1mW nL eff
 I
⋅  DC
 Î DN

= M1 ⋅
⋅
M2
⋅ M3
3
3

I 

 KFN +  DC  KFP 
 Î 


 DP 


M4.
(23)
The smaller …norm, the better the oscillator. Multiplier M1
and thus …norm is still a function of frequency offset ∆f, it
has a -10dB/decade slope. This is important to keep in
i3
mind when comparing oscillators in the 1/∆f -region.
III. DESIGN IMPLICATIONS
The second multiplier M2 in (23) is usually given by the
technology. Only the multipliers M3 and M4 can be
optimized by the circuit designer. M3 is determined by
stage number n and gate length Leff. M4 gives a hint on the
dimensioning of the NMOS and PMOS peak currents.
2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, TX, USA, June 6-8, 2004, pp. 277-280
A. Enlargement of Cnode , n or Leff
B. Influence of PMOS to NMOS gate width ratio WP/WN
The following considerations are starting from a
oscillator with a high oscillation frequency f0. It has a
small stage number n0 and comprises MOSFETs with
minimum gate length Leff0. Moreover, the inverters are
symmetric, i.e. WP = µN/µP WN. The design goal is to
implement a oscillator with a lower oscillation frequency f1
and with the same DC-current consumption IDC. Different
implementation strategies are compared in respect to their
influence on …norm.
Strategy “C”: The node capacitance Cnode is increased
from Cnode0 to CnodeC by an additional capacitor:
The multiplier M4 in equation (23) can be transformed to
reveal the influence of PMOS and NMOS channel width.
With the average peak drain current ÎD proportional to gate
width W and carrier mobility µ, the following values can
be defined:
f1 C node 0
.
=
f 0 C nodeC
(24)
According to (19), (23) and (24), the DC-current IDC stays
constant and …norm is not affected:
£ norm C = £ norm 0 .
(25)
Strategy “N”: The stage number n0 is increased to nN:
f1 n 0
.
=
f0 n N
(26)
Again, the IDC stays constant, but …norm is decreased:
n
f
(27)
£ norm N = £ norm 0  0  = £ norm C  1  .
n
N

 f0 
Strategy “WL”: The channel length L is increased. To
keep the peak drain currents and IDC constant, the channel
width W is increased by the same factor (W ~ Leff).
2
Therefore, the channel area increases ~ Leff . The node
capacity Cnode is composed of the gate capacity
CG (~ WLeff2 ~ Leff2) and some parasitic capacitors
CP (usually ~ W ~ Leff). Therefore, as f ~ 1/Cnode:
m
f1  Leff 0 
 , 1 < m < 2.
(28)
=
f 0  LeffWL 
The exponent tends towards 2 for CG >> CP and towards 1
for CG << CP. According to (23), …norm is decreased:
2
2
L
 =£
 f1  m . (29)
£ norm WL = £ norm 0  eff 0


norm 0 
L
effWL 

 f0 
The exponent 2/m is at least one (CG >> CP) and at most
two (CG << CP).
As can be seen from (25), (27) and (29), the multiplier
M3 (and thus …norm) is most decreased with strategy WL. For
small channel area (CG << CP), …norm is lowered by 6 dB if
Leff is doubled. For large channel area (CG >> CP), …norm is
lowered by 3 dB if Leff is doubled. Strategy N is then as
effective as the strategy WL. …norm is lowered by 3 dB if n is
doubled. The worst strategy is C, because …norm stays
constant when Cnode is increased.
[
µW = 2 (µ N WN ) + (µ P WP )
w effN =
µ N WN
µW
-1
=
]
−1 −1
−1
Î DN
ID
, w effP =
,
(30)
µ P WP
µW
=
Î DP
ID
.
(31)
-1
With weffP = 2 - weffN , the multiplier M4 of (23) reads:
 1
£ norm ( ∆f ) = K ⋅ 
 w effN
K=
3


1
 KFN +  2 −
w effN


3


 KFP  ,(32)


1
VDD
1
⋅
⋅ 2 .
∆f C ox 1mW nL eff
(33)
To find the minimum, …norm is differentiated:
∂ £ norm
 1
∂ 
 w effN
  1
= K ⋅ 3

  w effN


2
2


 1 
 KFN − 3
 KFP  . (34)


 w effP 
The minimum …norm-value is obtained for
w effP
µ W
= P P =
w effN µ N WN
KFP
.
KFN
(35)
Thus, with KF ~ µNot [4], the optimum WP/WN ratio is
 WP 
µ

 = N
 WN  opt µ P
KFP
µN
=
KFN
µP
N otP
.
N otN
(36)
NotN,P is the effective oxide trap density in the NMOS and
PMOS transistor, respectively.
In [5], waveform symmetry is said to lower the
upconversion of device 1/f-noise to phase noise. But the
value (WP/WN)sym for waveform symmetry (i.e. tpHL = tpLH),
approximately given by
 WP

 WN

µ
 = N ,
sym µ P
(37)
substantially deviates from the value (WP/WN)opt derived
here. WP has to be decreased in comparison to the
symmetric inverter, even if the trap densities of the PMOS
and NMOS transistors are equal. If NotP < NotN, as observed
in [4], WP has to be decreased further. A commonsense
explanation is as follows: If the PMOS has lower 1/f-noise
than the NMOS, it’s contribution to the cycle time T0 has
to be increased. Thus tpLH should be larger than the more
“noisy” tpHL and WP has to be decreased.
2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Fort Worth, TX, USA, June 6-8, 2004, pp. 277-280
III. MEASUREMENT RESULTS
A. Oscillators according to strategy C, N, WL
phase noise … [dBc/Hz]
-70
C
-80
N
WL
-90
perform slightly better. Accordingly, the optimum ratio
(WP/WN)opt should be somewhere in between 0.4 and 2.7.
This result confirms that waveform symmetry is not the
optimum for CMOS inverter ring oscillator phase noise
performance and that the PMOS portion of the total delay
must be larger than the NMOS portion. The noise
advantage of PMOS transistors in ring oscillators
coincides with measurements of LC-oscillators [7].
osc. spl. WP
WN
N
A 2.7
N
B 0.4
Q A 2.7
Q
B 2.7
-100
-110
1.0E +05
1.0E +06
frequency offset ∆ f [H z]
1.0E +07
Figure 2. Measured … against ∆f with 1/∆f3-trend lines
L
Lmin
C
1
N
1
WL 2
2.50
2.15
2.25
-83.1
-90.0
-92.1
2.15
1.60
3.39
3.02
-98.6
-99.8
-90.5
-90.4
-156.7
-157.0
-149.5
-148.2
+
n VDD IDD
fosz
*)
norm *)
[V] [mA] [GHz] [dBc/Hz] [dBc/Hz]
3 1.82 3.78
9 1.84 3.87
3 1.84 3.56
9 1.84 3.87
7 1.87 2.61
4# 1.8 7.95+
#
+
4 2.0 7.63
Table 2. Comparison of ring and quadrature oscillators
The three oscillators with symmetrical inverters were
realized in 0.18 µm standard CMOS technology. Figure 2
shows the measured phase noise and table 1 summarizes
the results. Compared to the C-oscillator, …norm is 5 dB
lower for the N-oscillator with tripled number of stages.
The improvement expected by theory is 10[log(3) = 4.8
dB. …norm is 8 dB lower for the oscillator with doubled
2
channel length. The expected value is 10[log(2 ) = 6.0 dB
for CG << CP. As Leff < L, the expected value is probably
underestimated.
osc.
n VDD IDD
fosz
*) …norm *)
[V] [mA] [GHz] [dBc/Hz] [dBc/Hz]
-148.7
-154.1
-156.9
Table 1. Ring oscillator C, N and WL measurement results.
*) measured and calculated @ ∆f = 500 kHz
B. Oscillators with different gate width ratio WP/WN
Two oscillators with different WP/WN ratio were
processed by different manufacturers, but both using
0.18 µm standard CMOS technology. To detect possible
differences in the device 1/f-performance of the two
technologies, the …norm-values of quadrature ring oscillators
(Q-oscillators, [6]) - realized in both technologies with the
same device dimensions - were compared. Table 2
summarizes the results. The Q-oscillator processed by
supplier A performs 1 dB better than the one processed by
B. The …norm-value of the N-oscillator with severe
unsymmetrical inverters (WP/WN = 0.4, supplier B) is equal
to the …norm-value of the N-oscillator with symmetrical
inverters (WP/WN ≈ µN/µP ≈ 2.7, supplier A), even though
the stage number is smaller and supplier A seems to
) simulation result, #) additional feedforward stages
*) measured and calculated @ ∆f = 1 MHz
V. CONCLUSION
Single-ended CMOS inverter ring oscillator close-in
phase noise performance can be optimized either by
enlarging the stage number or, even better, by enlarging
the channel length. The normalized phase noise was
measured to be 5 dB lower for a oscillator with tripled
number of stages and 8 dB lower for a oscillator with
doubled gate length compared to a oscillator that has
enlarged node capacitors. The optimum gate width ratio
WP/WN is shown to be determined by the flicker noise
coefficients KFN and KFP. As KFP usually is lower than
KFN, the PMOS width has to be decreased compared to a
symmetrical CMOS inverter design.
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