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Features .............................................................. 1
Applications ......................................................... 1
Pin Assignments.................................................. 1
Block Diagram ..................................................... 1
Timer Setting ....................................................... 2
Operation............................................................. 2
Absolute Maximum Ratings ................................. 3
Electrical Characteristics ..................................... 3
AC Electrical Characteristics ............................... 4
Notes ................................................................. 4
Acceleration Test Mode ....................................... 5
Application Circuit Example ................................. 6
Characteristics..................................................... 7
Dimensions.......................................................... 9
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Contents
Rev.1.1
S-8081B
CR TIMER
The S-8081B is a CMOS CR timer developed for appliances and
industrial equipment use. It consists of a CR oscillator, a 20-stage
divider, a power-on clear circuit, a trigger input chattering rejection
circuit, an internal voltage regulator, a level shift circuit, and an output
driver. It can be used as a high-precision, long-time monostable timer.
n Applications
• Time switch
• Long time delay generator
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• Wide power supply operating range : 4.5 to 16.5 V
• Low current consumption : 200 µA max.(C = 200 kΩ,
R = 0.0047 µF, open output )
• Time can be set by external CR
• Excellent oscillation stability because of built-in voltage regulator
• Power-on clear circuit is integrated
• Both trigger I/O inverting operation and set/reset operation can be
performed
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n Features
n Pin Assignment
1
SET
2
8
S−8081B
3
RESET
4
7
CR
6
DISCHARGE
5
TRIGGER
ON
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OUT
VDD
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VSS
D
8-pin DIP/SOP
Top view
Figure 1
n Block Diagram
SC
CR 7
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DIS- 6
CHARGE
TRIGGER 5
SET
RESET
Oscillation
circuit
20 - stage FF
FF20
tOUT
select
Input chattering
rejection circuit
2
Input
circuit
4
Input
circuit
Output
Control logic
3
OUT
Power ON
clear circuit
8
VDD
Voltage
regulator
1
VSS
level shift
Figure 2
Seiko Instruments Inc.
1
CR TIMER
S-8081 B
n Timer Setting
The timer time tOUT is decided by an external resistor RT and an external capacitor CT.
tOUT=(K×RT×CT×219) sec.
K=time constant coefficient
10 s≤tOUT≤10 hours (recommended)
RT≥50 kΩ, CT≥100 pF (recommended)
Note : If other CT or RT is used than above recommended, the internal C and R influence tOUT and it becomes different
1
2
VSS
VDD
8
SET
CR
7
CT**
RT*
4
OUT
DISCH
RESET TRIG
Connect between VDD and CR
Connect between CR and DISCHARGE
CT :
RT :
* RT ≥50 kΩ
** CT≥100PF
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3
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in each unit.
5
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Figure 3 Connection of external CT and RT
TRIGGER
tOUT
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OUT
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tOUT
RESET
Figure 4 TRIGGER operation timing chart
OUT
tOUT
RESET
ON
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SET
tOUT
n Operation
1. SET terminal
tOUT=tOSC×2
tOSC≈K×RT×CT
19
(Recommended : RT≥50 kΩ, CT≥100 pF)
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Figure 5 SET operation timing chart
At the rise of SET terminal, OUT goes high (VDD) and frequency dividing operation starts.
This terminal has a pull-down resistor built in.
2. RESET terminal
By bringing RESET terminal high (VDD), OUT goes low (VSS) and the internal counter is reset.
Set or trigger input is ignored when reset is high.
This terminal has a pull-down resistor built in.
2
Seiko Instruments Inc.
CR TIMER
S-8081 B
3. TRIGGER terminal
At the rise of TRIGGER terminal, OUT level is inverted. When OUT changes from low (VSS) to high (VDD),
frequency dividing operation starts. When OUT changes from high (VDD) to low (VSS), the internal counter is
reset. When starting TRIGGER operation during setting operation, reset the S-8081B before TRIGGER input. This
terminal has a chattering rejection circuit and a pull-down resistor built in.
Chattering rejection time ≈ tosc×7
4. CR and DISCHARGE terminals
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CR oscillation circuit can be constructed by connecting a timing capacitor CT between VDD and CR terminals, and
by connecting a timing resistor RT between CR and DISCHARGE terminals.
Set the oscillation period (tosc) following the formula below.
tOSC ≈ K×RT×CT
K : time constant coefficient
5. OUT terminal
OD
At the rise of SET or TRIGGER terminal, OUT goes high (VDD) and frequency dividing operation starts. OUT goes
low (VSS) after tosc ×219.
When OUT is high (VDD) if TRIGGER rises or RESET goes high (VDD), OUT goes low (VSS) and the internal counter
is reset.
PR
n Absolute Maximum Ratings
Table 1
Unless otherwise specified: Ta=25°C
Parameter
Parameter
Operating power supply voltage
Operating current consumption
SC
SET, RESET, TRIGGER input
pull-down resistance
High level input voltage
Low level input voltage
High level output current
Low level output current
Low level output voltage
VSS = 0 V
D
VDD
VIN, VOUT
Topr
Tstg
PD
ON
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n Electrical Characteristics
Conditions
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Power supply voltage
Input/output voltage*
Operating temperature
Storage temperature
Power dissipation
Symbol
at 25°C
Conditions
Min.
Typ.
Max.
Unit
4.5

16.5
V
R=200 kΩ Open output
C=0.0047 µF


200
µA
VIH=VDD
50

400
kΩ
0.8×VDD
VSS
10
20



15
30

VDD
0.2×VDD


0.4
1.276
1.450
1.624


0.05

%/V

0.10

%/°C
VIH
VIL
IOH
IOL
VOL
VOH=5.7 V VDD=8.0 V
VOL=2.3 V VDD=8.0 V
VDD=5.0 V IOUT=3.2 mA
C=0.0047 µF
Time constant coefficent
K
R=200 kΩ
VDD=4.5 to 16 V
Power
supply
voltage  f/fosc
C=0.0047 µF
fluctuation*
/ VDD
CR
R=200 kΩ
Ta=−20 to +60°C
 f/fosc
osc
Temperature fluctuation*
C=0.0047 µF
/ T
R=200 kΩ
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V
VSS−0.3 to VDD+0.3
V
−30 to+85
°C
−40 to+125
°C
300
mW
* Excluding DISCHARGE terminal
VDD = 12 V, VSS = 0 V, Ta = 25°C
VDD
Rdown
Unit
Table 2
Symbol
IDD
Ratings
V
mA
V
* Fluctuation of IC only
Seiko Instruments Inc.
3
CR TIMER
S-8081 B
n AC Electrical Characteristics
1. Input signal timing
Table 3
Symbol
Min.
Typ.
Max.
Unit
10
10
16×tOSC
10
10
10
tT+10
10
















µs
µs
µs
µs
µs
µs
µs
µs
10


µs
OD
SET pulse width
tS
RESET pulse width
tR
TRIG pulse width
tT
RESET-SET pulse interval
tRS
RESET-TRIG pulse interval
tRT
TRIG pulse interval
tTT
SET input timing
tTS
Pulse interval between timer
tOS
operation finish and SET
Pulse interval between timer
tOT
operation finish and TRIG
tOSC : oscillating frequency, (tOSC=K×RT×CT)
SET
PR
RESET
TRIG
tS
tR
tT
tRS
D
OUT
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Parameter
VDD=12 V, VSS=0 V, Ta=25 °C
tRT
tTS
tOS
tTT
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RESET input has the precedence over SET or TRIG input.
Figure 6
2. TRIG input pulse width and operation status
ON
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Table 4
VDD=12 V, VSS=0 V, Ta=25 °C
TRIG input pulse width
Operation
n Notes
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1. Notes on operation
TRIG operation
Indefinite*
No TRIG operation
SC
TRIG input pulse width≥16×tOSC
7×tOSC<TRIG input pulse width<16×tOSC
TRIG input pulse width≤7×tOSC
*TRIG operation does not always start.
tOSC : oscillating frequency
• Do not start TRIGGER operation during setting operation (see Figure 7). When starting TRIGGER operation during
setting operation, reset the S-8081B before TRIGGER input.
• Do not set the RESET terminal high while SET or TRIGGER terminal is at high level. Or, the S-8081B will enter
acceleration test mode. (see Figure 8)
SET
SET or
TRIGGER
TRIGGER
RESET
OUT
OUT
Figure 7
4
Figure 8
Seiko Instruments Inc.
CR TIMER
S-8081 B
2. Status just after power-ON
A power-on clear circuit is built in the S-8081B and it initializes this IC at power-ON. During initialization, the S-8081B
does not perform normal operation. Initialization time can not be defined clearly because it differs according to the
voltage fluctuation at power-ON. See Table 5 for reference. Pay sufficient attention to the operation just after powerON.
Table 5
Rise time
Initialization time*
<1 ms
1 ms
≥1 ms
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*
Time duration from power-ON to the time
when VDD reaches 4.5 V.
Time duration from power-ON. At this time, the S-8081B does not
operate normally.
3. CR oscillation
OD
CR oscillation circuit is always operating while power supply voltage is applied.
4. VIH level of input signal
PR
When pulling up the SET, RESET or TRIGGER terminal, pay attention to VIH level because they have pull-down
resistors built in.
n Acceleration Test Mode
This mode is performed
D
The S-8081B has the acceleration test mode to check its F. F. function in a short time.
as follows.
ON
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(1) Put SET terminal from low to high level.
(2) After (1), put RESET terminal from low to high level.
(3) With keeping (1) and (2) status, input 511 clocks whose levels are the same as VDD from CR terminal.
(From 1st to 9th and from 11th to 19th stages of 20-stage F.F. are all high. The 20-stage F.F. starts operation at
the falling of input signal.)
(4) Put RESET terminal low.
(5) Put SET terminal low.
(6) Input 514th clock from CR terminal.
(7) 20th stage of the 20-stage F.F. goes high from low, and the OUT terminal goes low.
SET
CR
CLOCK
input
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OUT
1
2
SC
RESET
510
511
512
513
514
1024
1025
Figure 9
When releasing from acceleration test mode, initialize the S-8081B according to (a) or (b) below.
(a) Turn the power off, and on again.
(b) Put RESET terminal high level.
Seiko Instruments Inc.
5
CR TIMER
S-8081 B
n Application Circuit Example
C
1
VSS
VDD
8
CT**
SET
CR
7
3
OUT
DISCH
6
RT*
hFE
100 min.
2
220 Ω
4
RESET TRIG
5
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Figure 10
6
*RT ≥ 50 kΩ
**CT ≥ 100 pF
Seiko Instruments Inc.
CR TIMER
S-8081 B
n Characteristics
1. Current consumption characteristics
IDD
1.2 Operating current consumption IDD Ambient temperature Ta
65
65
60
60
IDD
55
(µA)
(µA)
C=0.0047 µF
R=180 kΩ
Ta=25 °C
50
0
6.0
10
14
55
50
−40
18
VDD (V)
0
40
80 100
Ta (°C)
3. Oscillation frequency fOSC Ambient temperature Ta
900
C=0.0047 µF
R=180 kΩ
OD
2. Oscillation frequency f/fOSC Power supply voltage VDD
0.6
C=0.0047 µF
R=180 kΩ
Ta=25 °C
fOSC
PR
0.4
f/fOSC
C=0.0047 µF
R=180 kΩ
VDD=12 V
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1.1 Operating current consumption IDD Power supply voltage VDD
(Hz)
(%)
800
6.0
10
14
VDD (V)
18
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0
−40
80 100
Ta (°C)
* f/fOSC/ T is fluctuation of IC only.
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4. High level output current IOH Ambient temperature Ta
IOH
(mA)
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20
−40
0
40
0
40
5. Low level output current IOL Ambient temperature Ta
VDD=8.0 V
VOH=5.7 V
30
f/fOSC/ T*=0.053%/ °C
D
0.2
VDD=8.0 V
VOL=2.3 V
60
IOL 50
(mA)
40
30
−40
80 100
Ta ( °C)
Seiko Instruments Inc.
0
40
80 100
Ta ( °C)
7
CR TIMER
S-8081 B
6. Output Nch driver characteristics
0.8
Ta=25 °C
7. Output Pch driver characteristics
0.8
Ta=25 °C
VDD=5 V
0.6
Voltage
VDD=5 V
0.6
Voltage
between
VSS-OUT
(V) 0.4
between
VDD=8 V
VDD=8 V
VDD-OUT
0.4
(V)
VDD=12 V
0
2.0
4.0
VDD=12 V
0.2
6.0
8.0 10.0
IOL(mA)
0
1.0
8. Pull-down resistance Rdown - Ambient temperature Ta
100
Rdown
−40
0
40
80 100
Ta ( °C)
105
10. Oscillation frequency fOSC External resistance RT
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9. Oscillation frequency fOSC - External capacitance CT
R=180 kΩ
103
106
C=0.0047 µF
104
fOSC
ON
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fOSC
101
10−1
10−10
10−8
10−6
(Hz)
102
1
10−4
102
104
SC
CT (F)
11. Current consumption IDD External resistance RT
3
10
106
RT (Ω)
108
12. Current consumption IDD External Capacitance CT
90
C=0.0047µF
VDD=12 V
Ta=25 °C
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IDD
5.0
PR
60
40
(Hz)
4.0
D
(kΩ)
3.0
IOH(mA)
OD
80
2.0
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0.2
R=180 kΩ
VDD=12 V
Ta=25 °C
80
IDD
(µA)
70
(µA)
60
102
50
102
103
104
105
106
RT (Ω)
8
107
10−12
Seiko Instruments Inc.
10−11
10−10
10−9
10−8
CT (F)
10−7
8-pin SOP
FE008-B 990531
Dimensions
Unit:mm
5.0(5.15max)
5
1
4
0.15
+0.1
-0.05
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8
0.35
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1.27
+0.1
-0.05
DP00 -A 990531
8-pin DIP
Unit:mm
Dimensions
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9.3(9.6max)
1.5
7.62
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1.0
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2.54
0.5±0.1
0.3
+0.1
-0.05
0°~15°
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The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
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