Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Review of state-of-the-art solver solutions for HIL simulation
of power systems, power electronic and motor drives
Christian Dufour, Sébastien Cense, Vahid Jalili-Marandi, Jean Bélanger
Opal-RT Technologies
1751 Richardson, bureau 2525
Montréal, Québec, Canada, H3K 1G6
{christian.dufour, sebastien.cense, vahid.jalili-marandi, jean.belanger}@opal-rt.com
Keywords
Real-time simulation, Hardware-In-the-Loop simulation, HIL, motor drives, PMSM, SRM, power electronics.
Introduction
In this paper, we review state-of-the-art solvers and techniques applicable to HIL simulation of power systems,
power electronics and motor drives.
These methods can be distinguished by the applications as well as the computational hardware engines used.
Industrially speaking, there are two main types of hardware used today to make HIL: multi-core CPUs and FPGAs.
Other promising technologies like, GPU (and similar approaches such as Intel 100 cores ‘ Xeon phi’ coprocessors), are also possible and rather similar to multi-CPU approach but not discussed in this paper .
CPU vs. FPGA HIL overview
CPU-based HIL simulation is well-adapted to the HIL simulation of large systems involving complex solver
methods. They are typically closely linked to graphical programming languages, such as Simulink, and with
physical description simulation tools such as SimPowerSystems and Automated Code Generation software such as
Mathworks’ Real-Time Workshop, that provide a well-proven environment to make HIL experiments. One of the
main limitations of CPU-based HIL systems arise when trying to reach very high sampling rates: on PC-based realtime simulators, the PCIe transaction time limits the sampling rate well above 1 µs.
CPU algorithms are not limited to Electro-Magnetic Transient (EMT) real-time simulation such as in ARTEMiSSSN or HYPERSIM but also include real-time Transient Stability (TS), also known as phasor simulation.
FPGA-based HIL simulation is better adapted to the simulation of smaller systems with higher bandwidth: smaller
systems because typical FPGA systems can’t compete with CPUs in terms available memory and coding flexibility.
Higher bandwidth because FPGA models can run at very high sampling rates, below 1 µs typically, something that
CPU-based HIL methods cannot achieve today. The main reason for this HIL performance is that the system I/Os
are directly connected to the model, without the PCIe bus. One of the main drawbacks of FPGA models is that they
are much harder to code than their CPU counterparts and also impose some limits on the complexity of the solver
used.
HIL methods for power systems, motor drives and power electronic
CPU-based HIL solutions are the default choice to make HIL simulation of large models using complex solution
algorithms like ARTEMiS-SSN. The main disadvantages of CPU-based solutions is the relatively low sampling
frequency that than be achieved (5 µs in 2012) and relatively high I/O access latency. In many cases, however, it’s
possible to use interpolation or time-stamping of IGBT conduction times to obtain an equivalent sub-microsecond
resolution [2][7].
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Fig. 1. Respective advantages of HIL simulation on CPU and FPGA computational engines
On the FPGA, the situation is the opposite. FPGAs’ low coding abstraction level and architecture disqualify them
for the design of complex solvers and models that are possible on CPU. But these models are directly connected to
simulation I/O points so they result in very low latency. Also, FPGA models directly sample models containing
IGBT devices, so high accuracy power electronic model are easier to obtain on FPGA from this point of view.
Some applications require the use of both approaches such as HIL simulation of large MMC systems with
thousands of I/O points.
On CPUs, ARTEMiS-SSN[1][3] is a good example of a solution algorithm for power systems. It can also be used
for power electronics with the help of special interpolation techniques. SSN uses the state-space equations of a
model to build its nodal admittance equations. It can solve very complex models. HYPERSIM[4] and RTDS[5] are
other examples of very high-end CPU-based real-time power system simulators, based on the classic nodal
admittance, first described more than 40 years ago. HYPERSIM in particular makes automatic task parallelization
and especially well adapted for the simulation of very large power systems. Alternately, it’s also possible to
simulate motor drives on CPU using much simpler solvers, like interpolated switching-functions, often called
Time-Stamped Bridge (TSB) models. TSB can simulate 2-level and 3-level inverters very accurately and
efficiently, including special modes like non-pulsing/natural rectification models.
On FPGAs, the algorithmic solutions vary and are often limited by implementation issues. For example, making
divisions or doing iterations on FPGA it quite difficult. Small models can be solved using either nodal or statespace method, in both cases with precalculation of switch permutations. Other practical problems also arise, like
the very long time to generate a bitstream. More general solvers, like OPAL-RT’s ‘Electric Hardware Solver’
(eHS), have been reported also using a constant nodal admittance method[12]. Various motors (PMSM, SRM) can
also be designed on FPGA.
Multi-level Modular Converter case
The Multi-level Modular Converter (MMC) model is a type of voltage inverter that is rapidly gaining acceptance in
many applications, notably in HVDC systems. This type of device is singular in HIL simulation because of its
extremely high number of I/O points, typically in the thousands. In this regard, FPGA models can greatly simplify
the HIL simulation of such devices by allowing some kind of pre-processing of the numerous MMC cells’ I/O.
MMC can also be modeled in SSN, with the advantages of a straightforward nodal solver like SSN. For example,
natural rectifying modes are easier to simulate in a nodal admittance solver like SSN.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
We summarize the various algorithms and applications in Table 1.
Table 1: Summary of different solvers/method/models advantages and disadvantages on CPU and FPGA
CPU
Advantages
Disadvantages
State-Space Nodal (SSN) EMT
simulation
 Can simulate large and complex
networks, no switch limit, various
solvers, user-defined models,
interpolated inverter models, all faults
types supported, etc…
 Limited power electronic event
resolution: with state-space interpolation,
can handle some systems with 1-2kHz
PWM but is sensible to circuit
parameters.
HYPERSIM: Classic nodal
admittance solver EMT
simulation
 Same as SSN
 Limited power electronic simulation
capability. Potentially higher sample time
than SSN because of larger nodal
admittance matrix.
Interpolated Switching Functions
or ‘Time Stamped Bridge’ (TSB)
 Very fast, excellent accuracy. Support
for natural rectification and high
impedance modes.
 Not possible to model inverter individual
switch faults.
Multi-level converters (MMC)
 Exact delay-free modeling using SSN.
No high-impedance parameter tuning
required as for FPGA models.
 In practical HIL applications with
thousands of I/O points for IGBT gates,
FPGA methods are faster.
Real-time Transient Stability
simulation
 Very fast method for ultra-large systems
 Lower resolution than EMT simulation
 Automatic task allocation.
 I/O latency of CPU models (even if the
switching accuracy is similar to FPGA
models due to interpolation)
 Can be coupled with SSN simulation
FPGA
Custom Converters and Motor
Drive models
 Very high switching resolution
 Very low I/O latency (<1 µ)
 New topology configurations have to be
design by Opal-RT specialist
 Parameters can be changed bitstream
regeneration
 Can support most switch fault types
Electric Hardware Solver (eHS)
 User can design the circuit topology
without changing the bitstream
 Very high switching resolution
 Very low I/O latency (<1 µ)
 Requires tuning of the conductance
parameter of the Fixed Nodal Admittance
Matrix Method (FNAMN).
 The FNAMN can create numerical
oscillations at switching times.
 Parameters can be changed without
bitstream regeneration
 Can support most switch fault types
Multi-Level Converter (MMC)
 I/O capture and preprocessing of MMC
cells equations on FPGA - based on
switching functions
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 High-impedance mode require tuning
Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Power system and motor drive CPU-based HIL application examples
Interpolated CPU-based simulation of high-frequency PWM motor drives
The most ‘easy’ way to simulate a high-frequency PWM motor drive is by using interpolated switching functions
on CPU. When applied to inverters, this method is often called ‘Time-Stamped-Bridge’ or TSB.
This was used to make the HIL simulation industrial air conditioning drive in [7]. The motor was 10 kHz and PWM
frequency was around 10 kHz. This type of model, depicted in Fig. 2, can be made to support non-switching modes
like natural rectification or high-impedance mode. However, the method used to emulate the high-impedance mode
is prone to numerical stability because of the algebraic nature of TSB.
Fig. 2. A PMSM drive with AC-side circuit.
Bipolar HVDC system using ARTEMiS-SSN solver.
SSN is a nodal admittance-based solver built-in the ARTEMiS real-time plug-in for SimPowerSystems. SSN is
used to simulate a real complete 12-pulse bipolar HVDC link with switched filter banks[10]. This circuit represents
a 2000 MW (500 kV, 2 kA at each pole) HVDC link. The rectifier and the inverter are 12-pulse converters and the
link is bipolar. The rectifier and the inverter are interconnected through two lines using smoothing reactors. The
transformer tap changers are not simulated and fixed taps are assumed. Reactive power required by the converters
is provided by a set of capacitor banks plus 11th, 13th and high pass filters on each side. These capacitors and
filters can be switched; each station has 7 switched banks.
Line (300 km)
transfo
Switched filter banks
6-pulse
thyristor
rectifier
345kV
50 Hz
500kV
60 Hz
AC filters (600 MVars)
Line (300 km)
Fig. 3.
Bipolar 12-pulse HVDC link with switched filter banks
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
In Fig. 3, the SSN state-space groups are indicated by the colors. Stations (with 2 poles) on both sides of the lines
are simulated on two different cores of the RT-LAB simulator. On each side of the line, the SSN method results in
a nodal admittance matrix of size 19, a value much smaller than if the nodal admittance matrix would have been
assembled with all individual RLC branches.
The bipolar HVDC link with switched filters can be simulated at a time step of 49 µs on 3 cores of a 3.3 GHz PC
using RT-LAB.
Large motor drive simulation using SSN
In this section, we overview the HIL simulation models used to simulate the ACS 6000 medium voltage, variable
speed frequency converter manufactured by ABB[11]. It is used to feed high power induction and synchronous
motors in marine and industrial applications, and is designed to deliver a very high standard for reliability and
availability. The active rectifier unit (ARU) consists of a transformer connected to a 3-level neutral clamped
converter (NPC). With ACS 6000 a maximum of three ARU’s can be connected in parallel for higher drive power
rating resulting in 12-pulse or 18-pulse rectifier configurations. Unlike the traditional analog test stand, this
simulator allows an easy change of the different configurations that are possible with the ACS 6000, as multiple
rectifiers and motor inverters can be connected to the same DC bus, without needing to change the hardware setup.
Fig. 4. The HIL Configuration for the ABB ACS 6000 Triple ARU Drive
A complete triple ARU drive, depicted in Fig. 4, is composed of three zig-zag transformers in series, each
connected to a 3-level NPC inverter, and DC link with filters. An auxiliary circuit comprising a diode bridge is also
connected to the DC link for charging the DC bus before the drive starts. The DC link feeds another 3-level NPCbased induction motor drive. In the figure, a single SSN solver, with no delay, is used for the network, triple 3-level
NPC rectifier (CPUs 1, 2, 3, 4), the precharge circuit and motor inverter and simulated on other CPUs with a delay,
a very common decoupling technique in the presence in a large DC-link capacitor.
The controller under test is the original ACS 6000 control system, consisting of the different boards for control,
measurements and protection. Particularly, to test some novel control strategies, such as a Direct Torque Control
(DTC), the model must run in real-time with a sampling time no larger than 25 microseconds to ensure a correct
dynamic response. Such a constraint on the model sampling time is achieved by parallel computation of the drive
circuit on multiple-core CPUs using an innovative algorithm, called SSN method. The SSN algorithm is able to
seamlessly decouple the whole drive circuit that consists of a large amount of power electronic switches, so that it
is possible to distribute the computation on different cores, in parallel, to increase the total speed of calculation
without adding any delay.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
It was reported that the HIL simulation results of the steady-state operation points have been validated with the
corresponding measurements from the field, and the difference is less than 3%.
Real-time phasor simulation
Power systems transient stability (TS) simulation or phasor simulation is focused on the power system stability. In
this approach, the machines and the various controllers of a grid are described by their respective differential
equations, all connected by the grid itself, the latter being described by algebraic equation. This results in a set of
differential-algebraic equations (DAEs) as follows:
ẋ = f ( x ,V )
(1)
YV=I (x, V )
(2)
x (t0) = x0
(3)
where x is the vector of state variables, V and I are the vector of bus voltages and currents, Y is the nodal
admittance matrix of the network, and x0 is the initial values of state variables.
Fig. 5. IEEE 39 bus system scaled up 256 times for ePHASORsim simulation.
For transient stability simulation the transmission network is modeled in the main frequency phasor domain, and
the dynamics of the system only depend on rotating machines and control devices such as excitation system, power
system stabilizer, turbine and governor. Therefore, a simulation time-step in the order of few milliseconds to half of
a cycle is sufficient. Equation 1 describes the dynamic behavior of the system, while Eq. 2 describes the network
constraints on Eq. 1.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Because of the much larger time step used by the phasor method, a much larger network can be simulated in realtime. Events such as faults, OLTC tap changing, breaker actions can be made on the network and their effect
analyzed by this approach.
For example, a network such as the IEEE 39 bus system scaled up 256 times, resulting in a network of 20000 and
5000 more than generator can be simulated in real-time using this approach implanted in the OPAL-RT software
package ePHASORsim (see Table 2).
Table 2 ePHASORsim solver performances
Number of Bus
Number of Generators
Number of Controllers
Time to execute
one model step @ 10 ms
5000
1280
2304
2 ms
7000
1800
3240
3 ms
20000
5120
9216
8 ms
Motor drive and power electronic HIL example using FPGAs
Permanent Magnet Synchronous Motors and boost converter on FPGA
In [8], the FPGA implementation of a Permanent Magnet Synchronous Motor (PMSM) model using the latest
JMAG-RT Finite-Element-Analysis software’s real-time models: variable-DQ and Spatial Harmonic. In the
variable-DQ (VDQ) model, the DQ inductances are varied according to the saturation level and a sinusoidal backEMF is assumed. In the Spatial Harmonic (SH) model, the instantaneous magnetization state is used to integrate the
model; differential inductance and non-sinusoidal back-EMF are considered for all possible points of operation,
resulting in improved precision, especially in transient states. The SH model also includes torque and current
harmonics contents induced by machine slots and back-EMF spatial configurations. The VDQ and SH models,
together with a boost converter, are implemented in an ML605 FPGA board running in the RT-LAB real-time
simulation environment. The models are notably made with floating-point FPGA operators. In this model, the
PMSM motor has latencies of 150 ns (Variable DQ model) or 450 ns (full FEA model), while the boost converter
and IGBT inverter ran with 100ns and 150 ns respectively. The complete model is depicted in Fig. 6.
Fig. 6. Global architecture of dual SH-VDQ PMSM drive with boost converter using JMAG-RT
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Switched Reluctance Motor and bidirectional boost DC-DC converter on FPGA
In [13], we describe an FPGA implementation of a Switched Reluctance Motor Drive and a DC-DC bidirectional
boost converter targeted for HIL testing of modern hybrid electric vehicles (HEV). These FPGA models allow the
HIL simulation of SRM drive and boost converters with switching frequencies in the 50-100 kHz range because of
the very high FPGA sampling rate. The models are also integrated in the RT-LAB real-time environment and
directly linked with the simulator I/Os, providing ultra-low gate-to current latency. The complete model is depicted
in Fig. 7.
Fig. 7. FPGA-based SRM Drive HIL with DC-DC converter
Electric Hardware Solver on FPGA
The previous custom FPGA models of motor drives and power converters were custom-designed according to
specific client requirements using highly skilled FPGA specialists to code them. Their requirements included, in
particular, the capacity to change the model parameters without re-generating a new bitstream. This can be called a
variable parameter solver, something quite natural in CPUs but not so on FPGA because of the additional coding
effort required.
OPAL-RT’s Electric Hardware Solver (eHS) goes further by allowing the user to modify the topology of the
network being simulated. The eHS is basically a bitstream that allows the user to design their model in a standard
simulation software graphical interface (SPS and PLECS are supported). At the heart of eHS are the ANECS
solvers. The idea of ANECS is to allow users to design a switched electric circuit and converter topology from the
netlist obtained from SPS or PLECS. The global eHS topology is depicted in Fig. 8.
Key characteristics of the ANECS solver modules are:

Uses nodal method with fixed admittance matrix nodal method (FAMNM) to solve switched electric circuits.

Uses the Backward Euler method to provide very good accuracy below 1 µs.

Has a priori unlimited switch count because of the use of constant admittance matrix approach.

The time step is variable depending on the circuit size and ranges from 100ns to 1µs.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Fig. 8. eHS global structure
The Fixed Admittance Matrix Nodal Method (FAMNM) key idea is to simulate switches as a capacitor in the open
state and an inductor in the closed state. When discretized with the Backward Euler method, a capacitor and an
inductor equation can be made so their implicit term g (sometimes called ‘discrete admittance’ term) have the same
value if the following constraints are met:
g=C/h=h/L
(4)
where h is the simulation time step, C is the capacitor value, L is the inductor value and g is the resulting discrete
admittance of L and C (Equation 4 is valid for the Backward Euler method). In the method, g is chosen by the user.
At 1µs, with g=1, the corresponding capacitance and inductance are 1 µF and 1 µH for example. With these
parameters, it can be noted that the global admittance matrix of the system will remain unchanged if a switch
changes conduction state, which is the main advantage of this method. The FAMNM presents the disadvantages of
adding real inductors/capacitors in a circuit and can exhibit inaccuracies at high switch frequencies.
eHS example case: AC-DC-AC converter
Figure 9 shows an AC-DC-AC converter, feeding a Permanent Magnet Synchronous Motor (PMSM). It consists of
a 6.6 kV, 60 HZ three-phase power source connected to a 6.6 kV/440V, 60 Hz Y/D transformer. The 440V, 60 Hz
voltage obtained at the secondary of the transformer is first rectified by a six pulse IGBT bridge. Then, the filtered
DC voltage is applied to the IGBT Three-Level Inverter. The IGBT inverter uses Pulse Width Modulation (PWM)
with an 8-kHz carrier frequency. The rectifier Pulse Width Modulation (PWM) frequency is 4 kHz.
The circuit is simulated on CPU and FPGA as follows:

ANECS 1: AFE 2-level Rectifier including the first L-C filter, discretized with a time step of 400ns.

ANECS 2: 3-level NPC inverter including the second L-C filter, discretized with a time step of 690 ns.

An FPGA PMSM motor [6] model with JMAG-RT, discretized using a time step of 100ns.

The AC source and the transformer are simulated on one CPU core at 15 microseconds.

The controller is implemented in a separate Intel core with Simulink.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Fig. 9. AC-DC-AC Converter driving a PMSM
Validation against SimPowerSystems offline simulation at 500 nanoseconds time step
During this test, we operate the grid converter and motor drive on the Virtex-6 FPGA and compare the results with
SimPowerSystems. The grid converter switches at 8 kHz frequency while the 3-level motor inverter is switching at
4 kHz. The two converters run at a time step of 690 ns and the PMSM motor at 100 ns, on the FPGA. They are
coupled to the grid system (source+ transformer) on the CPU-side of RT-LAB, a part that runs at a time step of
20µs.
Fig. 10. Grid-side currents and voltages (eHS and SPS superposed)
Fig. 11. Transformer secondary voltage and currents (eHs and SPS superposed)
Fig. 12. Motor current with zoom on the right (eHS and SPS superposed)
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
Figure 10 presents the grid voltage and current (for phase A); Fig. 11 depicts the transformer secondary current and
voltage while Fig. 12 depicts the motor current. All figures superpose the eHS results with SPS. One can observe
that electric quantities computed in real-time eHS models compare very well with the results obtained in off-line
mode with SPS.
Multi-level Modular Converters (MMC)
Multi-level Modular Converters are a special case in terms of real-time simulation. MMC are voltage inverters
typically composed of hundreds of two-IGBT-capacitor cells connected in series. On one side, the complexity of
the MMC topology favors to the use of full-fledged solvers like SSN. However, the extremely high number of I/O
points (several thousands in many cases) favors an approach in which the MMC model directly interacts with the
I/Os (especially the IGBT gate signals) on the FPGA. The latter approach avoids the huge PCIe data transmission
that would require sending of IGBT gate signals to the CPU-side and therefore increases HIL performance.
Cell #30
Cell #1
Line
Cm
Cm
Line
Cell #60
Cell #31
+
Vc
-
Cm
Cm
Fig. 13. A simple MMC-based HVDC link.
Today, medium-size MMC (up to 100-150 cells per arms) can be simulated in real-time using SSN today [14]. By
comparison, systems with more than 400 cells per arms can be simulated on FPGAs.
Conclusion
As of 2013, many solver solutions exist for HIL simulation of power systems, power electronic and motor drives,
mainly based on CPUs and FPGAs. CPU solvers can solve complex power system problems using advanced
solvers like SSN. With SSN, it is possible to perform real-time simulation of very complex systems, such as
paralleled multi-level converter, thyristor-based HVDC link and MMC converters.
FPGAs are preferred if total HIL latency must be in the 1µs range, a common requirement for many power
converters and drives. FPGA solutions often require customization of the solver, a task only achievable by FPGA
specialists. With the eHS, it becomes possible to make FPGA-HIL without the intervention of an FPGA specialist
in the process, thus greatly accelerating the HIL set-up and test procedures.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France
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