Compensation of Input Current Distortion
in Three-Phase Buck Rectifiers
Ben Guo, Fan Xu, Zheyu Zhang, Zhuxian Xu, Fred Wang, Leon M. Tolbert, Benjamin J. Blalock
Center for Ultra-wide-area Resilient Electric Energy Transmission Networks (CURENT),
Department of Electrical Engineering and Computer Science,
The University of Tennessee
Knoxville, TN 37996-2250, USA
bguo@utk.edu
Abstract— An overlap time for two commutating switches is
necessary to prevent current interruption in a three-phase buck
rectifier, but it may cause input current distortion. In this paper, a
modified pulse-based compensation method is proposed to
compensate for the overlap time. In addition to the traditional
method which places the overlap time based on the voltage
polarity, this new method first minimizes the overlap time to
reduce its effect and then compensates the pulse width according
to the sampled voltage and current. It is verified by experiments
that the proposed method has better performance than the
traditional method, especially when the line-to-line voltage crosses
zero. Another distortion comes from the irregular pulse
distribution when two sectors change in a 12-sector space vector
PWM. This paper proposes two compensation methods for that
scenario as well, compensating the duty cycle and increasing
switching frequency near the boundaries of two sectors. It is
shown through experiments that both methods can reduce the
input current distortion in the buck rectifier.
signal of the switch that bears reverse voltage. It assumes that
the transition time is much smaller than the pulse width and can
be omitted. But this assumption is not precise when the
sinusoidal voltage on the device is crossing zero or the current
on the DC inductor is small at light load.
Another distortion comes from the modulation scheme. The
12-sector space vector modulation has been shown to have
lower switching loss compared to traditional 6-sector
modulation schemes [7-11]. Two sub-sectors are divided
according to the input current and voltage relationship in each
60˚ sector in Fig. 2. The vector arrangement will be changed to
achieve lowest switching voltage in two sub-sectors. But this
will produce irregular pulse distribution and cause input current
distortion at the moment of sector change [6][10-12]. When the
arrangement of the vectors alternates near the boundary of two
sub-sectors, the interval between two pulses will become short
on one switch and long on its complementary switch.
Index Terms—Three-phase buck rectifier, current source,
overlap time, space vector, sector change.
I. INTRODUCTION
The three-phase buck-type rectifier can be used as an active
front end in high-efficiency power supplies for communication
and data centers [1][2]. Its topology is shown in Fig. 1, where a
diode is in series with the MOSFET to form the switch in order
to block the voltage in both directions.
(a)
JK
I 3 [ S3 , S 2 ]
JJK
I 4 [ S3 , S 4 ]
JJK
I 5 [ S5 , S 4 ]
JJK
*
iabc
JJK
I 2 [ S1 , S2 ]
JK
I1 [ S1 , S6 ]
JJK
I 6 [ S5 , S 6 ]
JJK
I 0 [ S1 , S4 ] [ S3 , S6 ] [ S5 , S 2 ]
Fig. 1. Three-phase buck rectifier with freewheeling diode.
Overlap time is added in the gate signals of the buck rectifier
to prevent DC current interruption [1-3]. The overlap time will
cause error in the current control and increase the low-order
harmonics in the input current [4]. The distortion caused by the
overlap time is shown to be proportional to its duration and the
carrier frequency [5]. A compensation method for the overlap
time is proposed in [6], which adds overlap time to the gate
(b)
Fig. 2. Sector division in space vector PWM: (a) Input current and voltage;
(b) Space vector plane.
In this paper, the current distortion caused by the overlap
time is analyzed first. A modified pulse-based method is
proposed for the overlap time compensation. The commutation
in the buck rectifier is modeled, and a minimized overlap time
is proposed. Based on the model, the compensation pulse width
can be generated under different switching voltage and current.
The proposed method is verified through experiments in a 7.5
kW all-SiC buck rectifier.
Then the irregular pulse distribution is analyzed as well. Two
methods are proposed to reduce the irregular pulse
distribution—compensating for the duty cycle and increasing
the switching frequency near the sector change. Both methods
are analyzed and verified through simulation or experiments in
this paper.
component of the input current in Fig. 6, where the effect of the
overlap time toggles when
or
cross zero.
II. OVERLAP DISTORTION AND ITS COMPENSATION
As shown in Fig. 1, the commutation occurs between the
upper three switches (S1, S3, and S5) or the lower three
switches (S4, S6, and S2) in the buck rectifier. The basic
commutation unit can be drawn in Fig. 3, containing two
switches Sx and Sy. The voltage sources Vx and Vy indicate
two phase voltages, and Idc is the DC current on the inductor Ldc.
In Fig. 4, a double pulse test circuit is built based on Fig. 3 to
study the commutation under different operating conditions.
The active switches are 1200 V SiC MOSFETs, CMF20120D,
from Cree [13], and the series diodes are 1200 V SiC Schottky
barrier diodes (SBDs), SDP60S120D, from SemiSouth [14].
Fig. 5. Overlap time distortion.
Fig. 6. Input current distortion.
(a)
(b)
Fig. 3. Commutation unit in buck rectifier: (a) Circuit schematic; (b) Gate
signals.
B. Modified Pulse-based Compensation Method
The traditional pulse-based compensation method adds the
overlap time to the gate signal of the switch which bears reverse
voltage. It depends on the polarity of the line-to-line voltage.
As shown in Fig. 7, the gate pulse width of S3 is added by 2 ∆
to compensate the overlap time in Sector 2 when
0. The
input current will have no distortion since the transition
happens at the ideal moment and . Similarly, the overlap
0.
time is added on the S1 gate signal in Sector 3 when
The traditional compensation method assumes that the
commutation time is much smaller than the pulse width and can
be omitted.
Fig. 4. Device double pulse test board.
A. Distortion Caused by Overlap Time
The commutation between S1 and S3 in Sector 2 and 3 (Fig.
2) are taken as an example. The typical gate signals are shown
in Fig. 5 for S1 and S3. The overlap time ∆ is added on the
reference gate signals of S1 and S3 to prevent the interruption
of DC inductor current, as shown in Fig. 5.
When
0, the transition happens when S1 switches at
and rather than the ideal moment and , resulting in a
0, the
gain in the input current and a loss in . When
transitions occur at and when S3 switches, rather than the
ideal moment and , resulting in a loss in and a gain in .
This gain and loss will cause distortion of the fundamental
Fig. 7. Traditional compensation.
Fig. 8. Slow transition distortion.
However, the commutation time will become much longer
and cannot be ignored when the line-to-line voltage is crossing
zero or the DC current is small under light load, as shown in
Fig. 8. Under these conditions, the traditional method is not
enough to compensate for the overlap time effect. The turn-on
waveforms of Sx are measured in the double pulse test (Figs. 3
and 4) and shown in Fig. 9(a) when
= 340 V and
= 20
= 10 V and
= 20 A. The rise time of
A. In Fig. 9(b),
is more than 200 ns in Fig. 9(b), ten times of that shown in Fig.
9(a). The turn-off waveforms of Sx are shown in Fig. 10 when
= 680 V. The fall time of
is 40 ns when = 12 A in
= 1.5 A in Fig. 10(b).
Fig. 10(a) while 280 ns when
modules are added to the traditional method. First, the
minimum overlap time ∆ is selected for the gate signal to speed
up the transition and reduce the compensation effort. The
commutation process is modeled to generate the compensation
, DC current
pulse width according to line-to-line voltage
, and the overlap time ∆ . Finally the ideal reference pulse
is added by 2 ∆ and to get the actual reference
width
pulse width , which is sent to the modulator.
tΔ
2tΔ
tc
tx
t x*
Fig. 11. Modified pulse-based compensation method.
Time (100ns/div)
C. Commutation Analysis in Buck Rectifier
To model the commutation in the buck rectifier, the
theoretical turn on waveform of Sx is shown in Fig. 12 when
0 [15]. When the parasitic inductance
is not
considered, the channel current of the MOSFET is proportional
with the gate voltage from to , as the solid line shown in
Fig. 12. The gate charge time is proportional to the gate resistor
and the input capacitor
(including gate-source capacitor
and gate-drain capacitor
).
(a)
Vgs(10V/div)
Ids(5A/div)
Time (100ns/div)
Vds(100V/div)
(b)
Fig. 9. Measured turn-on waveforms: (a)
= 340 V,
= 20 A.
= 10 V,
+ Vxy Lp
Ldc
Idc
vds
= 20 A; (b)
+
ids
Fig. 12. Theoretical turn on
waveform of Sx.
Sx
Sy
Fig. 13. Sx turn on circuit with
parasitic inductance.
When is considered, the current rise time will be increased
when the switching voltage is low, as the dash line shown in
is distributed on the
Fig. 12. In this case, the voltage
in Fig. 13. The current rise time can be
parasitic inductance
⁄ .
written as
(a)
The current rise time
of Sx is determined by the larger of
⁄
, where
the two and is given by
2 ,
. When
is small,
is predominantly
⁄ . The charge loss of Sx or the charge gain of Sy can
⁄2.
be approximated by
(b)
Fig. 10. Measured turn-off waveforms: (a)
= 680 V,
= 680 V,
= 1.5 A.
= 12 A; (b)
A modified pulse-based compensation method is proposed to
compensate the overlap time. As shown in Fig. 11, two more
Conservatively, Sy should be kept on until current is fully
commutated to Sx when
0. The overlap time ∆ should
is close to zero.
be larger than , which is long when
Actually it is possible to accelerate the turn-on process of Sx
with careful selection of ∆ . If ∆ is set to the gate charge time
2 , the gate of S1 has reached the turn-on voltage at the end of
overlap time although its current has not reached . When Sy
is turned off, the DC inductor will force the current to be
commutated to Sx.
0
0
0
0
0
0
0
1
2
0
1
2
0
1
2
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
0
0
0
0
0
0
Fig. 16. Turn on with 150 ns overlap time.
0
0
Fig. 14. Sx turn on circuit with reduced overlap time.
0
The commutation with reduced overlap time can be
described with the equivalent circuit in Fig. 14. When Sy is
turned off, the related current and voltage in the commutation
can be expressed by (1) where
is the transconductance of
the MOSFET,
the
_ the gate-source voltage of Sy, and
gate drive voltage.
0
0
0
0
0
0
0
0
0
_
(1)
_
_
_
_
⁄
In this transition, the voltage on Sx has already dropped to a
low value, so
can be ignored in (1). The voltage spike on Sy
can be given by (2) and is proportional to the gate turn off speed
of Sy and the parasitic inductance .
3
4
The experimental waveforms of the turn on process under
=
different overlap times are shown in Figs. 15 to 17 when
= 20 A. The overlap time, current rise time, and
10 V and
voltage spike on Sy are listed in Table I. When overlap time is
550 ns in Fig. 17, there is no voltage spike on Sy.
TABLE I. SWITCHING CHARACTERISTICS WITH DIFFERENT OVERLAP TIME
Overlap Time
Current Rise Time
Voltage Spike on Sy
10 ns
70 ns
70 V
150 ns
180 ns
25 V
550 ns
270 ns
-
Fig. 15. Turn on with 10 ns overlap time.
6
7
8
9
10
In Figs. 15 and 16, it is obvious that the slope of
will
increase when Sy is turned off. The commutation is accelerated
while the voltage spike is affordable.
With reduced overlap time, the commutation can be
accelerated and the charge loss can be largely reduced. The
compensation time for the turn-on process of Sx can be
expressed by (3) when
0.
_
,
,
(2)
_
5
Fig. 17. Turn on with 550 ns overlap time.
,
∆
(3)
∆
,
∆
2
The theoretical turn off waveform of Sx is shown in Fig. 18
0 [15]. Before Sx is turned off, Sy has been turned
when
on although there is no current flowing in it. In this
commutation, the overlap time should be long enough for the
gate of S3 to be charged.
∆
1
,
2
If the junction capacitor on Sy is not considered, Sx current
is charged to
, as the solid line shown
will not drop until
in Fig. 18. The channel current of the MOSFET in Sx is
proportional with its gate voltage from to . The current fall
can be approximated by 2 .
time
But in the actual circuit, the junction capacitor on Sy will
always delay the voltage increase on Sx, as the dash line shown
in Fig. 18. The equivalent circuit can be drawn in Fig. 19, where
and
are mainly the output capacitance of the devices.
includes the drain-source capacitance
and gate-drain
of the MOSFET.
is the junction
capacitance
capacitance of the series diode. When Sx is turned off,
will
will be discharged by the DC current. The
be charged and
charge or discharge time can be approximated by
where
.
⁄
,
The current fall time
of Sx is determined by the larger of
⁄
. When
2 ,
the two and is given by
⁄ . The
is large and
is small,
is predominantly
charge gain of Sx or the charge loss of Sy can be approximated
⁄2
by
.
E. Experimental Verification
A 7.5 kW all-SiC three-phase buck rectifier was built (Fig.
20) [16], whose parameters are shown in Table III. 4-paralleled
SiC MOSFETs and 2-paralled SiC Schottky diodes are
connected in series for each switch in order to reduce the
conduction loss.
DSP board
Interface
board
DC capacitors
DC inductor
connector
VGG
Vp
vGS
Vth
vDS
tfi
iD
Idc
Vxy
t1 t2
0
t
Fig. 18. Theoretical turns off
waveform of Sx.
Fig. 19. Sx turn off circuit with
parasitic capacitance.
The compensation time for turn-off process of Sx can be
0 . Its pulse width should be
expressed by (4) when
0. The junction capacitance is a function
reduced when
of the voltage on the device [13][14]. A look-up table is built in
a digital signal processor to estimate under different voltage
conditions.
__
,
,
(4)
2
D. Application of Proposed Compensation Method
Based on the analysis above, the minimum overlap time ∆ is
for both the turn-on and
the gate charge time 2
turn-off process. The compensation time
for Sx is
__
,
,
when
0 .
__
Meanwhile, the pulse width of Sy should be reduced by
__
,
,
when
0.
__
Take S1 in Fig. 1 as an example. S1 has switching behavior
in 180 of a line period. The compensation pulse width in 6
sectors is listed in Table II for S1 and its complementary
switch. The modulation scheme is Modified Fullwave
Symmetrical Modulation (MFSM) [7].
TABLE II. COMPENSATION PULSE WIDTH
Compensation Pulse Width
Sector
10
11
12
1
2
3
S1
__
,
S5
__
,
S1
__
,
S5
S1
S5
S1
S3
S1
__
__
,
__
,
__
,
__
,
__
,
,
,
,
__
__
,
,
__
__
,
__
,
__
__
,
__
__
,
,
S3
__
,
__
,
S1
__
,
__
,
S3
__
,
__
,
Voltage
AC inductor
connector
AC input
terminal
AC input Cold plate Main board
capacitors
Fig. 20. 7.5kW all-SiC buck rectifier.
TABLE III. THREE-PHASE CURRENT SOURCE RECTIFIER PARAMETERS
7.5 kW
Power Rating
Three-phase line-to-line 480 Vac,rms
Input Voltage Rating
110 µH each phase
Input Inductor
6 µF each phase
Input Capacitor
400 Vdc
Output Voltage Rating
1.9 mH
Output Inductor
150 µF
Output Capacitor
28 kHz
Switching Frequency
98.5 %
Efficiency
> 99 %
Power Factor
The parameters are listed in Table IV for the compensation
formula (3) and (4). The time constant and turn-off delay
are measured in the converter and the parasitic
is estimated based on the PCB trace length. The
inductance
parasitic capacitance
is estimated based on the junction
capacitance value provided in the device datasheets [13][14]. It
decreases as the switching voltage
is shown in Fig. 21 that
increases.
TABLE IV. COMPENSATION PARAMETERS IN THE CONVERTER
10 ns for turn on process
Time Constant
20 ns for turn off process
100 nH
Parasitic inductance
40 ns
Turn-off delay
0
10
2
0
0
0
0
0
Cp (nH)
td(off)
10
10
10
1
0
-1
0
100
200
300
400
500
Switching Voltage (V)
600
700
800
Fig. 21. Cp under different switching voltage.
Experiments were carried out to verify the proposed
compensation method. As shown in Fig. 22, the input current
will have much distortion when the overrlap time is not
compensated. With the proposed compensaation method, the
distortion is largely reduced.
0
0
0
0
0
0
0
0
0
0
2
4
6
8
10
12
14
16
Fig. 24. Experiment results with reduced overlap time
(208 Vac, 20A Idc, 100 ns overlap time).
18
20
Fig. 25. Experiment results with
h pulse compensation
(208 Vac, 20A Idc, 500 ns overlap time).
Fig. 22. Experiment results without (upper) and withh (lower) overlap
compensation (480Vac, 2.5A Idc).
In Figs. 23 to 26, the buck rectifier is operaating under 208V
input line-to-line voltage and 20A output curreent. In Fig. 23, the
traditional compensation method is applied wiith 500 ns overlap
time. The overlap time is chosen to be longer tthan the transition
time when the voltage is small. The input currrent has resonance
when the line-to-line voltage crosses zero.
In Fig. 25, though the overlap time is sstill 500 ns, it is
compensated based on the commutation modeel proposed in this
paper. The distortion is reduced compared w
with Fig. 23. Their
harmonic comparison is shown in Fig. 28. Thhe THD decreases
from 1.9% to 1.7% with the pulse compensatiion.
0
2
Small overlap time and the compensatioon based on the
commutation model are both used in Fig. 26, and there is
almost no obvious distortion in the current waveform. Their
harmonic comparison is shown in Fig. 29. Thhe THD decreases
from 1.9% to 1.3% with the proposed methodd.
8
10
12
14
16
18
2
Trraditional, overlap=500ns
Trraditional, overlap=100ns
0.6
0.4
0.2
10
20
30
40
Harmonic Order
Fig. 27. Harmonic reduction with
h reduced overlap time
(208 Vac, 20A Idc).
1
50
Traditional, overlap=500ns
Pulse compensation, overlap=500ns
0.8
0.6
0.4
0.2
0
Fig. 23. Experiment results with traditionall method
(208 Vac, 20A Idc, 500 ns overlap tim
me).
6
0.8
0
% of Fundamental
The compensation pulse width for S1 chaanges with
in
the experiment, as shown in Fig. 30. The turn--on compensation
time Ton is largest when the voltage crosses zzero. The turn-off
compensation time Toff is small in this experiiment because the
turn-off speed of S1 is high in this case.
4
Fig. 26. Experiment results witth proposed method
(208 Vac, 20A Idc, 100 nss overlap time).
1
% of Fundamental
Based on the previous analysis, the overlaap can be largely
reduced to accelerate the commutation. As sshown in Fig. 24,
the overlap time is only 100 ns, and the distorrtion is much less
than that in Fig. 23. Their harmonic comparrison is shown in
Fig. 27. The total harmonic distortion (THD
D) decreases from
1.9% to 1.4% with the reduced overlap time.
10
20
30
40
Harmonic Order
Fig. 28. Harmonic reduction with
h pulse compensation
(208 Vac, 20A Idc).
50
% of Fundamental
1
Traditional, overlap=500ns
Proposed, overlap=100ns
0.8
0
0
0
0.6
0
0
0.4
0
0.2
0
0
0
10
20
30
40
Harmonic Order
Fig. 29. Harmonic reduction with proposed method
(208 Vac, 20A Idc).
50
0
0
2
4
6
8
10
12
14
Fig. 34. Compensation pule width for S1
(480 Vac, 5A Idc, 100 ns overlap time).
16
18
In Figs. 31 and 32, the buck rectifier is operating under 480V
input line-to-line voltage and 5A output current. The proposed
method can reduce the distortion in the current waveform.
Their harmonic comparison is shown in Fig. 33. The THD
decreases from 2.5% to 2.0% with the proposed method.
In this case, the turn-off speed is low under large voltage and
small current. The turn-off compensation time Toff changes
with the voltage in Fig. 34.
Because of the fast switching speed of SiC devices, the
compensation pulse width is usually less than 300 ns. The
distortion will be more severe when some lower speed devices
are used or the input capacitor is small or the converter is
operating at higher switching frequency. In these applications,
the proposed method will bring more improvement to the
current waveform.
Fig. 30. Compensation pule width for S1
(208 Vac, 20A Idc, 500 ns overlap time).
III. IRREGULAR PULSE DISTRIBUTION AND ITS COMPENSATION
A. Distortion Caused by Irregular Pulse Distribution
The irregular pulse distribution of the modulation usually
happens in the 12-sector modulation schemes. Different from
6-sector modulation, two sub-sectors are divided in each 60˚
sector according to the input current and voltage relationship,
as shown in Fig. 2.
Fig. 31. Experiment results with traditional method
(480 Vac, 5A Idc, 500 ns overlap time).
JK JK
I 0 I1
0
2
4
6
8
10
12
14
16
18
% of Fundamental
ic
Traditional, overlap=500ns
Proposed, overlap=100ns
0.8
JK JKJK JK
I1 I 0 I 0 I 6
ia
i
2
Fig. 32. Experiment results with proposed method
(480 Vac, 5A Idc, 100 ns overlap time).
1
JK
I6
*
a
ΔQ
JK
I1
JK JK
I6 I0
ic*
Fig. 35. Irregular pulse distribution in MFSM.
0.6
0.4
JK
I6
0.2
0
10
20
30
40
Harmonic Order
Fig. 33. Harmonic reduction with proposed method
(480 Vac, 5A Idc).
50
*
a
JK
I1
ia
ΔQ
i
ic
JK
I0
JK
I1
JK
I6
JK
I0
ic*
Fig. 36. Irregular pulse distribution in asymmetric modulation.
15
Ias
Ibs
Ics
10
δ1Ts
δδ1Ts
Is/A
5
0
-5
δ 6Ts
ia
JK
I6
ic*
-10
JK
I1
ΔQ1
JK JK
I 0 I1
ΔQ2 i
*
a
JK
I6
JK
I0
-15
0
0.005
time/s
0.01
(a)
(b)
Fig. 38. Simulation of distortion during sector change:(a) Current on AC
inductors; (b) Enlarged picture of the current distortion and gate signal.
ic
15
Fig. 37. Pulse-based damping method.
B. Compensation Methods for Irregular Pulse
The shaded area in Figs. 35 and 36 indicates the input current
of the buck rectifier. S1 and S5 have irregular pulse distribution
at the boundary of Sector 10 and 11, as shown in both figures.
An average function is applied to the pulse current with the
average period of switching cycle . The average currents
and deviate from the reference currents and near the
boundary, which can be described by the extra charge ∆ . In
Fig. 36, the peak value of can reach two times that of ,
while in Fig. 35 the peak value of is only 1.5 times that of .
The extra charge ∆ in Fig. 36 is four times that of Fig. 35, so
the distortion of 12-sector asymmetric PWM is much worse
than the symmetric MFSM.
Two methods are proposed here to reduce the extra charge
∆ . The first is to increase the switching frequency near the
boundary of the two sectors. In this way ∆ can be reduced
because the deviation time is shortened. This method will bring
more switching loss, which is acceptable since it only occurs
near 6 sector boundaries on the space vector plane.
The second effective method is a pulse-based compensation
method. As shown in Fig. 37, S1 has pulse width
and S5
( and are duty cycles of S1 and S5
has pulse width
respectively and is the switching period). If the pulse width
of S1 is reduced by
, the deviation of from can be
reduced. The current pulse is distributed more regularly at the
sector change. The extra charge ∆ is split into two parts,
∆ and ∆ , each of which is smaller than ∆ . ∆ and
∆ can be given by (5). The optimal point for the pulse-based
∆ ,
.
compensation is achieved when ∆
1
∆
(5)
∆
1
The simulation results given in Figs. 38 and 39 demonstrate
that the pulse-based damping method can reduce the irregular
pulse distribution and the input current distortion.
Ias
Ibs
Ics
10
5
Is/A
The arrangement of the vectors will alternate in two
sub-sectors to achieve the lowest switching voltage within a
switching cycle. The vector arrangement change in two
consecutive sectors is shown in Figs. 35 and 36 for Modified
Fullwave Symmetrical Modulation (MFSM) [7] and 12-sector
asymmetric modulation respectively [11].
0.015
0
-5
-10
-15
0
0.005
time/s
0.01
0.015
(b)
(a)
Fig. 39. Simulation of distortion after compensation:(a) Current on AC
inductors; (b) Enlarged picture of the current distortion and gate signal.
The pulse-based compensation method can only be applied
to the asymmetric PWM. It will not increase the switching
frequency and is easy to apply. Increasing the switching
frequency near sector boundary can be widely applied to both
symmetric and asymmetric PWMs.
C. Experimental Verification
The three-phase buck rectifier in Fig. 20 is operating under
208 V input line-to-line voltage and 5A output current. Without
compensation at the sector change, the irregular pulse causes
current distortion in Fig. 40. The green curve in the figure is the
gate signal of S1 and the black curve is the gate signal of S3.
The arrangement of the two active vectors changes as shown in
Fig. 40.
0
0
0
0
0
0
0
Fig. 40. Experiment results without irregular pulse compensation.
0
0
0
0
0
0
Fig. 41. Experiment results with pulse-based compensation.
[6]
[7]
0
2
4
6
8
10
12
14
16
18
[8]
[9]
55
15 55
15 6
15 65
15 7
15 75
15 8
15 85
15 9
15 95
Fig. 42. Experiment results with increased switching frequency.
16
The pulse-based compensation is applied in Fig. 41, where
the pulse width of S3 is reduced and the pulse width of S1 is
increased to compensate the irregular pulse. The distortion is
reduced compared with Fig. 40. The switching frequency is
increased from 28 kHz to 40 kHz near the boundary of the two
sectors in Fig. 42, where the distortion is also reduced.
However, there is still some distortion in the current
waveform. It is because of the sliding intersection between two
active vectors, as described in [6].
VI. CONCLUSIONS
In this paper, a modified pulse-based compensation method
is proposed to compensate overlap time. In addition to the
traditional method that places the overlap time based on the
voltage polarity, the new method first minimizes the overlap
time to reduce its effect and then compensates the pulse width
according to the sampled voltage and current. The experiments
have demonstrated its advantages over traditional methods
especially when the switching voltage is near zero. Two
methods are proposed to reduce the irregular pulse distribution
during sector change within 12-sector modulation schemes.
Besides increasing switching frequency, the pulse-based
damping method can also reduce the deviation of the average
current near the boundary of two consecutive sectors.
ACKNOWLEDGEMENT
This work made use of Engineering Research Center Shared
Facilities supported by the Engineering Research Center
Program of the National Science Foundation and DOE under
NSF Award Number EEC-1041877 and the CURENT Industry
Partnership Program.
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