PD - 94006A
Advanced Process Technology
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Ease of Paralleling
l Simple Drive Requirements
Description
IRF640N
IRF640NS
IRF640NL
l
HEXFET® Power MOSFET
D
RDS(on) = 0.15Ω
G
Fifth Generation HEXFET ® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer with an
extremely efficient and reliable device for use in a wide
variety of applications.
The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation levels
to approximately 50 watts. The low thermal resistance and
low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of its
low internal connection resistance and can dissipate up to
2.0W in a typical surface mount application.
The through-hole version (IRF640NL) is available for lowprofile application.
VDSS = 200V
ID = 18A
S
TO-220AB
IRF640N
D2Pak
IRF640NS
TO-262
IRF640NL
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
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Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy ‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt †
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew„
Max.
18
13
72
150
1.0
± 20
247
18
15
8.1
-55 to +175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
1
10/08/04
IRF640N/S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
200
–––
–––
2.0
6.8
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.25
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
10
19
23
5.5
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
1160
185
53
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.15
Ω
VGS = 10V, ID = 11A ƒ
4.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 50V, ID = 11A ƒ
25
VDS = 200V, VGS = 0V
µA
250
VDS = 160V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
67
ID = 11A
11
nC
VDS = 160V
33
VGS = 10V, See Fig. 6 and 13
–––
VDD = 100V
–––
ID = 11A
ns
–––
RG = 2.5Ω
–––
RD = 9.0Ω, See Fig. 10 ƒ
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 18
showing the
A
G
integral reverse
––– –––
72
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 11A, VGS = 0V ƒ
––– 167 251
ns
TJ = 25°C, IF = 11A
––– 929 1394 nC
di/dt = 100A/µs ƒ
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Thermal Resistance
RθJC
RθCS
RθJA
RθJA
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Parameter
Typ.
Max.
Junction-to-Case
Case-to-Sink, Flat, Greased Surface „
Junction-to-Ambient„
Junction-to-Ambient (PCB mount)
–––
0.50
–––
–––
1.0
–––
62
40
Units
°C/W
2
IRF640N/S/L
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
10
1
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
4.5V
0.1
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
10
4.5V
1
0.1
0.1
100
I D , Drain-to-Source Current (A)
100
TJ = 175 ° C
10
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
6.0
7.0
8.0
9.0
10.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 1. Typical Output Characteristics
5.0
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
0.1
4.0
20µs PULSE WIDTH
TJ = 175 °C
3.5
ID = 18A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF640N/S/L
2500
VGS , Gate-to-Source Voltage (V)
2000
C, Capacitance(pF)
20
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
1500
Ciss
1000
Coss
500
Crss
0
10
100
12
8
4
1000
0
20
40
60
80
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
V DS= 160V
V DS= 100V
V DS= 40V
16
0
1
ID = 11A
TJ = 175 ° C
10
TJ = 25 ° C
1
10us
100us
10
1ms
10ms
1
0.1
0.2
TC = 25 °C
TJ = 175 °C
Single Pulse
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
1.4
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
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1.6
0.1
0.1
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
4
IRF640N/S/L
VGS
D.U.T.
RG
16
16
ID , Drain Current (A)
ID , Drain Current (A)
RD
V DS
20
20
+
V
DD
-
10V
12
12
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
8
8
VDS
4
90%
4
0
0
25
25
50
75
100
125
150
50 T 75
125
° C)
, Case100
Temperature
(150
TC C
, Case Temperature ( ° C)
175
175
10%
VGS
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response(Z thJC )
10
1
D = 0.50
0.20
PDM
0.10
0.1
t1
0.05
0.02
0.01
0.01
0.00001
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
L
VDS
DRIVER
D.U.T
RG
+
- VDD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
IRF640N/S/L
600
ID
4.4A
7.6A
BOTTOM 11A
TOP
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( ° C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
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ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
IRF640N/S/L
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRF640N/S/L
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
IGBTs, CoPACK
2 - DRAIN
1- GATE
3 - SOURCE
2- DRAIN
3- SOURCE
4 - DRAIN
4- DRAIN
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
HEXFET
1 - GATE
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
RE CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
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PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
8
IRF640N/S/L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
THIS IS AN IRF 530S WITH
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN THE AS S EMBLY LINE "L"
INTE RNATIONAL
RECT IFIER
LOGO
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
PART NUMBER
F 530S
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INT ERNAT IONAL
RE CT IF IE R
LOGO
AS SE MBLY
LOT CODE
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PART NUMBE R
F530S
DAT E CODE
P = DE SIGNAT E S LEAD-FREE
PRODUCT (OPT IONAL)
YE AR 0 = 2000
WEE K 02
A = AS SE MBLY S IT E CODE
9
IRF640N/S/L
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE AS SEMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = ASS EMBLY SIT E CODE
10
IRF640N/S/L
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
Notes:
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
 Repetitive rating; pulse width limited by
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature.
‚ Starting TJ = 25°C, L = 4.2mH
„ This is only applied to TO-220AB package
RG = 25Ω, IAS = 11A.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
† ISD ≤ 11A, di/dt ≤ 344A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the automotive [Q101] (IRF640N)
& industrial market (IRF640NS/L).
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/04
www.irf.com
11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/