PCM1850A
PCM1851A
SLES173 – MARCH 2006
24-BIT, 96-kHz STEREO A/D CONVERTER
WITH 6 × 2-CHANNEL MUX AND PGAE
FEATURES
•
•
•
•
•
Multiplexer and Programmable-Gain Amplifier
(PGA)
– 6×2-Channel Single-Ended Inputs
– Multiplexed Output
– Maximum Input Level: 2.4 V rms
– Input Resistance: 50 kΩ, Minimum
– PGA Gain: 11-dB to –11-dB Range, 0.5
dB/Step
24-Bit Delta-Sigma Stereo A/D Converter
Antialiasing Filter Included
Oversampling Decimation Filter
– Oversampling Frequency: ×64
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
High Performance
– THD+N: 0.0023% (Typically)
– SNR: 101 dB (Typically)
– Dynamic Range: 102 dB (Typically)
•
•
•
•
•
•
PCM Audio Interface
– Master/Slave Mode Selectable
– Data Formats: 24-Bit Left-Justified, 24-Bit
I2S, 16-, 24-Bit Right-Justified
Mode Control by Serial Interface:
– With SPI Control (PCM1850A)
– With I2C Control (PCM1851A)
Sampling Rate: 16–96 kHz
System Clock: 256 fs, 384 fs, 512 fs, 768 fs
Dual Power Supplies: 5 V for Analog, 3.3 V for
Digital
Package: 32-Pin TQFP
APPLICATIONS
•
•
•
•
•
•
DVD/HDD/DVD+HDD Recorder
AV Amplifier Receiver
CD Recorder
MD Recorder
Multitrack Recorder
Electric Musical Instrument
DESCRIPTION
The PCM1850A/1851A is a high-performance, low-cost, single-chip stereo analog-to-digital converter with a
single-ended analog front end that consists of a 6-stereo-input multiplexer and wide-range PGA. The
PCM1850A/1851A includes a delta-sigma modulator with 64-times oversampling, a digital decimation filter and a
low-cut filter that removes the dc component of the input signal. For various applications, the PCM1850A/1851A
supports two modes (master and slave) and four data formats through a serial control interface, SPI for the
PCM1850A and I2C for the PCM1851A. The PCM1850A/1851A is suitable for a wide variety of cost-sensitive
DVD/CD/MD recorder and receiver applications where good performance and operation from a 5-V analog
supply and 3.3-V digital supply is required. The PCM1850A/1851A is fabricated using a highly advanced CMOS
process and is available in a small 32-pin TQFP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
PCM1850A
PCM1851A
www.ti.com
SLES173 – MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
VINL1
VINL2
VINL3
VINL4
VINL5
VINL6
MOUTL
Single-Ended
MUX and PGA
Reference
VINR1
VINR2
VINR3
VINR4
VINR5
VINR6
MOUTR
Audio
Data
Interface
Decimation
Filter
with
High-Pass Filter
VREF1
VREFS
VREF2
BCK
LRCK
DOUT
Delta-Sigma
Modulator
Single-Ended
MUX and PGA
OVER
Control
Data
Interface
MS (ADR)(1)
MD (SDA)(1)
MC (SCL)(1)
Delta-Sigma
Modulator
TEST0
TEST1
RST
Clock and Timing Control
Power Supply
VCC
(1)
AGND DGND
SCKI
VDD
PCM1850A (PCM1851A)
B0004-09
PIN ASSIGNMENTS
VINR6
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
PCM1851A
(TOP VIEW)
VINR6
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
PCM1850A
(TOP VIEW)
24 23 22 21 20 19 18 17
24 23 22 21 20 19 18 17
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
2 3 4
VREFS
VREF1
VREF2
Vcc
AGND
ADR
SCL
SDA
5 6 7 8
25
16
26
15
27
14
28
13
29
12
30
11
31
10
32
9
1 2
LRCK
BCK
DOUT
OVER
DGND
VDD
SCKI
TEST0
1
VINR2
VINL2
VINR1
VINL1
MOUTL
MOUTR
RST
TEST1
3 4 5 6
VINR2
VINL2
VINR1
VINL1
MOUTL
MOUTR
RST
TEST1
7 8
LRCK
BCK
DOUT
OVER
DGND
VDD
SCKI
TEST0
VREFS
VREF1
VREF2
Vcc
AGND
MS
MC
MD
P0040-01
2
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SLES173 – MARCH 2006
TERMINAL FUNCTIONS
PCM1850A
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
29
—
Analog GND
BCK
2
I/O
Bit clock input/output (1)
DGND
5
—
Digital GND
DOUT
3
O
Audio data output
LRCK
1
I/O
Sampling clock input/output (1)
MC
31
I
Mode-control clock input (2)
MD
32
I
Mode-control data input(2)
MOUTL
12
O
Multiplexer output, L-channel
MOUTR
11
O
Multiplexer output, R-channel
MS
30
I
Mode-control select input (3)
OVER
4
O
Overflow flag
RST
10
I
Reset, active-LOW(3)
SCKI
7
I
System clock input; 256 fS, 384 fS, 512 fS, or 768 fS(2)
TEST0
8
I
Test 0, must be connected to GND(3)
TEST1
9
I
Test 1, must be connected to GND(3)
VCC
28
—
Analog power supply, 5-V
VDD
6
—
Digital power supply, 3.3-V
VINL1
13
I
Analog input 1, L-channel
VINL2
15
I
Analog input 2, L-channel
VINL3
17
I
Analog input 3, L-channel
VINL4
19
I
Analog input 4, L-channel
VINL5
21
I
Analog input 5, L-channel
VINL6
23
I
Analog input 6, L-channel
VINR1
14
I
Analog input 1, R-channel
VINR2
16
I
Analog input 2, R-channel
VINR3
18
I
Analog input 3, R-channel
VINR4
20
I
Analog input 4, R-channel
VINR5
22
I
Analog input 5, R-channel
VINR6
24
I
Analog input 6, R-channel
VREFS
25
—
Reference S decoupling capacitor (= 0.5 VCC)
VREF1
26
—
Reference 1 decoupling capacitor (= 0.5 VCC)
VREF2
27
—
Reference 2 decoupling capacitor (= VCC)
(1)
(2)
(3)
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant
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PCM1851A
TERMINAL
NAME
NO.
I/O
Mode control address select input (1)
ADR
30
AGND
29
—
Analog GND
BCK
2
I/O
Bit clock input/output (2)
DGND
5
—
Digital GND
DOUT
3
O
Audio data output
LRCK
1
I/O
Sampling clock input/output (2)
MOUTL
12
O
Multiplexer output, L-channel
MOUTR
11
O
Multiplexer output, R-channel
OVER
4
O
Overflow flag
RST
10
I
Reset, active-LOW(1)
SCKI
7
I
System clock input; 256 fS, 384 fS, 512 fS, or 768 fS (3)
SCL
31
I
Mode-control clock input(3)
SDA
32
I/O
TEST0
8
I
Test 0, must be connected to GND(1)
TEST1
9
I
Test 1, must be connected to GND(1)
VCC
28
—
Analog power supply, 5-V
VDD
6
—
Digital power supply, 3.3-V
VINL1
13
I
Analog input 1, L-channel
VINL2
15
I
Analog input 2, L-channel
VINL3
17
I
Analog input 3, L-channel
VINL4
19
I
Analog input 4, L-channel
VINL5
21
I
Analog input 5, L-channel
VINL6
23
I
Analog input 6, L-channel
VINR1
14
I
Analog input 1, R-channel
VINR2
16
I
Analog input 2, R-channel
VINR3
18
I
Analog input 3, R-channel
VINR4
20
I
Analog input 4, R-channel
VINR5
22
I
Analog input 5, R-channel
VINR6
24
I
Analog input 6, R-channel
VREFS
25
—
Reference S decoupling capacitor (= 0.5 VCC)
VREF1
26
—
Reference 1 decoupling capacitor (= 0.5 VCC)
VREF2
27
—
Reference 2 decoupling capacitor (= VCC)
(1)
(2)
(3)
(4)
4
I
DESCRIPTION
Mode-control data input/output (4)
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant
Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input/open-drain LOW output, 5-V tolerant
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ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VCC
VDD
Supply voltage
VALUE
UNIT
–0.3 to 6.5
V
–0.3 to 4
V
±0.1
V
–0.3 to (VDD + 0.3) < 4
V
–0.3 to 6.5
V
–3 to (VCC + 3) < 9
V
Ground voltage differences: AGND, DGND
Digital input voltage: LRCK, BCK, DOUT, OVER
Digital input voltage: RST, SCKI, MS (ADR) (2), MC (SCL) (2), MD (SDA) (2), TEST0, TEST1
Analog input voltage: VINL1–6, VINR1–6
Analog input voltage: MOUTL, MOUTR, VREF1, VREF2, VREFS
–0.3 to (VCC + 0.3) < 6.5
V
±10
mA
Ambient temperature under bias
–40 to 125
°C
Storage temperature
–55 to 150
°C
Junction temperature
150
°C
Input current (any pins except supplies)
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
(1)
(2)
°C
260
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PCM1850A (PCM1851A)
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Analog supply voltage
4.5
5
5.5
V
VDD
Digital supply voltage
2.7
3.3
3.6
V
Analog input voltage, full scale (0
dB)
VCC = 5 V, PGA gain = 5.5 dB
2
Digital input logic family
Digital input clock frequency
Vrms
TTL
System clock
Sampling clock
4.096
49.152
MHz
16
96
kHz
20
pF
85
°C
Digital output load capacitance
TA
UNIT
Operating free-air temperature
40
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
PCM1850APJT, PCM1851APJT
MIN
TYP
UNIT
MAX
DIGITAL INPUT/OUTPUT — DATA FORMAT
Left-justified, I2S, right-justified
Audio data interface format
Audio data bit length
16, 24
Audio data format
fS
Sampling frequency
System clock frequency
bits
MSB-first, 2s complement
16
48
96
256 fS
4.096
12.288
24.576
384 fS
6.144
18.432
36.864
512 fS
8.192
24.576
49.152
768 fS
12.288
36.864
–
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kHz
MHz
5
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SLES173 – MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
PCM1850APJT, PCM1851APJT
MIN
TYP
UNIT
MAX
INPUT LOGIC
VIH (1)
VIL
(1)
VIH (2) (3)
VIL
IIH
Input logic level
(2) (3)
(2)
IIL (2)
IIH (1) (3)
2
VDD
0
0.8
2
5.5
0
0.8
±10
VIN = VDD
±10
VIN = 0
Input logic current
VIN = VDD
IIL (1) (3)
VDC
65
100
µA
±10
VIN = 0
OUTPUT LOGIC
VOH (4)
VOL (4) (5)
IOUT = –4 mA
Output logic level
2.8
IOUT = 4 mA
0.5
VDC
AFE MULTPLEXER
Input channels
6
Input level for full scale
2
2.4
Vrms
Center voltage (VREF1)
Selected channel
0.5 VCC
V
Center voltage (VREFS)
Unselected channel
0.5 VCC
V
Input impedance
Selected channel
50
169
Unselected channel
50
57
kΩ
AFE PGA
Gain range
–11
Gain step
0
0.5
Monotonicity
11
dB
dB
Specified
Antialiasing filter frequency
response
–3 dB, PGA gain = –5.5 dB
300
kHz
0.6 VCC
Vp-p
MONITOR OUTPUT
Output level for full scale
AC-coupled, >10 kΩ
Output load
AC-coupled
THD+N
S/N
(6) (7)
Signal-to-noise ratio
Gain error
AC-coupled, 10 kΩ, 3 Vp-p output
(6) (7)
(6) (7)
10
kΩ
0.0016%
AC-coupled, 10 kΩ
104
dB
AC-coupled, 10 kΩ
–3
% of FSR
Center voltage
0.5 VCC
V
ADC
Resolution
Full-scale input voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
24
bits
0.6 VCC
Vp-p
Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-kΩ typical pulldown resistor)
Pins 7, 31, 32: SCKI, MC/SCL (PCM1850A/1851A), MD/SDA (PCM1850A/1851A) (Schmitt-trigger input, 5-V tolerant)
Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850A/1851A) (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V
tolerant)
Pins 1–4: LRCK, BCK (in master mode), DOUT, OVER
Pin 32: SDA (PCM1851A) (open-drain LOW output)
Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-Hz
HPF and 20-kHz LPF in the RMS mode at fIN = 1 kHz.
Reference level (0 dB) is specified as 2-V rms input on VINL[1:6] and VINR[1:6] pins with PGA gain of –5.5 dB.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
PCM1850APJT, PCM1851APJT
MIN
TYP
UNIT
MAX
ACCURACY
Gain mismatch,
channel-to-channel
Gain error
Bipolar zero error
DYANAMIC PERFORMANCE
THD+N
% of FSR
±2
±5
% of FSR
% of FSR
(1) (2)
fS = 48 kHz, VIN = –0.5 dB (1.89 Vrms)
0.0023%
fS = 96 kHz (4),
VIN = –0.5 dB (1.89 Vrms)
0.0027%
fS = 48 kHz, VIN = –60 dB (2 mVrms)
fS = 96 kHz
S/N
±3
±2
High-pass filter bypass
Total harmonic distortion +
noise (3)
Dynamic range
±1
fS = 96 kHz
fS = 96 kHz
(4),
Channel separation (among
channels) (5)
fS = 96 kHz
fS = 96 kHz
96
dB
101
dB
102
92
(4)
fS = 48 kHz
102
102
A-weighted
fS = 48 kHz
(3)
1%
96
A-weighted
fS = 48 kHz, A-weighted
(3)
Channel separation
(between L-ch and R-ch)
(4),
1%
VIN = –60 dB (2 mVrms)
fS = 48 kHz, A-weighted
(3)
Signal-to-noise ratio
(4),
0.004%
98
dB
100
90
(4)
96
dB
96
DIGITAL FILTER PERFORMANCE
Pass band
0.454 fS
Stop band
0.583 fS
Hz
±0.05
Pass-band ripple
Stop-band attenuation
–65
Delay time
HPF frequency response
(1)
(2)
(3)
(4)
(5)
–3 dB
Hz
dB
dB
17.4/fS
s
0.019 fS
mHz
Analog performance specifications are tested with the System Two™ audio measurement system by Audio Precision™, using a 400-Hz
HPF and 20-kHz LPF in the RMS mode at fIN = 1 kHz.
Reference level (0 dB) is specified as 2-V rms input on VINL[1:6] and VINR[1:6] pins with PGA gain of –5.5 dB.
Unselected channel inputs are terminated to AGND with 0.33 µF.
fS = 96 kHz, system clock = 256 fS.
2-V rms input is applied to all unselected channels, and input of selected channel is terminated to AGND with 0.33 µF.
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
PCM1850APJT, PCM1851APJT
MIN
TYP
UNIT
MAX
POWER-SUPPLY REQUIREMENTS
VCC
VDD
Voltage range
4.5
5
5.5
2.7
3.3
3.6
28
35
Operational
ICC
Powered down
Supply current
(1)
IDD
(2)
fS = 96 kHz
6
(3)
(2),
PCM1850A
80
Powered down
(2),
PCM1851A
280
Operating, fS = 48 kHz
Power dissipation
10
12
Powered down
Operating, fS = 96 kHz
160
(3)
180
Powered down
(2),
PCM1850A
1.2
Powered down
(2),
PCM1851A
1.9
mA
µA
190
fS = 48 kHz
VDC
mA
µA
208
mW
TEMPERATURE RANGE
Operation temperature
–40
Thermal resistance (θJA)
(1)
(2)
(3)
8
85
80
Minimum load on DOUT (pin 3), BCK (pin 2), LRCK (pin 1)
Halt SCKI, BCK, LRCK.
fS = 96 kHz, system clock = 256 fS.
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°C/W
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted).
DIGITAL FILTER
Decimation Filter Frequency Response
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
50
−10
−20
0
Amplitude – dB
Amplitude – dB
−30
−50
−100
−40
−50
−60
−70
−150
−80
−90
−200
0
8
16
Frequency [× fS]
24
−100
0.00
32
0.25
0.50
0.75
1.00
Frequency [× fS]
G001
Figure 1. Overall Characteristics
G002
Figure 2. Stop-Band Attenuation Characteristics
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0.2
–4.13 dB at 0.5×
−1
−2
−3
−0.2
Amplitude − dB
Amplitude – dB
0.0
−0.4
−0.6
−4
−5
−6
−7
−8
−0.8
−9
−1.0
0.0
0.1
0.2
0.3
0.4
0.5
Frequency [× fS]
0.6
−10
0.45
G003
Figure 3. Pass-Band Ripple Characteristics
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0.47
0.49
0.51
0.53
Frequency [× fS]
0.55
G004
Figure 4. Transition-Band Characteristics
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted).
High-Pass Filter Frequency Response
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.2
0
−10
−20
−30
−0.2
Amplitude – dB
Amplitude – dB
0.0
−0.4
−0.6
−40
−50
−60
−70
−80
−0.8
−90
−100
0.0
−1.0
0
1
2
3
4
Frequency [× fS/1000]
0.1
0.2
0.3
0.4
Frequency [× fS/1000]
G005
Figure 5. HPF Pass-Band Characteristics
G006
Figure 6. HPF Stop-Band Characteristics
ANALOG FILTER
Antialiasing Filter Frequency Response (at PGA Gain = –5.5 dB)
AMPLITUDE
vs
FREQUENCY
−5.5
0
−5.6
−5
−5.7
−10
−5.8
−15
Amplitude – dB
Amplitude – dB
AMPLITUDE
vs
FREQUENCY
−5.9
−6.0
−6.1
−20
−25
−30
−6.2
−35
−6.3
−40
−6.4
−45
−6.5
0.1
f–3dB = 300 kHz
−50
1
10
100
1k
1
f – Frequency – kHz
10
100
1k
G007
Figure 7. Antialiasing Filter Pass-Band
Characteritics
10
10k
f – Frequency – kHz
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G008
Figure 8. Antialiasing Filter Stop-Band
Characteritics
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TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
DYNAMIC RANGE AND SNR
vs
FREE-AIR TEMPERATURE
107
106
Dynamic Range and SNR – dB
THD+N – Total Harmonic Distortion + Noise – %
0.004
0.003
0.002
104
103
Dynamic Range
102
SNR
101
100
99
98
0.001
−40
−15
10
35
60
TA – Free-Air Temperature – °C
97
−40
85
−15
10
35
60
TA – Free-Air Temperature – °C
G009
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE AND SNR
vs
SUPPLY VOLTAGE
85
G010
107
0.004
106
Dynamic Range and SNR – dB
THD+N – Total Harmonic Distortion + Noise – %
105
0.003
0.002
105
104
103
Dynamic Range
102
101
SNR
100
99
98
0.001
4.5
4.7
4.9
5.1
VCC – Supply Voltage – V
5.3
5.5
97
4.5
G011
Figure 11.
4.7
4.9
5.1
VCC – Supply Voltage – V
5.3
5.5
G012
Figure 12.
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TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE
vs
fSAMPLE CONDITION
DYNAMIC RANGE AND SNR
vs
fSAMPLE CONDITION
107
106
Dynamic Range and SNR – dB
THD+N – Total Harmonic Distortion + Noise – %
0.004
0.003
0.002
105
104
103
Dynamic Range
102
SNR
101
100
99
98
97
0.001
16
36
56
76
fSAMPLE Condition – kHz
16
96
36
56
76
fSAMPLE Condition – kHz
G013
Figure 13.
Figure 14.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
96
G014
OUTPUT SPECTRUM
0
0
Input Level = –0.5 dB
Data Points = 8192
−20
−20
−40
−40
Amplitude – dB
Amplitude – dB
Input Level = –60 dB
Data Points = 8192
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
5
10
15
20
0
f – Frequency – kHz
5
10
G015
Figure 15.
12
15
20
f – Frequency – kHz
G016
Figure 16.
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TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless
otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE
vs
SIGNAL LEVEL
THD+N – Total Harmonic Distortion + Noise – %
100
10
1
0.1
0.01
0.001
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Signal Level – dB
G017
Figure 17.
SUPPLY CURRENT
PGA GAIN LINEARITY
SUPPLY CURRENT
vs
fSAMPLE CONDITION
OVERALL GAIN
vs
GAIN SETTING
30
11
9
25
7
5
20
Overall Gain – dB
ICC and IDD – Supply Current – mA
ICC
15
IDD
10
3
1
−1
−3
−5
−7
5
−9
0
16
36
56
76
fSAMPLE Condition – kHz
96
−11
−11 −9
−7 −5
−3 −1
1
3
5
7
9
11
Gain Setting – dB
G018
Figure 18.
G019
Figure 19.
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DETAILED DESCRIPTION
SYSTEM CLOCK
The PCM1850A/1851A supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio
sampling frequency. The system clock must be supplied on SCKI (pin 7).
The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock is
operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be
selected by mode control via the serial port. The 768-fS system clock is not available in master mode or for fS =
88.2 kHz and 96 kHz in the slave mode. The system clock is divided into 128 fS and 64 fS automatically, and
these frequencies are used to operate the digital filter and the delta-sigma modulator, respectively.
Table 1 shows the relationship of typical sampling frequency to system clock frequency, and Figure 20 shows
system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING RATE FREQUENCY
(kHz)
(1)
256 fS
384 fS
768 fS (1)
512 fS
32
8.192
12.288
16.384
24.576
44.1
11.2896
16.9344
22.5792
33.8688
48
12.288
18.432
24.576
36.864
64
16.384
24.576
32.768
49.152
88.2
22.5792
33.8688
45.1584
—
96
24.576
36.864
49.152
—
Slave mode only
t(SCKH)
H
2V
SCKI
0.8 V
L
t(SCKL)
T0005-11
SYMBOL
PARAMETER
MAX
UNIT
System clock pulse duration, HIGH
8
ns
t(SCKL)
System clock pulse duration, LOW
8
ns
Figure 20. System Clock Timing
14
MIN
t(SCKH)
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POWER-ON-RESET SEQUENCE
The PCM1850A/1851A has an internal power-on-reset circuit, and initialization (reset) is performed automatically
at the time that the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system
clocks after VDD > 2.2 V (typical), the PCM1850A/1851A stays in the reset state and the digital output is forced to
zero. The digital output is valid after the reset state is released and the time of 4500/fS has passed. At the
moment of the power-on-reset release, the PCM1850A/1851A does not need a system clock. Figure 21
illustrates the internal power-on-reset timing and the digital output for power-on reset.
VDD
2.6 V
2.2 V
1.8 V
Reset
Release From Reset
1024 System Clocks
4500/fS
Internal Reset
System Clock
DOUT
Zero Data
Normal Data
T0014-10
Figure 21. Internal Power-On-Reset Timing
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ANALOG FRONT END
The PCM1850A/1851A has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22.
Selection of the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in
Table 2 and Table 3. The change of the input selection and the gain selection is performed immediately after the
serial control packet for the change is sent. A popping noise or other unexpected transient response could be
generated in the audio signal during channel and gain change. Because the PCM1850A/1851A has no
zero-cross detection and no other buffering capability for channel and gain change, appropriate data handling in
the digital domain is recommended to control transients.
The PCM1850A/1851A analog front end permits only ac input via an input capacitor; dc input is prohibited. A
signal source resistance of less than 1 kΩ is recommended for the VINxx pins.
All unselected channel inputs are terminated VREFS (= 0.5 VCC) using a resistor, typically 57 kΩ.
The PCM1850A/1851A employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load on
these pins must be ac-coupled and not less than 10 kΩ. The full-scale output level is typically 0.6 VCC.
VINL1
R
VINL2
R
R
PGA
(11 dB to –11 dB)
with MUX
VINL6
R
G = –1
LIN+
R
LIN–
VREF1
(= 0.5 VCC)
VREFS
(= 0.5 VCC)
MOUTL
B0131−01
Figure 22. Analog Front-End Block Diagram (L-Channel)
Table 2. Multiplexer Input Selection
16
CH2
CH1
CH0
0
0
0
Mute
0
0
1
Channel 1 (default)
0
1
0
Channel 2
0
1
1
Channel 3
1
0
0
Channel 4
1
0
1
Channel 5
1
1
0
Channel 6
1
1
1
Mute
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Table 3. PGA Gain Selection
PG5
PG4
PG3
PG2
PG1
PG0
PGA GAIN [dB]
RIN [kΩ, Typical] (1)
0
0
1
0
1
0
–11 (default)
201
0
0
1
0
1
1
–10.5
199
0
0
1
1
0
0
–10
196
0
0
1
1
0
1
–9.5
193
0
0
1
1
1
0
–9
190
0
0
1
1
1
1
–8.5
188
0
1
0
0
0
0
–8
185
0
1
0
0
0
1
–7.5
181
0
1
0
0
1
0
–7
178
0
1
0
0
1
1
–6.5
175
0
1
0
1
0
0
–6
172
0
1
0
1
0
1
–5.5
169
0
1
0
1
1
0
–5
165
0
1
0
1
1
1
–4.5
162
0
1
1
0
0
0
–4
158
0
1
1
0
0
1
–3.5
155
0
1
1
0
1
0
–3
151
0
1
1
0
1
1
–2.5
147
0
1
1
1
0
0
–2
144
0
1
1
1
0
1
–1.5
140
0
1
1
1
1
0
–1
136
0
1
1
1
1
1
–0.5
133
1
0
0
0
0
0
0
129
1
0
0
0
0
1
0.5
125
1
0
0
0
1
0
1
122
1
0
0
0
1
1
1.5
118
1
0
0
1
0
0
2
114
1
0
0
1
0
1
2.5
111
1
0
0
1
1
0
3
107
1
0
0
1
1
1
3.5
103
1
0
1
0
0
0
4
100
1
0
1
0
0
1
4.5
96
1
0
1
0
1
0
5
93
1
0
1
0
1
1
5.5
89
1
0
1
1
0
0
6
86
1
0
1
1
0
1
6.5
83
1
0
1
1
1
0
7
80
1
0
1
1
1
1
7.5
77
1
1
0
0
0
0
8
73
1
1
0
0
0
1
8.5
70
1
1
0
0
1
0
9
68
1
1
0
0
1
1
9.5
65
1
1
0
1
0
0
10
62
1
1
0
1
0
1
10.5
59
1
1
0
1
1
0
11
57
(1)
RIN(kΩ, typical) = 258/(1 + 10GAIN/20)
The PCM1850A/1851A becomes mute for PG[5:0] values other than those listed.
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SERIAL AUDIO DATA INTERFACE
The PCM1850A/1851A interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3).
Interface Mode
The PCM1850A/1851A supports both master and slave modes as interface modes, and they are selected by
mode control via the serial port as shown in Table 4.
In master mode, the PCM1850A/1851A provides the timing for serial audio data communications between the
PCM1850A/1851A and the digital audio processor or external circuit. While in slave mode, the PCM1850A/1851A
receives the timing for data transfer from an external controller.
Table 4. Interface Mode
MD1
MD0
INTERFACE MODE
0
0
Slave mode (256 fS, 384 fS, 512 fS, 768 fS) (default)
0
1
Master mode (256 fS)
1
0
Master mode (384 fS)
1
1
Master mode (512 fS)
Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated
in the clock and timing control circuit of the PCM1850A/1851A. The frequency of BCK is fixed at 64 × LRCK. A
768-fS system clock is not available in master mode.
Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1850A/1851A accepts the 64 BCK/LRCK or 48
BCK/LRCK (only for 384 fS SCKI) format. A 768-fS system clock is not available for fS = 88.2 kHz and 96 kHz in
slave mode.
Data Format
The PCM1850A/1851A supports four audio data formats in both master and slave modes, and they are selected
by mode control via the serial port as shown in Table 5. Figure 23 illustrates the data formats in both slave and
master modes.
Table 5. Data Format
18
FORMAT NO.
FMT2
FMT1
FMT0
FORMAT
0
1
0
1
Left-justified, 24-bit
1
1
0
0
I2S, 24-bit, (default)
2
0
0
0
Right-justified, 24-bit
3
0
1
1
Right-justified, 16-bit
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FORMAT 0: FMT[2:0] = 101b
24-Bit, MSB-First, Left-Justified
LRCK
Left-Channel
Right-Channel
BCK
DOUT
1
2
3
22 23 24
MSB
1
LSB
2
3
22 23 24
MSB
1
LSB
FORMAT 1: FMT[2:0] = 100b
24-Bit, MSB-First, I2S
LRCK
Left-Channel
Right-Channel
BCK
DOUT
1
2
3
22 23 24
1
LSB
MSB
2
3
22 23 24
LSB
MSB
FORMAT 2: FMT[2:0] = 000b
24-Bit, MSB-First, Right-Justified
Left-Channel
LRCK
Right-Channel
BCK
DOUT
24
1
2
3
22 23 24
MSB
LSB
1
2
3
22 23 24
MSB
LSB
FORMAT 3: FMT[2:0] = 011b
16-Bit, MSB-First, Right-Justified
Left-Channel
LRCK
Right-Channel
BCK
DOUT
16
1
2
MSB
3
14 15 16
LSB
1
2
3
MSB
14 15 16
LSB
T0016-16
Figure 23. Audio Data Format
(LRCK, BCK Work as Inputs in Slave Mode and Outputs in Master Mode)
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Interface Timing
Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively.
t(LRCP)
1.4 V
LRCK
t(BCKL)
t(LRSU)
t(BCKH)
t(LRHD)
1.4 V
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DOUT
T0017-02
SYMBOL
PARAMETER
t(BCKP)
BCK period
t(BCKH)
t(BCKL)
MIN
TYP
MAX
UNIT
150
ns
BCK pulse duration, HIGH
60
ns
BCK pulse duration, LOW
60
ns
t(LRSU)
LRCK setup time to BCK rising edge
20
ns
t(LRHD)
LRCK hold time to BCK rising edge
20
ns
µs
t(LRCP)
LRCK period
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
10
20
ns
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
20
ns
tr
Rise time of all signals
10
ns
tf
Fall time of all signals
10
ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are measured from 10% to 90% of
IN/OUT signal swing. Load capacitance of DOUT is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: LRCK, BCK Work as Inputs)
20
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t(LRCP)
0.5 VDD
LRCK
t(BCKL)
t(BCKH)
t(CKLR)
0.5 VDD
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DOUT
T0018-02
SYMBOL
PARAMETER
t(BCKP)
BCK period
t(BCKH)
BCK pulse duration, HIGH
t(BCKL)
BCK pulse duration, LOW
t(CKLR)
Delay time, BCK falling edge to LRCK valid
t(LRCP)
LRCK period
t(CKDO)
Delay time, BCK falling edge to DOUT valid
t(LRDO)
Delay time, LRCK edge to DOUT valid
MIN
TYP
MAX
UNIT
150
1/(64 fS)
1000
ns
60
0.5 t(BCKP)
400
ns
60
0.5 t(BCKP)
400
ns
–10
20
ns
60
µs
–10
20
ns
–10
20
ns
10
1/fS
tr
Rise time of all signals
10
ns
tf
Fall time of all signals
10
ns
NOTE: Timing measurement reference level is 0.5 VDD. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load
capacitance of all signals is 20 pF.
Figure 25. Audio Data Interface Timing (Master Mode: LRCK, BCK Work as Outputs)
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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
In slave mode, the PCM1850A/1851A operates under LRCK, synchronized with system clock SCKI. The
PCM1850A/1851A does not need a specific phase relationship between LRCK and SCKI, but does require the
synchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCKs/frame (±5 BCKs for 48
BCKs/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS
and digital output is forced into the BPZ code until resynchronization between LRCK and SCKI is completed.
In the case of changes less than ±5 BCKs for 64 BCKs/frame (±4 BCKs for 48 BCKs/frame), resynchronization
with simultaneous discontinuity in the digital output does not occur.
Figure 26 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1850A/1851A might generate some noise in the audio signal. Also, the transition of
normal to undefined data and undefined or zero data to normal creates a discontinuity of data in the digital
output, which could generate some noise in the audio signal.
It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate,
interface mode, or data format is changed.
Resynchronization
Synchronization Lost
State of Synchronization
SYNCHRONOUS
ASYNCHRONOUS
SYNCHRONOUS
1/fS
DOUT
NORMAL DATA
32/fS
UNDEFINED
DATA
ZERO DATA
NORMAL DATA
T0020-05
Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization
Power-Down Control
RST (pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section is
shut off and the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK is
recommended to minimize power dissipation.
RST
POWER-DOWN MODE
LOW
Reset and power-down modes
HIGH
Normal operation mode
Overflow Flag Output
The PCM1850A/1851A has an output flag (pin 4) that indicates when overflow occurs in the L-channel or
R-channel, and this flag remains HIGH at least during the 8192/fS time for a momentary overflow occurrence.
HPF Bypass Control
The built-in HPF function for dc component rejection can be bypassed via the serial port. In bypass mode, the dc
component of the analog input signal, the internal dc offset, etc., are converted and included in the digital output
data.
22
BYP
HPF (HIGH-PASS FILTER) MODE
0
Normal (no dc component on DOUT) mode (default)
1
Bypass (dc component on DOUT) mode
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System Reset Control
The system reset control is used to resynchronize the system via the serial port when the system clock
frequency, interface mode, and data format are changed. Change them while SRST = LOW. If they are changed
during normal operation, analog performance can be degraded.
SRST
SYSTEM RESET
0
Resynchronization
1
Normal operation (default)
Mode Register Reset Control
The MRST bit is used to reset the mode control register to its default settings via the serial port.
MRST
MODE REGISTER RESET
0
Set default value
1
Normal operation (default)
SPI SERIAL CONTROL PORT FOR MODE CONTROL (PCM1850A)
The user-programmable built-in functions of the PCM1850A can be controlled through a serial control port with
the SPI format. All operations for the serial control port use 16-bit data words. Figure 27 shows the control data
word format. The most-significant bit must be set to 0. Seven bits, labeled IDX[6:0], set the register index (or
address) for write operations. The least-significant eight bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 28 shows the functional timing diagram for writing to the serial control port. MS (pin 30) is held at a logic-1
state until a register needs to be written. To start the register write cycle, MS is set to logic-0. Sixteen clocks are
then provided on MC (pin 31), corresponding to the 16 bits of the control data word on MD (pin 32). After the
sixteenth clock cycle has completed, the data is latched into the indexed mode control register in the write
operation. To write the next data word, MS must be set to 1 once.
LSB
MSB
0
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
D7
D6
D5
D4
Register Index (or Address)
D3
D2
D1
D0
Register Data
R0001-01
Figure 27. Control Data Word Format for MD
MS
MC
MD
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
IDX6
T0048-04
Figure 28. Serial Control Format
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CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A)
Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850A. These timing
parameters are critical for proper control port operation.
t(MHH)
MS
1.4 V
t(MSS)
t(MCL)
t(MCH)
t(MSH)
MC
1.4 V
t(MCY)
LSB
MD
1.4 V
t(MDS)
t(MDH)
T0013-06
SYMBOL
(1)
PARAMETER
MIN
MAX
UNIT
t(MCY)
MC pulse cycle time
100
ns
t(MCL)
MC LOW-level time
40
ns
t(MCH)
MC HIGH-level time
40
ns
t(MHH)
MS HIGH-level time
80
ns
t(MSS)
MS falling edge to MC rising edge
15
ns
time (1)
t(MSH)
MS hold
15
ns
t(MDH)
MD hold time
15
ns
t(MDS)
MD setup time
15
ns
MC rising edge for LSB to MS rising edge
Figure 29. PCM1850A Control Interface Timing
I2C SERIAL CONTROL PORT FOR MODE CONTROL (PCM1851A)
The user-programmable built-in function of the PCM1851A can be controlled through the I2C-format serial control
port, SDA (pin 32) and SCL (pin 31). The PCM1851A supports the I2C serial bus and the data transmission
protocol for standard mode as a slave device. This protocol is explained in I2C specification 2.0.
Slave Address
MSB
1
LSB
0
0
1
0
1
ADR
R/nW
The PCM1851A has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory
preset to 100101. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
pin (pin 30). A maximum of two PCM1851As can be connected on the same bus at one time. Each PCM1851A
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address with read/write bit,
data if write or acknowledgement if read, and stop condition. The PCM1851A supports only slave receivers, so
the R/W bit must be set to 0.
24
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PCM1851A
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SLES173 – MARCH 2006
SDA
SCL
St
1−7
8
9
1−8
9
1−8
9
9
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
Start
Condition
Sp
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
Stop
Condition
Transmitter
M
M
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
ACK
Sp
M: Master Device
St: Start Condition
S: Slave Device
Sp: Stop Condition
T0049-05
2
Figure 30. Basic I C Framework
Write Operation
The PCM1851A has only the write mode. A master can write to any PCM1851A registers using single or multiple
accesses. The master sends a PCM1851A slave address with a write bit, a register address, and the data. If
multiple access is required, the address is that of the starting register, followed by the data to be transferred.
When the data are received properly, the index register is incremented by 1 automatically. When the index
register reaches 33h, the next value is 31h. When undefined registers are accessed, the PCM1851A does not
send an acknowledgement. Figure 31 is a diagram of the write operation. The register address and the write data
are 8 bits and MSB-first format.
Transmitter
M
M
M
S
M
S
M
S
M
S
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
M: Master Device S: Slave Device
St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition
R0002-03
Figure 31. Framework for Write Operation
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PCM1851A
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SLES173 – MARCH 2006
TIMING DIAGRAM
Start
Repeated Start
Stop
t(D-HD)
t(BUF)
t(D-SU)
t(SDA-F)
t(P-SU)
t(SDA-R)
SDA
t(SCL-R)
t(RS-HD)
t(LOW)
SCL
t(S-HD)
t(HI)
t(RS-SU)
t(SCL-F)
T0050-01
SYMBOL
PARAMETER
MIN
UNIT
100
kHz
f(SCL)
SCL clock frequency
t(BUF)
Bus free time between STOP and START conditions
4.7
µs
t(LOW)
Low period of the SCL clock
4.7
µs
t(HI)
High period of the SCL clock
4
µs
t(RS-SU)
Setup time for START/repeated START condition
4.7
µs
t(S-HD), t(RS-HD)
Hold time for START/repeated START condition
4
µs
t(D-SU)
Data setup time
250
t(D-HD)
Data hold time
0
900
ns
t(SCL-R)
Rise time of SCL signal
20 + 0.1 CB
1000
ns
t(SCL-F)
Fall time of SCL signal
20 + 0.1 CB
1000
ns
t(SDA-R)
Rise time of SDA signal
20 + 0.1 CB
1000
ns
t(SDA-F)
Fall time of SDA signal
20 + 0.1 CB
1000
t(P-SU)
Setup time for STOP condition
ns
CB
Capacitive load for SDA and SCL lines
VNH
Noise margin at HIGH level for each connected device (including hysteresis)
400
0.2 VDD
Submit Documentation Feedback
ns
µs
4
Figure 32. PCM1851A Control Interface Timing Requirements
26
MAX
pF
V
PCM1850A
PCM1851A
www.ti.com
SLES173 – MARCH 2006
MODE CONTROL REGISTERS
User-Programmable Mode Control Functions
The PCM1850A/1851A has several user-programmable functions which are accessed via control registers. The
registers are programmed using the serial control port which is discussed in the SPI Serial Control Port for Mode
Control (PCM1850A) and I 2C Serial Control Port for Mode Control (PCM1851A) sections of this data sheet.
Table 6 lists the available mode control functions, along with their reset default conditions and associated register
index.
Register Map
The mode control register map is shown in Table 7. Each register includes an index (or address) indicated by the
IDX[6:0] bits B[14:8].
Table 6. User-Programmable Mode Control Functions
FUNCTION
Mode register reset
RESET DEFAULT
REGISTER
BIT(S)
Normal operation
31
MRST
PGA gain control
–11 dB
31
PG[5:0]
Channel 1
32
CH[2:0]
HPF enable
33
BYP
Normal operation
33
SRST
Audio interface mode control
Slave
33
MD[1:0]
Audio interface format control
I2S
33
FMT[2:0]
Multiplexer input channel control
HPF bypass control
System reset
Table 7. Mode Control Register Map
HEX
B15
B14
B13
B12
B11
B10
B9
B8
Register 31
0
0
1
1
0
0
0
1
RSV (1) MRST
Register 32
0
0
1
1
0
0
1
0
RSV (1) RSV (1) RSV (1) RSV (1) RSV (1)
Register 33
0
0
1
1
0
0
1
1
(1)
B7
BYP
B6
B5
B4
B3
B2
B1
B0
PG5
PG4
PG3
PG2
PG1
PG0
SRST RSV (1)
MD1
MD0
CH2
CH1
CH0
FMT2
FMT1
FMT0
RSV bits must be always written as 0. No values can be written in address 30h.
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PCM1850A
PCM1851A
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SLES173 – MARCH 2006
APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
The following figure illustrates a typical circuit connection diagram for six stereo inputs and an analog monitor.
Analog Input/Output
C17 C16 C15 C14 C13 C12 C11 C10
+
23
22
21
20
19
18
17
VINL6
VINR5
VINL5
VINR4
VINL4
VINR3
VINL3
25 VREFS
VINR2 16
26 VREF1
VINL2 15
27 VREF2
VINR1 14
28 Vcc
VINL1 13
PCM1850A/1851A
MOUTL 12
30 MS (ADR)(1)
MOUTR 11
31 MC (SCL)(1)
RST 10
32 MD (SDA)(1)
TEST1 9
TEST0
29 AGND
SCKI
Control
24
VDD
C1
0V
+
DGND
+
+
OVER
C3
+5 V
+
DOUT
+
+
BCK
C4
+
+
LRCK
+
C5
+
VINR6
+
1
2
3
4
5
6
7
8
+
+
+
+
+
+
C9
C8
C7
C6
C19
C18
C2
+
3.3 V
(1)
Audio Data Processor
PCM1850A (PCM1851A)
S0181-01
NOTE: C1, C2: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended, depending on layout and power supply.
C3, C4, C5: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended.
C6–C17: A 0.33-µF capacitor gives a 2.9-Hz (τ = 0.33 µF × 169 kΩ) typical cutoff frequency at the HPF input in normal
operation, and it requires power-on settling time with a 56-ms time constant in the power-on initialization period.
Cutoff frequency and time constant depend on PGA gain. Cutoff frequency varies from 2.4 Hz to 8.5 Hz for 0.33 µF.
DC-coupled input is inhibited for the analog input, VINL[1:6] and VINR[1:6].
C18–C19: A 2.2-µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.
28
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PCM1851A
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SLES173 – MARCH 2006
APPLICATION INFORMATION (continued)
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD Pins
The digital and analog power supply lines to the PCM1850A/1851A must be bypassed to the corresponding
ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize
the dynamic performance of the ADC.
AGND, DGND Pins
To maximize the dynamic performance of the PCM1850A/1851A, the analog and digital grounds are not
connected internally. These grounds must have low impedance to avoid digital noise feeding back into the
analog ground. Therefore, they should be connected directly to each other under the parts to reduce the potential
of a noise problem.
VINL[1:6], VINR[1:6] Pins
A 0.33-µF capacitor is recommended as the ac-coupling capacitor, which gives a 2.4- to 8.5-Hz cutoff frequency.
If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to each VINxx
pin, but a signal source resistance less than 1 kΩ is recommended for these pins in order to keep accuracy of
the gain control command and to maintain crosstalk performance.
MOUTL, MOUTR Pins
An ac-coupled light load is recommended; a 2.2-µF capacitor with a 10-kΩ load gives a 7.2-Hz cutoff frequency.
VREF1, VREF2, VREFS Pins
Between VREF1 and AGND, VREF2 and AGND, and VREFS and AGND, 0.1-µF ceramic and 10-µF electrolytic
capacitors are recommended to ensure low source impedance of the ADC references. These capacitors should
be located as close as possible to the VREF1, VREF2, and VREFS pins to reduce dynamic errors on the ADC
references. The differential voltage between VREF2 and AGND sets the analog input full-scale range.
BCK and LRCK Pins (in Master Mode), DOUT Pin
These pins have enough load-driving capability. However, if the output line is long, locating a buffer near the
PCM1850A/1851A and minimizing load capacitance is recommended in order to minimize the digital-analog
crosstalk and maximize the dynamic performance of the ADC.
System Clock
Because the PCM1850A/1851A operates based on a system clock, the quality of the system clock can influence
dynamic performance. Therefore, it is recommended to consider the system clock duty, jitter, and the time
difference between the system clock transition and the BCK or LRCK transition in slave mode.
Submit Documentation Feedback
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCM1850APJT
ACTIVE
TQFP
PJT
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1850APJTG4
ACTIVE
TQFP
PJT
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1850APJTR
ACTIVE
TQFP
PJT
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1850APJTRG4
ACTIVE
TQFP
PJT
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1851APJT
ACTIVE
TQFP
PJT
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1851APJTG4
ACTIVE
TQFP
PJT
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1851APJTR
ACTIVE
TQFP
PJT
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCM1851APJTRG4
ACTIVE
TQFP
PJT
32
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM1851APJTR
Package Package Pins
Type Drawing
TQFP
PJT
32
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
16.8
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM1851APJTR
TQFP
PJT
32
1000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
0,20
M
0,20
0,09
Gage Plane
32
0,15
0,05
1
0,25
0°– 7°
7,00 SQ
0,75
0,45
9,00 SQ
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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