DISCOVER - Loughborough University
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DISCOVER: Design and Simulation of Complex Low Volume Electronics Production by Dr Andrew A. West DISCOVER GROUP Paul Conway Chris Hinde Diana Segura David Whalley Tony Wilson Loughborough University Loughborough University - Wednesday 21 September 2006 DISCOVER 2 Industrial Context The Challenge Aims and Objectives Methodology Deliverables Current Status Questions? Industrial Context 3 The Challenge What are the reasons for poor first time yield and long term reliability in complex products? 4 Defects generated during the manufacturing flow, Lack of formalised process knowledge, Lack of knowledge concerning the implications of design features on manufacturing performance, Lack of in process performance monitoring and analysis, The impact of new materials and components e.g. (lead free legislation) Lack of knowledge of the impact of the adoption of new technology (e.g. novel agile approaches to reflow oven technology). Aims and Objectives Understand the causes of poor manufacturing performance within the low volume electronics manufacturing domain… Develop a suite of software tools that can enable models of complete design, manufacturing and business processes (throughout the entire product lifecycle) in terms of their propensity to create defects that could cause product failure, Reduce a products manufactured cost and time to market and enhance its quality, Enable simulation of new designs and the impact of design, manufacturing and business strategies, Enable the optimisation of designs and manufacturing processes for yield, quality and reliability. 5 Methodology Activities 6 Analysis of the causes of poor yield and service failure design and / or manufacturing processes, Mapping generic electronics design procedures into welldefined process steps, Modelling the defect causing propensity of each process, Developing knowledge-based software tools that capture both the design and manufacturing processes and defect causing propensity, Determining new product and new technology introduction scenarios to enable the software tools to be evaluated, Evaluation of the software tools from functional, human factors and business perspectives. Methodology: Work Packages WP1: Analysis of cause of poor yield and service performance WP2: Generic Design and Manufacturing Process Steps WP3: Design and Manufacturing Defect – Process Mapping WP4: Development of Component-Based (CB) simulation tool WP5: Evaluation of CB simulation tool for design and process optimisation WP6: Dissemination and Exploitation 7 Deliverables 8 A methodology for capturing and describing the linkages between design and manufacturing process variables and yield, product reliability, cost and quality A component based framework for constructing static (i.e. visual) and dynamic (i.e. enactable via computer-based simulation) process representations A lifecycle model of a design and production facility capable of simulating process yield and guiding product or process design Current Status ID Task Name 1 WP1 Test and service Data Capture 326 days? Mon 16/01/06 10 WP2 Assembly Process Flow Map 194 days? Mon 16/01/06 Start 11 Milestone2 - Initial Processes Mapped 0 days Fri 02/06/06 12 Milestone3 - Completion of process mapping 0 days Fri 13/10/06 13 Scope detail level required 164 days? Mon 16/01/06 14 Iniital process maps for all partners 15 16 83 days Wed 08/02/0 Capture partner process flows and process variations 160 days Mon 06/02/06 Capture partner design rules 33 days Mon 15/05/06 17 Encoding of DFM rules - Goodrich 18 days Mon 15/05/06 18 Encoding of DFM rules - Smiths 18 days Mon 15/05/06 19 Encoding of DFM rules - STI 11 days Mon 15/05/06 20 Iterative cycle of refining rules with expert support 12 days Tue 30/05/06 21 Creation of Rule-Based System 10 days Thu 15/06/06 22 Develop generic process flow with options (including rework) 140 days Sat 01/04/0 23 WP3 Individual Process step defect modelling 291 days Mon 21/08/06 0 days Fri 02/03/07 24 9 Duration Milestone5 - Define all processes 50% modelled Assembly Process Flow - Vision ed on feedbac k Circuit Designers Manufacturing Engineers Visualising Processes using BPM Tools Knowledge of Manufacturing Electronics Methods: Study of available documentation, visits, questionnaire, structured interview (based on adopted EM approach) TO-BE Processes (After Implementing CBT) 10 Information Time Cost Manufacturing engineers ion check bas End-User Processes (Current Practice) Model validat Circuit Designers End-User Requirements EM : refers to Enterprise Modelling Approaches such as GERAM, PERA, GRAI, CIMOSA (adopted in this project) BPM : refers to Business Process Modelling Tools such as ProcessWise, SysytemArchitecture, IThink (adopted in this project) Simulation and Demonstration of Current Practice Maintenance Testing & Installation Comparison Building BP Models Formalising Business Processes using EM approaches Simulation and Demonstration of Systems after Analysis Knowledge Elicitation Phase Modelling & Visualisation Phase What If Analyses & Assessment Phase Assembly Process Flow – Constructs “Real” World Processes CIMOSA Domain Context Diagram Non-CIMOSA Domain Activity Domain Processes Interaction Diagram Information Human Resource Structure Diagram Business Processes Physical Resource Finance Activity Diagram External Links Enterprise Activities Abstraction Mechanisms 11 Events Flow of Res./Mat. Flow of Process Alternative Flow Assembly Process Flow –Context Diagram C o ntext D iagram – G eneric L e ve l V iew D ISC O V E R P rod uc t D evelopm e nt P rod uc tion P rod uc t R ealization D P 7: M an u factu rin g S et-u p D P 3: P rod u ct Q u alification D P 1: P rod u ct D esign D P6: C om m ercia lised D esign to M an f D P 4: V ertica lly In tegrated D esign to M an f D P 2: P rocess D evelop m en t D P 9: T est D P 8: M an u factu rin g O p eration s D P 5: P a ra lle l D esign to M an u factu re C IM O S A D o m ain A ctivity N o n -C IM O S A D o m ain E vent( s) Info rm atio n Hu m an R esou rce Ph ysical R e so u rce F in an ce E xte rn al L in ks C o m plex L O w V olum e E lectro nic System s – P rocess M o delling T itle: 12 O vera ll C o nte xt D ia gra m N u m b er: X X X X D iag F lo w o f R e s./M at. F lo w o f P ro ces s D esign by: D iana Segura & T ony W ilson C hecked by: Last update: 19/09/2006 A ltern ative F low W olfson School of M ech an ical & M anufacturing E ngineering 2 Assembly Process Flow – Activity Diagram BPx.x.x Sub-process - Generic Process Set-up BPx.x.x - Pxxx Process Set Up Required Build Schedule EAX.X.X Product Set-Up Data i.e. EA7.1.1.1 Assembly Drawings EA7.1.1.2 ECNs EA7.1.1.3 Build Standard EA7.1.1.4 SMTKiting List EA7.1.1.5 SMT Layout Drawings EA7.1.1.6 SMT Process Chemistry List EA7.1.1.7 SMT Process Chemistry List EA7.1.1.8 PTHKiting List EA7.1.1.9 PTHLayout Drawings EA7.1.1.10 PTHProcess Tooling List EA7.1.1.11 Mechanical Components Kiting List EA7.1.1.12 Mechanical Component Layout Draw's EA7.1.1.13 Mechanical Assembly Tooling List EA7.1.1.14 Wave Solder Process Chemistry List EA7.1.1.15 Wave Solder Process Tooling List EA7.1.1.16 NSPinstructions &Drawings EA7.1.1.17 NSPChemistry List EA7.1.1.18 NSPTooling List EA7.1.1.19 Test Specs. EA7.1.1.20 Bom BPx.x.x Verify Process Parameter Input Data File Correlates With Prod ID EAX.X.X EAX.X.X Product Set-Up Data Input Process Set-up Parameters Define Set-up Parameter Adjustments EAX.X.X * ValidationVehicle e.g. Set-up Board, Sticky Board, Profile Board etc * Production Released Product Tooling * Process Chemicals * SMT, PHT, Mech Comp Kits etc. Produce First-off Yes EAX.X.X EAX.X.X Verify (Inspect or Test) First-off Define Defect Opportunity Cause Fail * Verification Equipment e.g. Paste Height/ Volume Measuring Kit, Magnifiers, SMT Overlays, Comp locator Software, API, AOI, AXI, FPT, ICT, FCT, etc No Validated First-Off (Pass Inspection or Test Stage) Pass EAX.X.X Validate Process Set-up As Production Ready Generic Manufacturing Set up 13 Can Defect Opportunity Be Negated During Set-up BPx.x.x - Pxxx Process Set Up With Defect Opportunity Concessions BPx.x.x - Pxxx Process Set Up Validated Assembly Process Flow – Activity Diagram DP7 (Manf Set-up) / BP7.3.2 - (Subprocess - PTH Kitting Setup) Process Set-up Completed No Do Component Leads Require Tinning DP8 (Manf Ops) / K300 (PTH & Mech Comp Kitting) Manf Op Completed Yes Company Standard - 0615-009 Requirements For Soft Soldered Electrical Connections EAX.X.X EAX.X.X.X Liquid Flux & Dip Tank Dip Flux Component Leads EAX.X.X.X Tin/Lead & Solder Bath Dissolve Gold Plating in Sacrificial Tin/Lead Bath PTH Operator EAX.X.X.X Liquid Flux & Dip Tank Dip Flux Component Leads EAX.X.X.X Tin/Lead & Solder Bath Lead Tinning 14 Dip Coat Leads in Uncontaminated Tin/Lead Bath Assembly Process Flow - Cause-Effect Diagram BP1.2 Product Architecture BP1.1 DFx Rules Product Development Product Realisation DP4: Vertically Integrated (i.e. Internal Production Model) DP1: Product Design BP3.2 Process Tooling Pre-qualification Generic Ishikawa.igx BP4.1 Internal NPI (New Product Introduction) BP3.1 Process Chemistry Pre-qualification BP5.1 Internal NPI With External Sub-assembly DP5: Parallel (i.e. Production Model Includes Internal & Outsourcing) BP6.1 BP6.2 Eternal NPI New Contract Introduction DP2: Process Dedvelopment BP2.2 BP2.1 Reliability Functionality Pre-qualification Pre-qualification DP6: Comercialised (i.e. Part Of Or All Of The DTM Sequence Outsourced) DP3: Product Qualification BP7.1 Documentation BP8.1 Comp & PCB Prep BP7.2 PCB Prep BP8.2 Side 1 SMT BP7.3 Component Loading BP7.4 SMT Processes BP7.5 PTH & Pre-wave BP7.6 Wave & Post Wave BP7.7 PCA Test & Rework BP8.3 Side 2 SMT BP8.4 PTH & Pre-wave Mech Comps BP8.5 Wave Soldering & Post-wave Mech Component Hand Soldering BP8.6 PCA Test BP7.8 PCA Completion BP8.7 PCA Completion BP7.9 Module Assy & Test BP7.10 Unit Assy & Test DP7: Manufacturing Set-up 15 BP8.9 Unit Assembly & Test DP8: Manufacturing Operations BP9.1 INTERNAL FAILURES: Inherent Defects In A Product's Mechanical Integrity That Are Detected During Printed Circuit Assembly & iTest (i.e.Yield) Inherent Defects In A Product's Mechanical Integrity That Are Detected During Environmental Stress Screening (i.e. Captured Infant Mortalities) Effects: BP9.1 Internal Failures BP9.2 External Failures BP9.2 EXTERNAL FAILURES: Inherent Defects In A Product's Mechanical Integrity That Cause Sporadic Early Life Field Failures (i.e Escaping Infant Mortalitiity Failures) Inherent Deficiencies In A Product's Mechanical Integrity That Cause Systematic Premature Inservice Stress Related Wear-out (i.e. Fatigue Resistance Failures Partners Design Rules – Vision 16 Partners Design Rules - Knowledge Elicitation Encoding DFM rules into “IF – THEN” rules (e.g. IF Thinner circuits are required THEN Use dedicated fixtures AND Vacuum clamping) Validation of the rules with experts Link rules to defect opportunity i.e. effect on reliability Inclusion of defect costs Inclusion of rule metrics Generation of common rules clustering Unification of Vocabulary across industrial partners Comparison with high volume electronics Comparison with International Standards Trial of commercial rule-based software 17 Partners Design Rules - Example ATTRIBUTES / CHECKS >> Solder? Finish RULES AND BEST PRACTICE >> Solder ? Finish IF THE MINIMUM THICKNESS OF TIN-LEAD BEFORE REFUSING/REFLOWING IS BE 0,15um. THEN THE BOARD IS TO HAVE A 60/40 REFUSED/REFLOWED TINLEAD SOLDER FINISH IF OVER 0,06um TO 0,12um THICK IMMERSION GOLD OR OVER 3um TO 9um THICK ELECTROLESS NICKEL. THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH IF OVER ELECTROLESS NICKEL 3um TO 9um THICK. THEN GOLD IMMERSION PLATE 0,06 TO 0,12um THICK, FINISH THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH The outer layers should have a FINISH NOTE, as determined by the Process Department. IF 18 Partners Design Rules – Metrics and Defects METRICS 19 DEFECTS AND REQUIREMENTS visual inspection THIS THICKNESS IS CRITICAL TO FACILITATE SUBSEQUENT REFLOW TECHNIQUES ON ASSEMBLY. NOT preferred for future designs (WHY?) visual inspection this was introduced to overcome soldering issues with Circast gold on Trent 500. NOT preferred for future designs (WHY?) visual inspection this is the preferred method for PCB’s with vias that may not solder fill and for reflow soldered Surface Mount Cards visual inspection this is the current standard solder finish for discrete plated through hole PCB DISCOVER 20 Industrial Context The Challenge Aims and Objectives Methodology Deliverables Current Status Questions?
