COURSE OUTLINE
1. GENERAL
SCHOOL
DEPARTMENT
LEVEL OF STUDY
COURSE UNIT CODE
TECHNOLOGICAL APPLICATIONS
COMPUTER SYSTEMS ENGINEERING
UNDERGRADUATE
SEMESTER OF STUDY
244506, 245506
5th
COURSE TITLE VHDL and FPGA design
COURSEWORK BREAKDOWN
Lectures
Laboratory experiments
TEACHING
WEEKLY HOURS
2
2
4
COURSE UNIT TYPE
PREREQUISITES :
LANGUAGE OF INSTRUCTION/EXAMS:
COURSE DELIVERED TO ERASMUS STUDENTS
MODULE WEB PAGE (URL)
ECTS
Credits
5
ElectiveNONE
GREEK
NO
2. LEARNING OUTCOMES
Learning Outcomes
The learning outcomes of the theoretical part are the following:
 Identify the modern development and design of digital systems, develop software using
VHDL
 Examine programmable logic devices (PLDs), CPLDs
 Develop provisions field programmable gateway (FPGA)
 Compose models for various cutting edge technologies (ASICs)
 Organize structured methodology to the design of very large systems
 Explain the Modeling Combinatorial and Sequential Logic
 Pose Modern and Asynchronous Sequential Circuits
 Organize modeling and arithmetic units
 Support the Optimal Implementation and Control Logic Circuits
General Skills



Search, analysis and data synthesis
Autonomous work
Project design
3. COURSE CONTENTS
Purpose:
The purpose of the course is the presentation of modern development and design of digital systems,
and the implementation and simulation of using VHDL.
Content:
Introduction of modern technologies for implementing digital circuits: SSI, Semi-custom, Full-Custom
and particularly in programmable logic devices (PLDs), CPLDs and field programmable gate arrays
(FPGA). Synthesis of models for various cutting-edge technologies designed for specific applications:
application specific integrated circuits (ASICs). Introduction of modern programming languages of
description hardware circuits, Data Objects, Commands conforming assignment, project entities in
VHDL language, process command, component command. Introduction to learning the VHDL
language. Structured methodology to the design of very large systems. Modeling Combinatorial and
sequential logic. Modern and Asynchronous Sequential Circuits. Modeling of arithmetic units and
Memory Channel. Implementation and control logic optimization. Synthesis with VHDL.
VHDL & FPGA Design Auto Workshop
The purpose of Laboratory VHDL & FPGA is:
The stude ts’ acquaintance with the FPGAs (Field Programmable Gate Array) devices.
Learning the VHDL language and its uses in modern industry
To acquaint the student with the VHDL language through the creation of applications in computer
language
4. TEACHING METHODS - ASSESSMENT
MODE OF DELIVERY Face to face
USE OF INFORMATION AND
COMMUNICATION TECHNOLOGY
TEACHING METHODS
Use of interactive lecture notes and slides to demonstrate
the basic operation of digital systems
Communicate through e-mail and e part of a discussion
group
Method description
Semester Workload
Lectures
26
Laboratory practise
26
Preparation of laboratory
exercises
Search the internet for
FPGA models
Self study
20
Total course hours
125
10
43
ASSESSMENT METHODS
“tude ts’ evaluatio co prises of the :
 Final exam (60%) and

laboratory (40%)
5. RESOURCES
- Recommended Books:
1.
2.
3.
4.
5.
Salcic Z. & Smailagic A., "Digital System Design & Prototyping Using FPGA & HDL", Kluwer
Academic Publishers, 2000.
Parhami B., "Computer Arithmetic: Algorithms and Hardware Designs", Oxford Uiv. Press,
1999.
Hayes J., "Computer Architecture and Organization", Mc Graw-Hil, 3rd Edition, 1998
Salcic, VHDL and FPLDs , Kluwer Academic Publishers, 1998
Hennessy J.-Patterson D., Computer Architecture: A Quantative Approach", Morgan
Kaufmann Publishers, 2nd Edition, 1996.