Fully Integrated PLL Based Clock Generator for
Implantable Biomedical Applications
Garrett Bischof, Ben Scholnick, and Emre Salman
Electrical and Computer Engineering Stony Brook University, New York 11794
gbischof@ic.sunysb.edu, emre@ece.sunysb.edu
Abstract – The design and verification of an ultra low power
phase-locked loop (PLL) with application to implantable
biomedical systems is presented. A systematic PLL design
methodology is introduced, where the first step is a high level
characterization of the system in MATLAB. The second step
involves a transistor level implementation in Cadence using
0.35µm CMOS technology. The proposed low power and low area
PLL consists of a phase-frequency detector, charge pump, secondorder low pass filter, and a ring oscillator based voltage controlled
oscillator (VCO). The final design is fully integrated and has a
power consumption of approximately 492µW. The operating
frequency of the PLL is 6.78MHz, which is the lowest frequency
designated for the Industrial, Scientific, and Medical (ISM) band.
The phase margin and the bandwidth of the PLL are, respectively,
61.9° and 2.96 Mhz.
designed to provide a continuous clock signal. Since the
receiver is implanted within the human body, any circuit within
the chip should consume ultra low power and area. An example
application is a blood sugar monitoring device that is implanted
under the skin to measure patient’s blood sugar.
The rest of the paper is organized as follows. Background
information about PLLs is provided in Section II. System level
design considerations are described in Section III. Transistor
level implementation of the PLL is explained in Section IV.
Simulation results are presented in Section V. Finally, the paper
is concluded in Section VI.
II. BACKGROUND
Keywords- PLL, VCO, implantable device, receiver, clock generator.
I. INTRODUCTION
A phase-locked loop is one of the most critical blocks in
wireless/wire-line communication systems and clock generators
[1]. A PLL is used to recover the clock signal from a corrupted
incoming data signal. The recovered clock signal is used to
sample the data and produce a clean data signal. The PLL is
also used as a synthesizer to generate a stable clock signal from
a reference signal. This clock signal is used for the digital
blocks of a system.
This paper addresses the problem of designing a low power
and low area PLL in 0.35µm CMOS technology for use in
implantable biomedical wireless systems that operate at
6.78MHz. These implantable circuits typically contain digital
blocks for efficient signal processing of the sensed data [2].
Thus, a stable clock signal is required to synchronize these
digital blocks within the receiver. A common approach is to
extract the system clock signal from the carrier signal.
Among different modulation schemes, on-off keying pulseamplitude modulation (PAM) or frequency-shift keying (FSK)
are common schemes due to their relatively simple design and
robustness against highly nonideal transmission medium within
the human body [3]. A primary limitation of these schemes is
that no carrier signal is provided during the off keying intervals.
A dedicated clock generator, i.e., a PLL should therefore be
978-1-4244-9877-2/11/$26.00 ©2011 IEEE
A PLL works by comparing the input data stream (reference
signal) with the output of the voltage controlled oscillator
(VCO) using a phase-frequency detector (PFD).
Any
difference in the phase and frequency of the two inputs of the
PFD causes a predictable output signal which is used by the
charge pump (CP) to either charge or discharge the capacitors
in the low pass filter (LPF). If the VCO output is lagging
behind the reference signal, the PFD will cause the CP to inject
additional current into the LPF. The DC voltage at the output of
the LPF will rise, thereby increasing the output frequency of the
VCO. Once any phase or frequency differences have been
eliminated, the circuit is referred to as “locked”. In the locked
condition, the output signal of a PLL can be used as a stable
clock signal to recover clean data from the corrupted incoming
data signal.
During on keying intervals, the carrier signal is utilized
as the reference signal to synthesize a stable clock signal.
Alternatively, during off keying intervals, the charge pump is
disabled and the voltage of the LPF remains constant. PLL
therefore continues to provide a stable clock signal during each
operation mode of the receiver.
A systematic PLL design methodology is introduced where
the first step is a high level characterization of the system in
MATLAB [4], as shown in Figure 1. The second step is to
select values of the circuit parameters and verify the operation
of the system also using MATLAB. This step ensures that the
system is stable and fundamental constraints can be satisfied,
i.e., system is capable of achieving the lock condition. Then,
the transistor level design is achieved, and simulated with
Cadence Spectre [5], to estimate the power consumption. To
improve the performance of the system, Cadence simulations
are completed with different parameters as well as different
transistor designs. Drawing the physical layout and post layout
verification of the system are the last steps.
The PLL architecture discussed in this paper consists of four
blocks: PFD, charge pump, low pass filter, and VCO. The
charge pump and low pass filter are included to significantly
improve the acquisition range of the PLL [6]. A second order
loop filter is adopted to avoid stability issues and reduce high
frequency jitter.
Figure 3: Second order low pass filter.
In order to ensure stability, the phase margin of the PLL should
be greater than 60°. Also, a bandwidth smaller then the
operating frequency is desirable to reduce high frequency jitter
[6]. Other significant design constraints include low power
dissipation and small chip area.
Understanding the transfer function of the PLL is essential
in determining the optimal values of the low pass filter (LPF)
components, as well as the charge pump (CP) current and VCO
gain. According to control theory, the transfer function of a
closed loop system with negative feedback is given by
(1)
,
1
where HO is the open loop transfer function. The open loop
transfer function of the system is
·
·
(2)
.
Note that the unit of KVCO in (2) is Hz/V. The transfer function
of the second order low pass filter illustrated in Figure 3 is
1
Figure 1: Design method illustrating the seven primary steps.
Replacing (3) in (2) produces
1
III. SYSTEM LEVEL DESIGN
Figure 2 introduces the system level representation of the
6.78MHz PLL and the transfer function of each block.
.
(4)
Finally, replacing (4) in (1) gives
1
1
Figure 2: PLL architecture and the corresponding transfer functions.
(3)
.
.
(5)
The phase margin of the PLL is determined through the
bode plot of HO. The bode plot of HO crosses 0 dB at a specific
frequency. The phase margin is equal to the phase shift at this
frequency plus 180°. There is a tradeoff between the size of R1
and C1, and the phase margin. Smaller values of the low pass
filter parameters permit on-chip integration, but decreasing R1
and C1 also degrades the phase margin. In order to obtain a
phase margin close to 70° while keeping all of the components
on- chip, R1 is selected to be 2KΩ, and C1 to be 800pF.
Table 1: DESIGN PARAMETERS OF THE PLL, PHASE MARGIN, AND
CHARGE PUMP CURRENT*VCO GAIN
Value
R1
2KΩ
C1
800pF
Value
Phase Margin
61.9°
C2
50pF
ICP*KVCO
1020A/Vs
Bandwidth
2.95MHz
.
PHASE MARGIN AS A FUNCTION OF KVCO*ICP
70
X: 1286
Y: 62.7
Bode diagram
150
50
Magnitude (dB)
PHASE MARGIN (degrees)
60
40
30
100
50
0
-50
20
-100
-90
0
0
1000
2000
3000 4000 5000
ICP*KVCO (A/V*s)
6000
7000
8000
Phase (deg)
10
-120
-150
Figure 4: Relationship between phase margin and Kcp*ICP.
-180
2
10
3
4
10
5
10
6
10
10
7
10
8
10
Frequency (Hz)
Figure 5: Open loop transfer function to evaluate stability.
Bode diagram
20
Magnitude (dB)
0
-20
-40
-60
-80
-100
0
Phase (deg)
As determined by (4) and (5), KVCO and ICP always appear
multiplied together, so in this part of the analysis, they can be
treated as a single parameter since it is their combined value
that determines the phase margin and bandwidth of the system.
Later, the values of ICP and KVCO can be individually selected to
minimize power disipation, ripple on the VCO control voltage,
and to achieve an appropriate duty cycle for the VCO. As
shown in Figure 4, the maximum phase margin occurs when the
value of ICP*KVCO is 1286A/Vs. There is a direct relationship
between ICP*KVCO and the power dissipation of the system. In
this design, ICP*KVCO is selected to be 1020A/Vs. This produces
a phase margin of 61.92° and a bandwidth of 2.95MHz.
Achieving a phase margin greater than 60° is a more important
design constraint than achieving a smaller bandwidth. Since C1
is already at a maximum size to fit on the chip, the only way to
further decrease the bandwidth is to decrease R1 or ICP*KVCO.
Decreasing either of these values will also decrease the phase
margin. Since the phase margin cannot be reduced any further,
the final parameters for the PLL are: R1 = 2KΩ, C1 = 800pF, C2
= 50pF, and ICP*KVCO = 1020A/Vs. C2 is selected to be 50pF in
order to reduce the ripple on the VCO control voltage.
Increasing C2 any further will decrease the phase margin.
Figures 5 and 6 show, respectively, the bode plots of the open
and closed loop transfer functions. Table 1 summarizes the
parameter selection of the PLL.
-45
-90
-135
-180
3
10
4
10
5
10
6
10
7
10
Frequency (Hz)
Figure 6: Closed loop transfer function to evaluate bandwidth and peaking.
8
10
The next step is to verify that the PLL is able to obtain the
locked condition. This verification is completed in Simulink
using the model shown in Figure 7.
Figure 8: Conceptual diagram of the PFD consisting of two D type flip-flops
and a NOR gate.
Figure 7: Simulink implementation of a PLL to verify stability and obtain
locked condition.
IV. TRANSISTOR LEVEL DESIGN
After the system level design of the PLL has been completed
and the PLL operation has been verified, as described in the
previous section, the next step is to achieve the transistor level
design of the PFD, CP, and VCO using 0.35µm CMOS with a
reduced power supply of 2Volts.
A. Phase-frequency detector
The PFD is constructed using two true-single-phase-clock
(TSPC) D-flip-flops (DFF), as shown in Figure 9 and a
conventional NOR gate. The D input of the D-flip-flop is
always grounded. This characteristic permits a DFF design
with only six transistors. A small number of transistors makes
this design a good choice to save power and space [7]. These
DFFs are reset when there is logic high at the RESET input,
and the output signal after reset is also logic high.
Figure 10 shows the timing diagram of the PFD and gives
some insight into the operation of the PFD and DFF. Since the
D inputs of the DFFs are grounded, on the rising edge of the
reference signal (VREF), a zero is sent to the output of the first
flip-flop (UP). Then, on the rising edge of the VCO output,
(VVCO), a zero is sent to the output of the second DFF
(DOWN). When UP and DOWN are both zero, the output of
the NOR becomes one, which causes both DFFs to reset, and
the UP and DOWN signals both return to logic high. As shown
in Figure 8, VREF is leading VVCO, this means that the VCO
needs to speed up to match VREF. Correspondingly, Figure 10
shows more zeros in the UP signal than the DOWN signal, this
corresponds to an increase in the VCO control voltage as well
as the VCO output frequency. When the PLL is locked, the UP
and DOWN signals become a nearly constant logic high value.
Figure 9: Transistor level representation of a six transistor flip-flop where the
data input is connected to ground .
Figure 10: PFD timing diagram illustrating the reference voltage, VCO output
voltage, UP, DOWN, and RESET signals.
B. Charge pump and low pass filter
The charge pump is incorporated into the PLL design in
order to increase the acquisition range of the circuit [6]. The
charge pump also has the ability to be easily tuned to meet the
specifications of the circuit. The parameter ICP*KVCO should be
1020A/Vs to achieve a phase margin of 61.9°, as described in
section III. The VCO gain is selected so that the VCO center
frequency is around 6.78MHz. A VCO gain of 8.5MHz/V
makes the center frequency around 6.78MHz. ICP is then
determined by dividing 1020A/Vs by 8.5MHz/V resulting in
120µA. When there is a zero in the UP signal, the PMOS
transistor in the CP as shown in Figure 11 closes and the top
current source charges capacitors C1 and C2. When the DOWN
signal is a zero, the zero gets inverted and produces a one at the
input of the NMOS transistor. This signal closes the NMOS
transistor and the lower current source discharges the two
capacitors. The voltage Vctrl controls the frequency of the VCO.
circuitry required for differential operation, the VDD-Vctrl input
is grounded. This technique causes the top transistor of the
transmission gate to be constantly conducting. Vctrl controls the
VCO frequency by adjusting the resistance of the lower
transistor in the transmission gate. The greater Vctrl is, the
smaller the transmission gate resistance will be. From (6) and
(7), a lower transmission gate resistance means a greater VCO
frequency.
The gain of this VCO is adjusted by altering the W/L ratios of
the transistors until the center frequency is approximately
6.78MHz. This produces a VCO gain of 8.5MHz/V. Voltagefrequency characteristics of the VCO are illustrated in Figure
13. The output of the VCO is then connected to two inverters in
order to convert the sinusoidal output into a square wave
output.
Figure 12: Transmission gate controlled VCO.
C. Voltage controlled oscillator
The voltage controlled oscillator (VCO) chosen for this
design is a transmission gate controlled ring oscillator, as
shown in Figure 12. The transmission gate controlled oscillator
is designed to oscillate between 1KHz and 15MHz. This makes
it suitable for lower frequencies such as 6.78MHz [8]. In this
technology, it is difficult for a varactor controlled ring oscillator
to operate at a frequency this low. The oscillation frequency of
a ring oscillator is
1
(6)
,
2
where N is the number of delay stages and tD is the delay per
stage. tD is proportional to
(7)
,
where R is the sum of the transmission gate and the inverter
resistance and CL is the load capacitance. From (6) and (7), the
oscillation frequency can be controlled by varying the
resistance of the transmission gate [8].
Generally, this ring oscillator has two differential control
inputs: Vctrl and VDD-Vctrl. In order to avoid the additional
Table 2: W/L RATIOS OF THE TRANSISTORS WITHIN THE VCO
M2
M3
M1
W/L [µm/µm]
0.6/5.0
4.0/2.5
0.6/2.5
6
15
FREQUENCY (MHz)
Figure 11: Charge Pump and low pass filter.
x 10
VCO FREQUENCY VERSUS VCTRL
10
X: 0.925
Y: 6.73e+006
5
0
0
0.5
1
VCTRL (V)
1.5
2
Figure 13: Voltage-frequency characteristics of the VCO.
V. SIMULATION RESULTS
Simulation is completed in Cadence Spectre [5] with the
following parameter values: R1 = 2KΩ, C1 = 800pF, C2 = 50pF,
ICP = 120µA, KVCO = 8.5MHz/V. Figure 14 depicts the
variation of the VCO control voltage (Vctrl) as the PLL reaches
the locked condition. According to this figure, when the PLL is
locked, Vctrl is nearly constant. The ripple on the control
voltage when the PLL is locked is 670µV which is equal to
only 0.07% of the Vctrl. The UP and DOWN signals are mostly
equal to VDD during the lock condition, as shown in Figure 15.
At locked condition, the reference signal (VREF) and the VCO
output (VVCO) have the same frequency and are in phase. The
overall power consumption is 492µW.
VCO CONTROL VOLTAGE
1.2
1.1
VCTRL (V)
1
0.9
VII. CONCLUSION
This paper has presented a low-power PLL implemented in
0.35µm CMOS technology for an implantable biomedical
device. The PLL is used to generate a stable clock signal at
each mode of the receiver including the off keying intervals of
the PAM scheme. The key design objectives are size, power
consumption, and the signal acquisition ability of the system.
This implementation of the PLL adequately addresses these
design concerns, with the entire circuit consuming
approximately 492µW of power, and is able to lock to an
external 6.78MHz clock within a reasonable amount of time.
The proposed low power, low area PLL has great potential in
implantable biomedical systems.
ACKNOWLEDGMENT
0.8
0.7
0.6
0.5
the addition of a frequency divider in the feedback loop. The
next step will be to complete the physical layout, and to verify
the operation of the post layout design.
0
5
10
TIME (µs)
15
20
Figure 14: Variation of Vctrl as the lock condition is achieved by the PLL.
The authors greatly appreciate the advice received by a panel
of mentors: Mr. Scott Abrams, CEO and President of Omnicon
Croup, Hauppauge, NY; Mr. Andrew Braverman, President and
CEO of Apptec Corp at Port Jefferson Station, NY; Ms. Yizhen
Chen, Motorola, Inc., Holtsville, NY; Dr. David Hernandez,
Access Systems – Honeywell, Shanghai, China; Mr. Steve
Rubin, Patent Attorney, Dilworth and Barrese, LLP, Melville,
NY; Ms. Yu Sun, Motorola, Inc., Holtsville, NY; Prof. Gerrit
Wolf, College of Business at SBU; and Ms. Jade Zhang,
Motorola, Inc., Holtsville, NY.
The mentoring panel is supported by the National Science
Foundation under Grant No. CNS 0829656 and IIP 0917956.
Any opinions, findings and conclusions or recommendations
expressed in this article are those of the authors and do not
necessarily reflect the views of the National Science
Foundation.
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[1]
[2]
[3]
Figure 15: Vctrl, UP, DOWN, Vvco, and VREF signals when the PLL is
in the locked condition.
[4]
[5]
[6]
VI. DISCUSSION AND FUTURE WORK
[7]
Future work includes jitter calculations. We will also
investigate techniques to increase KVCO while reducing ICP to
further reduce power dissipation. This modification will require
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