PhD defence by Ghanshyamsinh Vijaysinh Gohil on Modulation and

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PhD Public Defence
Title:
Modulation and Circulating Current Suppression for Parallel Interleaved
Voltage Source Converters
Location:
Pontoppidanstræde 111 in the auditorium
Time:
Friday 1 April 2016 at 13.00
PhD defendant:
Ghanshyamsinh Vijaysinh Gohil
Supervisor:
Professor Remus Teodorescu
Moderator:
Associate Professor Dezso Sera
Opponents:
Professor Francesco Iannuzzo, Dept. of Energy Technology, Aalborg University
(Chairman)
Assistant Professor Maryam Saeedifard, Georgia Institute of Technology, USA
Professor Paolo Mattavelli, University of Padova, Vicenza, Italy
All are welcome. The defence will be in English.
After the defence there will be an informal reception
in Pontoppidanstræde 111 (coffee room).
Abstract:
The two-level Voltage Source Converters (VSCs) are often connected in parallel to increase the current
handling capability. In such systems, the multi-level voltage waveforms can be obtained by interleaving
the carrier signals of the parallel connected two-level VSCs. The multi-level voltage waveform facilitates
reduction in both the switching frequency and the size of the harmonic filter components. This leads to
the improvement in both the system efficiency and power density. However, when VSCs are connected in
parallel and share the same dc-link, the circulating current flows through the closed path due to the
control asymmetry and the impedance mismatch. When the carriers are interleaved, the pole voltages
(switched output voltage of the VSC leg) of the interleaved parallel legs are phase shifted and it creates
instantaneous potential difference across the closed path, formed due to the parallel connection. This
instantaneous potential difference further aggravates the circulating current, which results in increased
losses and unnecessary over-sizing of the components present in the circulating current path. Therefore,
the circulating current should be suppressed to realize the full potential of the carrier interleaving.
The formation of the circulating current path can be avoided by using the line frequency isolation
transformer. However, it increases the overall size of the system and should be avoided. The use of the
Common-Mode (CM) inductor in series with the line filter inductor for each of the VSCs is proposed in
literature. Another approach proposes the use of the Coupled Inductor (CI) to suppress the circulating
current by providing magnetic coupling between the parallel interleaved legs of the corresponding
phases. Although the interleaved carrier signals lead to the reduction in the value of the harmonic filter
components, additional filter components (CIs) are often required to suppress the circulating current. The
volume of these inductive components can be reduced by integrating both of these functionalities into a
single magnetic component. Different integrated inductor solutions are presented in this thesis with an
objective to reduce the overall size of the magnetic component, so that the power density can be further
improved or for the given filter size, the switching frequency can be further reduced. The advantages
achieved by the magnetic integration are highlighted by comparing the volume and losses with that of the
separate inductor case.
The modulation scheme has significant impact on the core losses in the CI, the harmonic performance,
and the switching losses. These performance parameters for the conventional Pulse Width Modulation
(PWM) schemes are evaluated and compared. The PWM schemes for the size reduction of the CM and
core losses reduction in the CI is also proposed. For the multi-level converter, the Phase Disposition (PD)
PWM scheme results in optimal harmonic performance. However it cannot be applied to the parallel
VSCs in its original form as it may lead to the saturation of the CI. A modified PD modulator is proposed,
which ensures flux balancing in the CI, while ensuring the use of the nearest three vectors to synthesize
the reference space voltage vector in each sampling interval.
A 3.3 kV medium voltage converter using the two-level VSCs, configured in open-end transformer
topology has been studied. An integrated inductor for this topology is also proposed. The multi-objective
design optimization has been performed, where the energy loss and the volume are optimized. A noninferior (Pareto optimal) solution is obtained. The optimization process takes into account the yearly load
profile and it is used to minimize the energy loss, rather than minimizing the losses at a specific operating
point.
In a dual converter fed open-end transformer topology, each of the VSCs has to process the rated
current. In many high power applications, single two-level VSC may not be able to handle the rated
current. To overcome this problem, parallel connection of the two-level VSCs for the open-end
transformer topology is proposed. Using this topology, both the voltage and the current handling
capability of the converter can be increased. The carrier signals of the parallel VSCs are interleaved to
improve the harmonic performance. The integrated inductor for suppressing the circulating current
between the parallel VSCs and for improving the line current quality is also proposed.
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