This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
1
Development of Low-Cost 24-GHz Circuits
Exploiting System-in-Package (SiP) Approach
and Commercial PCB Technology
Federico Alimenti, Senior Member, IEEE, Paolo Mezzanotte, Gabriele Tasselli, Andrea Battistini,
Valeria Palazzari, and Luca Roselli, Senior Member, IEEE
Abstract— This paper deals with 24-GHz circuits developed
by exploiting a system-in-package approach. In order to reduce
the cost as much as possible, a standard multilayer printed
circuit board (PCB) technology has been adopted. Such a circuit
consists of a package built utilizing a 0.3-mm thick fiber-glass
substrate with 3.38 relative permittivity. The contacts between
the substrate and the mother board are realized along the
package perimeter exploiting 0.6-mm via-hole metalization
and half halo shield soldering pad. First, the developed
package is simulated and optimized by means of commercial
electromagnetic software. Then a prototype is fabricated and
measured. The obtained results show that the whole frequency
band from DC to 30 GHz can be covered. A packaged 26.5-mm
straight microstrip line exhibits an |S11 | value better than
−12 dB and an |S21 | value of about −1.4 dB at 24 GHz. This
value is only 0.6-dB worse than that of the unpackaged line. A
single-balanced diode mixer and a low-noise amplifier (LNA) for
industrial, scientific, and medical applications are then designed.
The integration of these building blocks within the PCB
package is finally demonstrated and experimentally verified. The
packaged mixer shows a 6.8-dB conversion loss. The packaged
LNA, instead, features a 9.1-dB gain with a 3.4-dB noise figure.
Index Terms— Microwave low-noise amplifiers, microwave
mixers, system-in-package.
I. I NTRODUCTION
T
HE availability of low-cost electronics will be the key
to the success of future microwave and millimeter-wave
applications, such as high data rate communication links,
radars for intelligent lighting systems, and passive imaging.
In this context, the electronic circuit packaging plays a central
role in terms of performance and cost [1]. The system-inpackage (SiP) approach offers an additional advantage because
multiple integrated circuits, passives, interconnects, and antennas can be integrated into a single functional package [2]. In
Manuscript received June 9, 2011; revised November 3, 2011; accepted
January 4, 2012. This work was supported in part by the Energy Efficient
and Intelligent Lighting Systems (EnLight) ENIAC European Project and
the COST Action IC0803 RF/Microwave Communication Subsystems for
Emerging Wireless Technologies (RFCSET). Recommended for publication
by Associate Editor P. Franzon upon evaluation of reviewers’ comments.
F. Alimenti, P. Mezzanotte, A. Battistini, V. Palazzari, and
L. Roselli are with Dipartimento d’Ingegneria Elettronica e
dell’Informazione, University of Perugia, Perugia 06125, Italy (e-mail:
alimenti@diei.unipg.it; mezzanotte@diei.unipg.it; andrea.battistini@artgroupsrl.it; valeria.palazzari@diei.unipg.it; roselli@diei.unipg.it).
G. Tasselli is with Institut de Microtechnique, École Polytechnique Fèdérale de Lausanne, Neuchâtel CH-2000, Switzerland (e-mail:
gabriele.tasselli@epfl.ch).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2012.2184111
order to make the SiP approach effective, however, designers
should be able to easily access package manufacturing services
for the fabrication of their custom layouts.
In the last few years, considerable efforts have been made
to improve the performances of microwave packaging while
reducing cost and making assembly easy. The multilayer
printed circuit board (PCB) technology was proposed by
several authors [3], [4] and it is already in production for
devices up to 5 GHz [5]. With such a technology, the PCB
dielectric substrate is exploited as the mechanical carrier, while
metal tracks are used to contact the internal circuit. The leads
can be absent or present. In the first case, a ball grid array
(BGA) approach is generally used to mount the package on
the mother board. In the second case, the leads are placed
on the package perimeter and are implemented by a proper
cutting (precision sawing) of metalized via holes. In [6], a
package fabricated with fiber-glass dielectric substrates has
been demonstrated up to 22 GHz. Such a package is leadless
and adopts a BGA mounting procedure. Similar solutions have
already been adopted in commercial products such as those
described in [7] and [8], but none of them uses the PCB
substrate to integrate RF building blocks (these are usually
implemented in Si or GaAs chips).
In this paper, we propose an extension of [6] in such a way
as to reduce costs and simplify the assembly procedure. To this
purpose, we adopt a number of peripheral leads fabricated by
cutting 0.6-mm via holes. Since the required level of accuracy
is nowadays a standard for PCB manufacturers, the proposed
approach is readily applicable to the development of SiP cells.
Following this line, two SiP building blocks for the 24-GHz
frequency band, namely a single balanced diode mixer and a
low-noise amplifier (LNA), were designed and tested. To the
authors’ knowledge these are the first SiP circuits exploiting
half-via up to 24 GHz.
This paper is organized as follows. First in Section II, the
method used to design the low-cost PCB package is described.
Both numerical simulations and experimental results are
shown, and the resonance problem is addressed. In Section III,
an equivalent circuit model of the package parasitic is proposed and validated. Finally, Section IV is devoted to the
design and testing of the SiP building blocks.
II. PACKAGE D ESIGN
The substrate chosen for the realization of the proposed
package is RO4003, a glass-reinforced hydrocarbon–ceramic
2156–3950/$31.00 © 2012 IEEE
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
(a)
(a)
(b)
(b)
Fig. 2. Amplitude of the E-field in the cavity formed by the package and
top mother board ground planes. (a) In the structure without half-halo shield
the package is grounded by means the peripheral leads only. As a result,
resonances may occur in the ground cavity. In this case, the coupling is due
to the vertical half via crossing the ground cavity itself. (b) In the structure
with half-halo shield, instead, resonances are no longer present. Both the
E-field plots were obtained at the frequency of 24 GHz.
(c)
Fig. 1.
(a) Proposed package in standard PCB technology mounted on
the mother board. (b) Mother board ground pad. (c) Transition detail. The
mechanical dimensions are as follows: package length l p = 26.5 mm, package
width w p = 15 mm, via hole diameter 2 r V = 0.6 mm, microstrip width
wm = 0.7 mm, and substrate thickness h = 305 μm.
laminate designed to offer superior high frequency performance and low-cost circuit fabrication. This is a low-loss
material that can be processed in the same way as FR4, i.e.,
exploiting the same production line. From the manufacturing
point of view, the main advantage of fiber-glass materials is the
high quality of the drilled holes and superior yield in realizing
multilayer structures.
The substrate parameters are as follows: thickness
h = 305 μm, metal thickness t = 17 μm, and relative
permittivity r = 3.38, as specified in the material data sheet
[9]. At the operating frequency, it is assumed tan δ = 0.008,
as in [10, p. 1410]. The metal roughness is about 3 μm,
see [11, p. 1779]. The metal conductivity is that of copper
and equal to σ = 5.8 × 107 S/m.
A. Structure Description
The proposed package is illustrated in Fig. 1 and consists of
a small rectangle of single-layer RO4003. This substrate has a
metal ground plane at the bottom and allows a microstrip-like
interconnection on the top. As an example, Fig. 1 shows a
through connection [50- uniform microstrip line (MLIN)]
between input and output ports, i.e., without any circuit
mounted or fabricated on the package itself.
The package ground is connected to the mother board
ground by means of a number of peripheral leads (34 in
the example of Fig. 1) soldered to a large ground pad (the
same size as the PCB package) available on the mother board
top layer. Such a ground pad is connected by several via
holes to the mother board ground plane (bottom face of the
mother board itself). As apparent from the figure, the leads
are fabricated by cutting miniaturized 0.6-mm via holes. The
same trick (half via hole) has also been exploited to realize
the electrical contact between the mother board feeding lines
and the signal ports of the packaged circuit.
The via hole diameter is derived from a tradeoff between
electrical and assembly requirements: large via holes with
large pads helps the assembly process but increases the interconnection parasitic capacitance (pad capacitance to ground).
On the other hand, small via holes make the fabrication and
assembly process critical (lower yield, alignment issues, etc.,)
while increasing the interconnection series inductance.
The pitch of the peripheral leads is another important
parameter. In general, this pitch should be decreased as the frequency increases. To clarify this concept, one can observe that,
when the signal line enters the package, two lateral ground
via holes are always present. A larger pitch between these
leads implies a longer ground return path, and thus higher
transition parasitics (grounding inductance). In this paper, a
pitch p = 1.6 mm has been used. This value is less than a
quarter wavelength in the adopted substrate (about 1.9 mm).
The cover of the proposed package can be realized by
exploiting a dielectric material, as shown in [6].
B. Design Method
The structure in Fig. 1 was designed using CST Microwave
Studio. The first design step was the simulation of a through
connection based on a 50- line implemented on the package
(i.e., the structure of Fig. 1). The mother board and the package
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ALIMENTI et al.: DEVELOPMENT OF LOW-COST 24-GHz CIRCUITS EXPLOITING SiP APPROACH
3
0
S21 (dB)
-2
-4
-6
-8
simulation
experiment
(a)
-10
14 16 18 20 22 24 26 28 30
frequency (GHz)
(a)
0
S21 (dB)
-2
-4
(b)
-6
-8
Fig. 4.
(a) 3-D view of the half halo-shield enclosure.
(b) Photograph of the bottom soldering pad on the PCB package ground
plane. The half-halo shield is realized by simply removing the solder resist
from the PCB package ground plane. During mounting, the ground cavity is
closed by the solder alloy flowing through the half halo path. In this way,
the ground cavity cannot be excited and resonances are avoided.
simulation
experiment
-10
14 16 18 20 22 24 26 28 30
frequency (GHz)
(b)
Fig. 3.
Simulated (full-wave) and measured |S21 | of the packaged
26.5-mm MLIN. (a) Structure is grounded by means of peripheral leads
only and the half halo shield is not present. As a result, the ground cavity
resonances are responsible of the various absorption deeps shown in the S21
response. (b) Half halo shield is used to avoid the ground cavity coupling.
The resonances completely disappear from the S21 response.
were grounded only by the peripheral package leads (half via
holes). In order to account for the soldering process (soldering
of the ground leads to the mother board ground pads), a gap of
g = 50 μm was considered in the model. This gap is localized
between the package bottom face (i.e., package ground plane)
and the mother board top face (i.e., mother board top ground
plane). The two ground planes were covered by a 17-μm
solder-resist layer with r = 4, and tan δ = 0.01.
The simulated E-field inside the ground cavity is shown in
Fig. 2(a), which shows evidence for the presence of a strongly
resonant behavior. Such a ground cavity is formed by the
package ground plane and by the top mother board ground
pad. These two planes are separated by the gap g. Laterally,
the ground cavity is closed by the soldered peripheral leads.
The electromagnetic field is coupled to this cavity by means of
the vertical half via (feeding via hole) connecting the mother
board and the package signal lines.
The corresponding |S21 | is illustrated in Fig. 3(a). This result
can be explained considering that a small portion of the input
signal can reach the output port being guided by the ground
cavity. As a consequence, when destructive interference takes
place, the deeps of the S21 response are obtained.
To validate the numerical full-wave model, a first package
prototype was realized and mounted on the mother board. The
experimental characterization was carried out with a 3680-K
Wiltron test fixture exploiting a custom-made thru-reflect-line
(TRL) calibration kit. The adopted TRL standards were fabricated on the same RO4003 substrate of the package. These
standards are two MLINs of different lengths and a microstrip
open at each port (acting as reflection standard). The full-wave
simulations do not account for the test fixture transitions, and
therefore were compared with de-embedded measurements.
All the experiments were carried out with both Agilent and
Anritsu 40-GHz vector network analyzers (VNAs), obtaining
results well within the instrumental accuracy. The measured
S21 is reported again in Fig. 3(a) and confirms the existence
of the simulated resonances.
The second design step is the optimization of the ground
connection in order to avoid parasitic resonances. Since these
resonances are due to the ground cavity, the main idea is to
prevent their excitation. At this point, it is interesting to note
that an optimization of the soldering process can only reduce
the gap g, but not completely remove it. As a result, the ground
cavity will be always present.
The excitation of the ground cavity was avoided by means
of a small soldering pad shaped as a half halo, as shown
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
lp
CB
RV
CP
w50
MLIN
RV
CP
full-wave model
equivalent circuit
LV
CB
LG
-1
S21 (dB)
LV
0
-2
Fig. 5. Equivalent circuit model ofthe PCB package. The extracted circuit
parameters are as follows: C B = 60 fF, C P = 35 fF, L V = 0.15 nH, R V =
1.5 , and L G = 5 pH. The width of each MLIN is equal to w50 = 0.67
mm. The length of the packaged line is l p = 26.5 mm.
-3
III. PACKAGE E QUIVALENT C IRCUIT
In the microwave and millimeter-wave frequency range, the
package parasitics have a significant impact on the circuit
performance. This impact can be evaluated after the circuit is
designed as a stand-alone one, or, better, the package parasitics
can be accounted for during the circuit design phase. In both
cases, a package equivalent circuit is needed.
A suitable equivalent circuit is reported in [3], which has
been adopted here with only a very small modification. Fig. 5
shows the modified equivalent circuit. Such a circuit describes
a generic mother board to package transition by means of a π
network. The capacitor C B represents the fringing E-field associated with the mother board MLIN end (soldering pad capacitance). C B also accounts for the stray capacitance between the
MLIN end and the halo structure. The inductor L V and the
resistor RV are the parasitics associated with the vertical via
connection. The capacitor C P is related to the fringing E-field
due to the in-package MLIN end (and to the small pad needed
for the half via fabrication). Finally, the inductor L G models
the package to the mother board ground connection.
The parameters of Fig. 5 have been determined by an optimization procedure in which the equivalent circuit parameters
were varied in such a way as to fit the full-wave model.
The results of this procedure are the following: C B = 60 fF,
14 16 18 20 22 24 26 28 30
frequency (GHz)
(a)
0
full-wave model
equivalent circuit
-10
S11 (dB)
in Fig. 4. Such a half halo was then placed around the
signal lead (half via). During the mounting process, this halfhalo pad was completely soldered to the large ground pad
available on the top mother board face. In this way, the
(spurious) excitation inputs of the ground cavity are shortcircuited and no electromagnetic field is coupled to the cavity.
This solution was preferred to the complete soldering of the
whole ground plane because of its easy assembly, reduction of
soldering paste, and lower thermal stress during mounting. In
particular, avoiding overheating during the assembly is the key
to reducing risks of both electrical and mechanical damages.
The effectiveness of half halo shield is anticipated by
Fig. 2(b), showing no E-field in the ground cavity, while the
analysis reported in Fig. 3(b) demonstrates that the resonances
are no longer present in the S21 response. This result is also
confirmed by the measurements of a package structure with
the half halo shield. At 24 GHz, the packaged 26.5-mm MLIN
features an insertion loss of about 1.4 dB, which is only 0.6 dB
more with respect to the unpackaged line.
-20
-30
-40
14 16 18 20 22 24 26 28 30
frequency (GHz)
(b)
Fig. 6. Comparison between the full-wave model and the extracted equivalent
circuit. (a) |S21 |. (b) |S11 |. The equivalent circuit includes all the previously
discussed transition parasitics.
C P = 35 fF, L V = 0.15 nH, RV = 1.5 , and L G = 5 pH.
These values are quite low since several vias have been used in
the package to mother board ground connection, as shown in
Fig. 1(b). The scattering parameters of the extracted equivalent
circuit are reported in Fig. 6, which shows the good agreement
between the equivalent circuit and full-wave simulations.
IV. PACKAGED B UILDING B LOCKS
To prove the validity of the described package design
approach, two typical microwave building blocks, namely a
down-conversion mixer and an LNA were developed. The
operation frequency has been selected equal to 24 GHz, i.e.,
within the industrial, scientific, and medical (ISM) frequency
range. Thanks to the PCB package approach, these two building blocks are reusable intellectual property (IP) cells similar
to that proposed, at lower frequency, in [2].
A. 24-GHz Diode Mixer
The mixer circuit was implemented on the same dielectric
substrate as the package. To this purpose, the packaged device
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ALIMENTI et al.: DEVELOPMENT OF LOW-COST 24-GHz CIRCUITS EXPLOITING SiP APPROACH
D1
G
5
TABLE I
R AT-R ACE D IMENSIONS
IF
Parameter
RF
D2
Symbol
Value
Rat-race hybrid length
lR
6 λ/4
–
Rat-race hybrid diameter
dR
4.20
mm
50- microstrip width
w50
0.67
mm
70- microstrip width
w70
0.34
mm
LO
TABLE II
(a)
MA4E2502L SPICE PARAMETERS
Parameter
(b)
Fig. 7. 24-GHz single-balanced planar mixer. (a) Schematic. (b) Packaged
prototype. The diodes and the related shorting stubs are placed inside the ratrace. A 0- resistor is used to pick up the IF node while bridging the ring.
was simply obtained by adding signal and ground leads to the
unpackaged mixer.
The proposed circuit is for low- or zero-IF applications,
such as Doppler radar receivers [12] or microwave radiometric
sensors. The mixer schematic and the fabricated prototype are
illustrated in Fig. 7, whereas the main geometrical dimensions
are quoted in Table I. The mixer is based on a well-known
single-balanced configuration, realized around a 180° rat-race
microstrip hybrid. Such a topology is chosen since it offers a
good compromise between RF/LO isolation (provided by the
hybrid), conversion loss (approaching that of a single diode
mixer), and implementation simplicity (single metal layer).
The main design innovation is that, in order to save PCB
area, the two diodes (D1 and D2 in Fig. 7) and their RF
shorting (radial) stubs are placed within the rat-race ring.
A quarter-wavelength short-circuited stub (G in Fig. 7) is
then used to provide a DC return for the diodes. Another
innovation is the following: the IF signal is picked up by a 0-
resistor crossing the hybrid; a device with standard 0603 size
is used for this purpose in order to reduce cost and making
the assembly possible with standard pick-and-place machines.
Two SURMOUNT low-barrier silicon Schottky diodes [13]
have been used in the design. This technology, featuring
very low package parasitics, is characterized by device electrical performances as high as for beam-lead diodes while
being compatible with automated assembly process. The
main parameters of the diode’s SPICE model are reported
in Table II.
A classical design methodology was adopted. First the
180° hybrid was synthesized in microstrip technology, based
on a 50- port impedance. As a consequence, the rat-race
Unit
Saturation current
Emission coefficient
Parasitic series resistance
Energy gap
Parasitic junction capacitance
Junction capacitance
Junction potential
Grading coefficient
Forward bias cap. coefficient
High injection knee current
Reverse breakdown voltage
Current at rev. breakdown voltage
Parasitic series inductance
Symbol
Value
Unit
IS
n
RS
Eg
CJ P
CJ0
VJ
m
FC
IK
BV
I BV
LS
26
1.2
12.8
1.11
60
10
80
0.5
0.5
14
5.0
10
0.8
nA
–
eV
fF
fF
mV
–
–
mA
V
μA
nH
transmission line had a characteristic impedance equal to
70.7 . The presence of the 0- resistor, which was made of
alumina, altered the propagation characteristics of the rat-race
microstrip underneath. To account for this effect, the effective
permittivity of the line below the resistor was modified. In
particular, for a length equal to the width of the 0603 device
(i.e., w R = 0.8 mm), the dielectric constant of the substrate
has been set to R = 5.3. A detailed derivation of such a
model is described in the Appendix. The rat-race hybrid was
also realized and measured separately, in order to fine-tune the
design and to maximize the isolation.
Then a harmonic balance simulator was adopted to complete
the mixer design. Particular care was devoted to the SPICE
model of the Schottky diodes which, substantially, was that
reported in the device’s data sheet. Open stubs were used to
match both LO and RF ports. The IF termination impedance
was set to Z I F = 240 , which is a computer-optimized
value for the minimum conversion loss. The impact of the
PCB package was finally evaluated by considering the lumpedelement equivalent circuit illustrated in Fig. 5.
For the measurement of the mixer conversion loss, two RF
signal sources were used, as illustrated in Fig. 8. Both sources
have an input impedance of 50 and their available power can
be regulated by an internal step attenuator. To obtain accurate
results, the available power of the sources was characterized
by a spectrum analyzer. In this characterization, the connection
cables were also considered.
Since the mixer performance was optimized for an IF
impedance of 240 , the delivered IF power must be measured
satisfying such a termination condition. In order to match the
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
Z0
ZIF
30
R2
spectrum
Z0 analyser
LO
source
Fig. 8. Test setup used to experimentally characterize the packaged mixer.
In order to match the spectrum analyzer input impedance (Z 0 = 50 ) to
the optimum IF impedance (Z I F = 240 ), a resistive pad has been used.
The resistance values are: R1 = 560 , R2 = 390 , and R3 = 56 . The
overall IF attenuation is A I F = 17.2 dB. This value has been accounted for
in the evaluation of the conversion loss.
spectrum analyzer input impedance (equal to 50 ) to the IF
impedance of the mixer (equal to 240 ), an asymmetrical
attenuator was used for test purpose only. The attenuator is
composed by a π-network of resistors with the following
values: R1 = 560 , R2 = 390 , and R3 = 56 . The
overall attenuation can be easily computed from the above
resistances and is equal to A I F = 17.2 dB. All the attenuator
resistances have a 1% tolerance with respect to their nominal
values. As a result, the IF power is obtained by increasing the
value measured with the spectrum analyzer by A I F .
The measured conversion loss of the packaged mixer is
reported in Fig. 9(a). In this experiment, the available LO
power is swept between −10 and +10 dBm, while the RF
power is kept at PR F = −30 dBm. The insertion loss of the
test fixture (Wiltron 3680 K) and of the feeding MLINs on the
mother board were evaluated to be about 1 dB for both RF and
LO ports.1 Such a value was used to correct the conversion loss
data. The signal frequencies are set as follows: f R F = 24.06
GHz, f L O = 23.96 GHz, and f I F = 100 MHz. A minimum
conversion loss of 6.8 dB was achieved for PL O = 3.5 dBm,
and the result is in good agreement with harmonic-balance
simulations. The conversion loss compares also well with other
published designs [14]–[16]. These works, however, refer to
unpackaged designs.
Fig. 9(b) shows the conversion loss of the mixer versus the
RF frequency. The available LO power was kept at PL O =
3.5 dBm, i.e., the optimum value determined by the analysis
of Fig. 9(a). In this experiment, the RF frequency was varied
between 23 and 25 GHz, while f L O = 24.06 GHz (i.e., the
IF frequency was different at each measurement point). From
Fig. 9(b), it emerges that the mixer is well centered around
24 GHz and features a bandwidth of about ±300 MHz with
only 0.4-dB degradation of the conversion loss (i.e., 7.2 dB
instead of 6.8 dB).
The linearity of the mixer was characterized by means of a
single tone test. The LO signal was kept at PL O = 3.5 dBm
and f L O = 24.06 GHz. The RF frequency was equal to
1 Let us consider the mother board used in the mixer experiment. The
distance between each coaxial-to-microstrip transition and either the RF and
the LO package leads is equal to 15 mm. By measuring a 30-mm MLIN with
the Wiltron 3680 K test fixture, an overall insertion loss of about 2 dB is
obtained. Such a loss is divided in two 1-dB contributions attributed to the
RF and LO ports (scalar de-embedding).
25
conversion loss (dB)
RF
source
R3
simulation
experiment
20
15
10
5
0
-10
-5
0
5
LO available power (dBm)
10
(a)
12
11
conversion loss (dB)
R1
simulation
experiment
10
9
8
7
6
23
23.5
24
24.5
25
RF frequency (GHz)
(b)
Fig. 9.
Conversion loss of the packaged mixer: comparison between
simulation and measurements. (a) Available LO power is swept between −10
to +10 dBm. During the experiment, f RF = 24.06 GHz, f L O = 23.96 GHz,
f I F = 100 MHz, and PRF = −30 dBm. (b) Available LO power is
kept at PL O = 3.5 dBm (i.e., the optimum value) and the RF frequency
is varied between 23 and 25 GHz. The frequency response is obtained for
PRF = −30 dBm and f L O = 24.06 GHz (i.e., the IF frequency is different
at each measurement point).
f R F = 23.96 GHz, while the RF available power was swept
between −20 to 10 dBm. The results are illustrated in Fig. 10,
showing again good agreement between experiment and ADS
simulations. The input-referred 1-dB compression point of the
mixer is P1 d B = 1 dBm.
Finally, the LO to RF isolation of the mixer was experimentally characterized. To this purpose, the signal generator
was connected to the LO port, while the spectrum analyzer
was used to measure the delivered power at the RF port.
The experiment was carried out with PL O = 3.5 dBm
and varying f L O from 23 to 25 GHz. The results are
reported in Fig. 11(b) showing an isolation always better
than 30 dB.
Fig. 11(b) also shows the data obtained with the harmonicbalance simulator in three different cases. Model 1 refers to
the ideally symmetric mixer. The microstrip rat-race (loaded
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ALIMENTI et al.: DEVELOPMENT OF LOW-COST 24-GHz CIRCUITS EXPLOITING SiP APPROACH
0
7
VGS
VDS
IF power (dBm)
-5
-10
INP
-15
OUT
GND
-20
(a)
simulation
experiment
-25
-30
-20
-15 -10
-5
0
5
RF available power (dBm)
10
Fig. 10. IF power versus available RF power: comparison between simulation
and measurements. In this experiment, PL O = 3.5 dBm, f L O = 24.06 GHz,
and f RF = 23.96 GHz. The input-referred 1-dB compression point of the
mixer is equal to about 1 dBm.
(b)
Fig. 12.
24-GHz LNA circuit. (a) Schematic. (b) Packaged prototype.
The amplifier is based on the NE350184C device, an N-channel heterojunction FET from CEL. The mechanical dimensions of the PCB package are
25 × 15 mm2 including the printed DC blocks.
D1
D2
LO to RF isolation. Both model 1 and model 2 disagreed
with the measured values. However, a mounting asymmetry
was noticed at the diode level by observing the mixer with a
microscope. In particular, D1 appeared to be lifted by about
50 μm with respect to the substrate plane. To describe this
effect, a parasitic capacitance Cm = 25 fF was connected
from the D2 cathode to ground, as depicted in Fig. 11(a).
The obtained simulation results in this case (model 3) are in
satisfactory agreement with the experiment.
Cm
(a)
60
LO/RF isolation (dB)
model - 1
model - 2
model - 3
experiment
50
B. 24-GHz LNA
40
30
20
23
23.5
24
24.5
LO frequency (GHz)
25
(b)
Fig. 11. LO to RF isolation of the packaged mixer: comparison between
simulation and measurements. (a) Equivalent circuit. (b) Results. Model 1
is the perfectly balanced mixer. In model 2, the effect of the 0- bridge is
accounted for. In model 3, a capacitor Cm = 25 fF is connected from the D2
cathode to ground (see the equivalent circuit). This capacitance accounts for
the observed diode mounting tolerances.
with the diodes) is centered at about 23.5 GHz, and at this
frequency the higher isolation is obtained. In model 2, the
IF bridge (realized with the 0-Omega resistor) is considered.
Such a device alters the rat-race symmetry, thus reducing the
The designed LNA is illustrated in Fig. 12 and is based
on an N-channel heterojunction field effect transistor (FET)
LNA from California Eastern Laboratories (CEL) named
NE350184C [17]. This device was chosen since it offers a
good gain (11 dB at 24 GHz) and a low noise figure (1.0 dB
at 24 GHz). Moreover, it adopts a Micro-X ceramic package
featuring very low parasitics while being compatible with a
pick-and-place automated assembly process.
The amplifier was designed pursuing the maximum gain.
An open stub was used to match the output port, whereas
a λ/4 impedance transformer was used for input matching.
Both input and output were a.c. coupled by means of quarterwavelength microstrip couplers optimized for the 24-GHz
center frequency. In the simulations, the effect of the PCB
package was evaluated by considering the lumped-element
equivalent circuit illustrated in Fig. 5.
The measurements were carried out by mounting the
packaged LNA on the mother board and contacting the latter
by means of a Wiltron 3680-K test fixture. The scattering
parameters were measured with an Agilent N5230A VNA.
The coaxial-to-microstrip transitions and the mother board
feeding lines were de-embedded with a TRL calibration kit.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
8
15
simulation
noise figure (dB)
simulation
experiment
S21 (dB)
10
5
experiment
6
4
2
0
0
20
22
24
frequency (GHz)
20
26
(a)
26
Fig. 14. Noise figure of the packaged LNA: comparison between simulation
and measurements. Biasing values: V DS = 3 V and I DS = 10 mA. The
measured noise figure is about 3.4 dB at 23.3 GHz.
0
-10
S11 (dB)
22
24
frequency (GHz)
0
0603
resistor
lR
-20
hR
-30
Al2O3
simulation
air
experiment
tR
t
-40
20
22
24
frequency (GHz)
26
(b)
w70
h
RO4003
Fig. 13. (a) |S21 | and (b) |S11 | of the packaged LNA: comparison between
simulation and measurements. Biasing values: V DS = 3 V and I DS = 10 mA.
The measured gain is about 9.1 dB at 23.3 GHz.
The latter was purposely designed to cover the 13–26-GHz
frequency range.
The LNA was biased with a drain current of 10 mA, a
drain–source voltage of 3 V, and a gate–source voltage of
about −0.3 V. Under these conditions, it showed an |S21 | equal
to 9.1 dB at 23.3 GHz, as illustrated in Fig. 13(a). This value is
1.2-dB worse than the small-signal simulations. The measured
−3-dB LNA bandwidth is about 2.8 GHz. The value of |S11 |,
instead, is −25 dB at 24 GHz, as reported in Fig. 13(b).
The noise figure measurements were carried out with an
Agilent N9020A MXA signal analyzer with an internal preamplifier up to 26.5 GHz. The noise figure of this instrument
(with the preamplifier) is about 15 dB as reported in [18, p. 9].
The Agilent N4002A noise source was used along with an
Y-factor methodology. This noise source has a nominal ENR
of about 14 dB. The losses due to the coaxial-to-microstrip
transition (Wiltron 3680-K test fixture) and to the input feeding
line (mother board microstrip) were estimated to be around
0.4 dB. This value was considered in order to correct the
measured noise figure data.
The experimental results are reported in Fig. 14, together
Fig. 15. Cross-section of the mixer PCB, showing the IF port bridging.
Such a bridge is realized by using a 0603 0- resistor. The main mechanical
dimensions are h = 305 μm, t = 17 μm, h R = 360 μm, t R = 10 μm,
l R = 1.6 mm, and w70 = 340 μm. The dielectric properties of the RO4003
substrate are r = 3.38 and tan δ = 0.008. The dielectric properties of the
alumina resistor body are: r = 9 and tan δ = 0.001.
with the corresponding simulations. As can be seen from
the figure, the packaged LNA shows a noise figure of about
3.4 dB at 23.3 GHz. This is 1.4-dB (i.e., 38%) away from
the simulations. The accuracy of the above measurements can
be estimated in about ± 1 dB, according to [19, p. 37]. This
value is mainly due to the low intrinsic gain of the considered
device under test.
V. C ONCLUSION
A standard multilayer PCB technology was used to produce
low-cost SiP circuits. Full-wave simulations and prototype
measurements show that, by a proper design, a PCB package
with half-via interconnection was able to cover the full frequency band from DC to 30 GHz. Two typical building blocks
for 24-GHz ISM applications, namely a planar mixer and a
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
ALIMENTI et al.: DEVELOPMENT OF LOW-COST 24-GHz CIRCUITS EXPLOITING SiP APPROACH
LNA, were successfully designed and tested. These circuits
represent a significant case of study of SiP integration.
The value of the obtained results was not in the concept
itself (half vias are well established) but in having demonstrated that a low-cost technology and material can be pushed
up to the millimeter-wave boundary. Since PCB services
are available to everybody, the above methodology will be
extremely useful for the implementation of reusable IP cells.
ACKNOWLEDGMENT
The authors would like to thank Agilent Technologies,
Santa Clara, CA, and Computer Simulation Technologies,
Darmstadt, DE, for the donation of the software licenses.
Thales Alenia Space, Rome, Italy, Microlease, Rome, and
ART, Passignano, Italy, are acknowledged for their support
during the experimental phase of this paper.
A PPENDIX
I MPACT OF THE 0- R ESISTOR
To model the presence of the 0- resistor, a transmission
line in a multilayered dielectric media has been considered.
The line cross-section is illustrated in Fig. 15. The length of
the resistor is l R = 1.6 mm, while its width (not shown in the
figure) is w R = 0.8 mm. The other relevant cross-section and
material parameters are given in the caption of Fig. 15.
An electromagnetic simulator (ADS Momentum) was used
to calculate the scattering parameters of a uniform transmission line, the length of which is equal to w R . These scattering
parameters were then compared to that of a single-layer MLIN
having a width equal to w70 , a length equal to w R , and suitable
dielectric constant. The dielectric constant was tuned in such
a way as to get the best fit between the two models (i.e.,
multilayer electromagnetic and single-layer circuital). As a
result, an equivalent relative permittivity R = 5.3 was found.
With such an R , the single-layer microstrip behaves like the
multilayer transmission line.
R EFERENCES
[1] I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, N. Kinayman, N. Jain,
R. Anderson, F. Kolak, R. Wohlert, S. Bawell, J. Bennett, and J.-P.
Lanteri, “Ultrawideband radar sensors for short-range vehicular applications,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp. 2105–2122,
Sep. 2004.
[2] N. Khandelwal and R. Jackson, “Active antenna module for low-cost
electronically scanned phased arrays,” IEEE Trans. Microw. Theory
Tech., vol. 56, no. 10, pp. 2286–2292, Oct. 2008.
[3] A.-V. Pham, A. Sutono, J. Laskar, V. Krishnamurthy, D. Lester, E. Balch,
and J. Rose, “Development of microwave multilayer plastic-based multichip modules,” IEEE Trans. Adv. Packag., vol. 24, no. 1, pp. 37–40,
Feb. 2001.
[4] R. Wormald, S. David, G. Panaghiston, and R. Jeffries, “A low cost packaging solution for microwave applications,” in Proc. 1st Eur. Microw.
Integr. Circuit Conf., Manchester, U.K., Sep. 2006, pp. 205–208.
[5] Universal Microwave Corporation. (2005). UMX-806-D16: Voltage Controlled Oscillator, Brooksville, FL [Online]. Available: http://www.vco1.
com/UMX.html
[6] K. Phan, K. Fujii, H. Morkner, and A. Rixon, “An integrated low noise
amplifier and image-rejection mixer in a surface mount package for low
cost 10–22 GHz applications,” in Proc. 1st Eur. Microw. Integr. Circuit
Conf., Manchester, U.K., Sep. 2006, pp. 122–125.
[7] Hittite Microwave Corporation. (2010). HMC463LH250: GaAs pHEMT
MMIC Low Noise AGC Amplifier, 2–20 GHz, Chelmsford, MA
[Online]. Available: http://www.hittite.com/products/view.html/view/
HMC463LH250
9
[8] Avago Technologies. (2008). AMMP-6532: 20–32 GHz GaAs MMIC
LNA/IRM Receiver in SMT Package, San Jose, CA [Online]. Available:
http://www.avagotech.com/docs/AV02-1022EN
[9] Rogers Corporation. (2007). RO4000 Series High Frequency Circuit Materials, Woodstock, CT [Online]. Available: http://www.
rogerscorporation.com
[10] D. Lohinetong, P. Minard, C. Nicolas, J. L. Bras, A. Louzir, J. Thévenard, J. Coupez, and C. Person, “Surface mounted millimeter waveguide
devices based on metallized dielectric foam or plastic materials,” in Proc.
IEEE Int. Microw. Symp., Long Beach, CA, Jun. 2005, pp. 1409–1412.
[11] J. Rautio, B. Rautio, S. Arvas, A. Horn, and J. Reynolds, “The effect of
dielectric anisotropy and metal surface roughness,” in Proc. IEEE Asia
Pacific Microw. Conf., Yokohama, Japan, Jun. 2010, pp. 1777–1780.
[12] F. Alimenti, F. Placentino, A. Battistini, G. Tasselli, W. Bernardini,
P. Mezzanotte, D. Rascio, V. Palazzari, S. Leone, A. Scarponi, N. Porzi,
M. Comez, and L. Roselli, “A low-cost 24 GHz doppler radar sensor
for traffic monitoring implemented in standard discrete-component technology,” in Proc. 4th Eur. Radar Conf., vol. 1. Munich, Germany, Oct.
2007, pp. 162–165.
[13] MA4E2502L - Low Barrier Silicon Schottky Diodes. MA/COM, Lowell,
MA [Online]. Available: http://www.macomtech.com
[14] Z. Li and K. Wu, “24-GHz frequency-modulation continuous-wave
radar front-end system-on-substrate,” IEEE Trans. Microw. Theory Tech.,
vol. 56, no. 2, pp. 278–285, Feb. 2008.
[15] L. Chiu, T. Y. Yum, Q. Xue, and C. H. Chan, “A low conversion-loss
ring hybrid mixer using TS-CMRC circuitry,” Microw. Opt. Technol.
Lett., vol. 41, no. 3, pp. 206–209, May 2003.
[16] Y.-L. Yang, J.-X. Chen, and Z.-H. Bao, “Broadband compact rat-race
hybrid and its application to mixers,” IET Microw. Antennas Propag.,
vol. 4, no. 12, pp. 2001–2007, Dec. 2010.
[17] California Eastern Laboratories (CEL). (2005). Hetero Junction Field
Effect Transistor NE350184C - K-Band Super Low Noise Amplifier,
Santa Clara [Online]. Available: http://www.cel.com
[18] Agilent Technologies. (2006). Agilent MXA Signal Analyzer N9020A
Data Sheet, Santa Clara, CA [Online]. Available: http://www.agilent.com
[19] Agilent Technologies. (2010). Noise Figure Measurement Accuracy The Y-Factor Method, Santa Clara, CA [Online]. Available: http://www.
agilent.com
Federico Alimenti (SM’09) was born in Foligno,
Italy, in 1968. He received the Laurea (magna cum
laude) and Ph.D. degrees from the University of
Perugia, Perugia, Italy, in 1993 and 1997, respectively, both in electronic engineering.
He held an internship at Daimler-Benz Aerospace,
Ulm, Germany, in 1993. Since 2001, he has been
with the Department of Electronic and Information
Engineering, University of Perugia, as a Research
Associate. In 2006, he was elected a member of
the Academic Senate in the same university. He has
authored more than 120 papers published in referred journals, conference
proceedings, and books chapters. His current research interests include the
design and characterization of microwave integrated circuits in complementary
metal-oxide-semiconductor and SiGe BiCMOS technologies.
Dr. Alimenti was a recipient of the URSI Young Scientist Award and was a
Visiting Scientist with the Technical University of Munich, Germany, in 1996.
Paolo Mezzanotte received the Ph.D. degree from
the University of Perugia, Perugia, Italy, in 1997.
He was involved with finite-difference timedomain analysis of microwave structures in cooperation with the Department of Electronic and Information Engineering, University of Perugia, from
1992. Since January 2007, he has been an Associate
Professor with the same university. His research
activities concern numerical methods, computeraided design techniques for passive microwave structures, and analysis and design of microwave and
millimeter-wave circuits. He has authored more than 100 papers published
in international journals and conference proceedings. His current research
interests include the study of advanced technologies such as low-temperature
co-fired ceramics and radio frequency microelectromechanical systems.
Dr. Mezzanotte serves as reviewer for several IEEE journals.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY
Gabriele Tasselli received the Degree in electronic
engineering from the University of Perugia, Perugia,
Italy, and the Ph.D. degree in information engineering from the same University in 2003 and 2011,
respectively.
He was an Research and Development Engineer
with WiS S.r.l., a spin-off company of the University of Perugia, where he contributed to the Lband telemetry for Formula-1 World Championship
and to other radio frequency applications such as
transceivers and radars from 2003 to 2008. From
2008 to 2011, he was a Senior Research and Development Engineer and a
Project Manager with ART S.r.l. Research Center, Passignano sul Trasimeno,
PG, Italy, where he was involved in the design of satellite telemetry. Currently,
he is a Scientific Collaborator with ESPLAB, IMT Neuchâtel, École Polytechnique Fèdérale de Lausanne, Neuchatel, Switzerland. His current research
interests include the design of radio frequency integrated circuits and RFbased sensors in complementary metal-oxide-semiconductor technologies.
Andrea Battistini was born in Terni, Italy, in 1981.
He received the Laurea degree (magna cum laude)
in electronic engineering from the Università degli
Studi di Perugia, Perugia, Italy, in 2006. He is
currently pursuing the Ph.D. degree with the Department of Electronic and Information Engineering,
Università degli Studi di Perugia.
He was an Research and Development Engineer
with ART S.r.l. (PG), Rome, Italy, in 1996. His
current research interests include analog design of
microwave sensors (both radiometers and radar) for
civil and space applications.
Valeria Palazzari received the Laurea degree in
electronic engineering and the Ph.D. degree in information and electronic engineering from the University of Perugia, Perugia, Italy, in 2000 and 2003,
respectively.
She has been with the High Frequency Electronics
Laboratory, Department of Electronic and Information Engineering, University of Perugia, since
2000. Since 2003, she has been with the ATHENA
Research Group, Georgia Institute of Technology,
Atlanta, where she is currently a Post-Doctoral
Assistant. Her current research interests include modeling, design, and realization of microwave integrated circuits in SiGe BiCMOS technology and
packaging technologies for radio frequency and wireless systems.
Luca Roselli (SM’01) was born in Florence, Italy,
in 1962. He received the Laurea degree in electronic
engineering from the University of Florence, Florence, Italy, in 1988.
He joined the Department of Electronic and Information Engineering, University of Perugia, Perugia,
Italy, as a Researcher Associate in 1992. In 2000,
he became an Associate Professor with the same
university. He founded the WiS S.r.l and the DiES
S.r.l, two University of Perugia spin-off companies.
Since 2008, he has been appointed the Director of
the Science and Technology Committee of the research center Pischiello,
Umbria, Italy, for the development of automotive ICT technologies. He
has authored more than 160 papers published in refereed journals and
conference proceedings. His current research interests include the design of
high-frequency electronic circuits, systems, and radio frequency identification
sensors.