Integrated Common and Differential
Mode Filters with Active Damping for
Active Front End Motor Drives
A Thesis
Submitted for the Degree of
Master of Science
in the Faculty of Engineering
By
Anirudh Acharya B
Department of Electrical Engineering
Indian Institute of Science
Bangalore - 560 012
India
January 2011
Acknowledgements
Any accomplishment in any walk of life is a collective effort - some contribute directly and
few indirectly. Hence I would like to mention a few who influenced, enthused, guided and
helped me to bring out this thesis.
At the outset, I would like to record my gratitude to my advisor Dr. Vinod John for
accepting me as a student of Power Electronics Group. His enthusiasm, guidance and concern
throughout my research have made my stay at IISc a memorable and cherishable moment
in my life. Apart from being a great teacher and a guide, his student centric approach with
grace and humility has been a great inspiration to me.
I owe my deepest gratitude to Dr. V. Ramanarayanan for sharing his wisdom inside and
outside the class room. His thought provoking ideas and simplistic approaches to complex
problems have influenced my research in a great way. I am grateful to (late) Dr. V.T.
Ranganathan for his lectures in Electric Drives and for his advice during my research. His
ideas, humble nature and simplicity have been a true inspiration. I am thankful to Dr. G.
Narayanan for his support and encouragement from initial to final level of my research. I
am grateful for all the guidance and concern he has showed towards me during my research.
I am thankful to Dr. G. K. Purushothama (MCE, Hassan), for his constant encouragement and advice to pursue higher studies.
I am indebted to all friends in Power Electronics Group for their support, stimulating
discussions and valuable inputs.
I am thankful to Mr. Ravi, Mr. Ramachandran and the other workshop staff for their
help in building my hardware and Mrs. Silvi Jose for the support extended in procuring
components. I also extend my thanks to Mr. D. M. Channe Gowda and his team at EE
offce for the smooth conduct of administrative activities.
I am thankful to my former colleagues of Mindtree for their encouragement and support
for pursuing higher studies.
This thesis would not have been possible without the continuous support of my family
for which I remain thankful. I am indebted to all who directly, indirectly helped me in this
accomplishment.
i
ii
Acknowledgements
Abstract
IGBT based power converters acts as front end in the present day Adjustable Speed Drive
(ASD). This offers many advantages and makes regenerative action possible. PWM rectifier
operation produces electrically noisy DC bus on common mode basis. This results in higher
ground current as compared to three phase diode bridge rectifier. Due to fast turn-ON and
turn-OFF time of IGBT, the inverter output voltage dv/dt is high during switching transients
and voltage waveform is rich in harmonics. As a result, in applications involving long cable
the motor terminal voltage during the switching transient is as high as twice the applied
voltage. This voltage stress reduces the life of insulation in motors. The high dv/dt output
voltage applied at the motor terminal excites the parasitic capacitive coupling resulting in
increased ground currents and causes Electric Discharge Machining (EDM) which reduces
the life of motor bearings. The common mode voltage due to PWM rectifier and the inverter
appear at the motor terminals exacerbating these problems.
The common mode voltage due to PWM inverter with AFE converter is analyzed. An
integrated approach for filter design is proposed wherein the adverse effects due to common
mode voltage of both AFE converter and the inverter is addressed. The proposed topology addresses the problems of common mode voltage, common mode current and voltage
doubling due to ASD. The design procedure for proposed filter topology is discussed with
experimental results that validate the effectiveness of the filter.
Inclusion of such higher order filter in the converter topology leads to problems such
as resonance. Passive methods are investigated for damping the line resonance due to LCL
filter and common mode resonance due to common mode filter. The need for active damping
technique for resonance due to common mode filter is presented. State space based damping
technique is proposed to effectively damp the resonance due to line filter and the common
mode filter. Experimental results are presented that validate the effectiveness of active
damping both on the line basis (differential mode) and line to ground basis (common mode)
of the filter.
iii
iv
Abstract
Contents
Acknowledgements
i
Abstract
iii
List of Tables
viii
List of Figures
ix
1 Introduction
1
1.1
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2
Voltage Doubling at Motor Terminal . . . . . . . . . . . . . . . . . . . . . .
3
1.3
Effect of High Frequency Common Mode Voltage on Motor . . . . . . . . . .
7
1.4
Common Mode Voltage due to Power Converter . . . . . . . . . . . . . . . .
8
1.5
Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
1.6
Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
1.6.1
Passive Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
1.6.1.1
Output Reactor . . . . . . . . . . . . . . . . . . . . . . . . .
13
1.6.1.2
Common Mode Filter . . . . . . . . . . . . . . . . . . . . .
13
1.6.1.3
Sine Filters . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
1.6.1.4
Clamp Filters . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Active Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Other Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.7.1
Increasing Insulation Grade . . . . . . . . . . . . . . . . . . . . . . .
17
1.7.2
Insulated Bearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.7.3
Grounding Shaft . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.7.4
Conductive Lubricant . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
1.7.5
Electro-statically Shielded Motor . . . . . . . . . . . . . . . . . . . .
18
1.7.6
ASD Carrier Setting and PWM Techniques . . . . . . . . . . . . . . .
18
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
1.6.2
1.7
1.8
v
vi
Contents
2 Filter Design
21
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2.2
High Frequency Behavior of Induction Motor . . . . . . . . . . . . . . . . . .
21
2.2.1
HF behavior of IM on Differential Mode . . . . . . . . . . . . . . . .
24
2.2.2
HF behavior of IM on Common Mode . . . . . . . . . . . . . . . . .
28
Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.3.1
Filter Design Objectives . . . . . . . . . . . . . . . . . . . . . . . . .
31
2.3.1.1
Design Objectives for Motor Filter . . . . . . . . . . . . . .
31
2.3.1.2
Design Objectives For Common Mode DC Bus Filter . . . .
32
Principle and Design of dv/dt Filter . . . . . . . . . . . . . . . . . . . . . . .
34
2.4.1
Working of dv/dt Filter
. . . . . . . . . . . . . . . . . . . . . . . . .
34
2.4.2
Design of dv/dt Filter . . . . . . . . . . . . . . . . . . . . . . . . . .
35
2.4.2.1
Design of Snubber Circuit . . . . . . . . . . . . . . . . . . .
41
2.5
Common Mode Circuit of AFE Converter . . . . . . . . . . . . . . . . . . .
45
2.6
Design of Common Mode Filter for AFE Converter . . . . . . . . . . . . . .
48
2.6.1
. . . . . . . . . . . . . . .
49
Common Mode Circuit of Proposed Topology . . . . . . . .
53
2.7
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
2.8
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
2.3
2.4
Selection of Filter Capacitor Cy and CMg
2.6.1.1
3 Active Damping
61
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
3.2
Transfer Function Analysis of LCL Filter . . . . . . . . . . . . . . . . . . . .
61
3.3
Passive Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
3.3.1
Differential Mode Damping . . . . . . . . . . . . . . . . . . . . . . .
62
3.3.2
Common Mode Damping . . . . . . . . . . . . . . . . . . . . . . . . .
65
State Space Representation . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
3.4.1
LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
3.4.2
Common Mode Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Active Damping Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
3.5.1
State Space Control Law . . . . . . . . . . . . . . . . . . . . . . . . .
71
3.5.2
Control Gain Formula . . . . . . . . . . . . . . . . . . . . . . . . . .
72
3.5.2.1
LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
3.5.2.2
CM Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
3.5.2.3
Sampling Technique . . . . . . . . . . . . . . . . . . . . . .
75
Analysis in Discrete Time Domain . . . . . . . . . . . . . . . . . . . . . . . .
76
3.6.1
76
3.4
3.5
3.6
Discrete Time Representation . . . . . . . . . . . . . . . . . . . . . .
vii
Contents
3.6.2
Closed Form Expression for Φ and Γ . . . . . . . . . . . . . . . . . .
76
3.6.2.1
Expressing Φ and Γ in terms of Filter Parameters . . . . . .
78
3.7
Reduced order estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
3.8
Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
3.9
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
4 Experimental Results
85
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
4.2
Experimental Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
4.3
Voltage Doubling at Motor Terminals . . . . . . . . . . . . . . . . . . . . . .
86
4.4
Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
4.4.1
L filter at Inverter Terminals . . . . . . . . . . . . . . . . . . . . . . .
87
4.4.2
dv/dt Filter at Inverter Terminals . . . . . . . . . . . . . . . . . . . .
87
4.4.2.1
Working of dv/dt Filter . . . . . . . . . . . . . . . . . . . .
89
4.4.2.2
Effectiveness of dv/dt Filter . . . . . . . . . . . . . . . . . .
93
Common Mode DC Bus Filter . . . . . . . . . . . . . . . . . . . . . . . . . .
93
4.5.1
Traditional Method . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
4.5.2
Proposed Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
4.5
4.6
CM Voltage at Motor Terminals . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.7
Active Damping using State Space Method . . . . . . . . . . . . . . . . . . . 106
4.8
4.7.1
Effect of Moving Average Filter . . . . . . . . . . . . . . . . . . . . . 106
4.7.2
Resonance Damping due to LCL filter . . . . . . . . . . . . . . . . . 106
4.7.3
Resonance Damping due to CM Filter . . . . . . . . . . . . . . . . . 108
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5 Conclusion
113
5.1
Summary of Present Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.2
Suggestions for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A Per Unit System
117
B Guideline from NEMA MG Part 31
121
C Experimental Setup
123
References
127
List of Tables
1.1
The switching states, pole voltages and common mode voltage magnitude . .
2.1
Net impedance of the winding for different DM configurations with identical
winding assumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
10
25
The behavior of motor with 100m long cable and parasitic capacitance between
the turns obtained for differential mode configuration for Y connected winding,
the leakage inductance is obtained using no-load and blocked rotor tests . . .
28
2.3
Design constraints and governing design variable for dv/dt filter . . . . . . .
36
2.4
Base Value used for calculations ActualV alue = P erU nit × BaseV alue . . .
57
2.5
Parameters for Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
2.6
Designed value of filter parameter . . . . . . . . . . . . . . . . . . . . . . . .
58
3.1
Value of α1 and α2 for different sampling time . . . . . . . . . . . . . . . . .
82
3.2
Value of Φ and Γ for different sampling time . . . . . . . . . . . . . . . . . .
82
3.3
Values of gain matrix coefficients . . . . . . . . . . . . . . . . . . . . . . . .
83
4.1
Reference to different experimental configuration and results . . . . . . . . .
85
4.2
Converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
4.3
The ground current, inverter output voltage dv/dt, voltage between neutral
point M to ground VMg with and without dv/dt filter and CM bus filter. . . . 111
C.1 Controller Parameter for system ratings indicated in Table. 4.2 . . . . . . . . 124
viii
List of Figures
1.1
The common mode and differential mode voltages and currents in a power
circuit with motor load connected. . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2
The characteristic impedance of cable and load with source. . . . . . . . . .
4
1.3
Motor cross-section showing shaft voltage and circulating current. . . . . . .
7
1.4
Parasitic capacitor associated with the motor. . . . . . . . . . . . . . . . . .
8
1.5
The inverter with diode bridge rectifier front end. . . . . . . . . . . . . . . .
9
1.6
Waveforms illustrating (a) CMV due to drive inverter alone and (b) resulting
CMC due to presence of parasitic capacitance. (c) CMV due to AFE rectifier
switching at higher frequency than inverter (d) CMV due to combined effect
of inverter and AFE rectifier (e) CMC with AFE rectifier ASD due to presence
of parasitic capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
1.7 dv/dt reactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
1.8
Sine filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
1.9
Basic sine filter with neutral point connected to DC bus mid-point O . . . .
15
1.10 Basic sine filter with neutral point connected to DC bus positive and negative
rail
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
1.11 dv/dt filter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
1.12 A variant of dv/dt filter topology. . . . . . . . . . . . . . . . . . . . . . . . .
16
1.13 The common mode voltage at motor neutral due to AZSPWM1 . . . . . . .
19
2.1
Three phase Y-connected stator winding with parasitic capacitance. . . . . .
22
2.2
(a) Turn-turn parasitic capacitance associated with the single winding (b)
turn-turn, turn- ground parasitic capacitance associated with the single winding 22
2.3
Impedance plot for Y connected DM arrangement of stator windings. . . . .
24
2.4
Impedance plot for Y connected CM arrangement of stator windings. . . . .
26
2.5
Differential Mode test set up for obtaining the impedance plot (a)∆ connected
(b) Y connected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
26
x
List of Figures
2.6
Impedance plot obtained using network analyzer for DM delta configuration
(indicated in Fig. 2.5 ). Behavior is inductive for frequencies between 50Hz
to 30kHz and capacitive between 60kHz to 100kHz in ∆-configuration. . . .
2.7
27
Impedance plot obtained using network analyzer for DM star configuration
(indicated in Fig. 2.5 ). Behavior is inductive for frequencies between 50Hz
to 70kHz and capacitive between 150kHz to 400kHz in Y-configuration. . . .
2.8
Common mode test set up for obtaining the impedance plot (a)∆ connected
(b) Y connected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9
27
28
Impedance plot obtained using network analyzer for CM delta configuration
(indicated in Fig. 2.8 ). Behavior is capacitive for frequencies between 2kHz
to 100kHz.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2.10 Impedance plot obtained using network analyzer for CM star configuration
(indicated in Fig. 2.8 ). Behavior is capacitive between 200Hz to 70kHz in
Y-configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
2.11 Impedance plot of motor along with long cable obtained using network analyzer for DM star configuration. Behavior is inductive for frequencies between
100Hz to 60kHz.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.12 Impedance plot of motor along with long cable obtained using network analyzer for CM star configuration. Behavior is capacitive between 1kHz to
60kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.13 Schematic of an active front end motor drive with integrated LCL filter for
the active front end rectifier, DC bus common mode filter, and dv/dt filter at
inverters terminal for the motor load. . . . . . . . . . . . . . . . . . . . . . .
33
2.14 Schematic of dv/dt filter shown for R-phase to illustrate the working of the
filter (a) The circuit when the top device conducts (Sr = 1) (b) the circuit
when the clamping diode (D1 ) conducts with top device still in conduction. .
34
2.15 Voltage across dv/dt filter capacitor and current through dv/dt filter inductor. 35
2.16 Single phase equivalent circuit of dv/dt filter with (a) motor leakage inductance taken into consideration for frequency ranges were the motor behaves
as inductive (b) motor turn to turn parasitic capacitance into consideration
for frequency ranges were the motor behaves as capacitive . . . . . . . . . .
36
2.17 The variation of resonant current and corresponding power loss in filter for
different values of inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
2.18 The allowable dv/dt given the cable length with risetime greater than propagation time of voltage wave and the dv/dt range for which the motor behavior
is inductive is indicated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
xi
List of Figures
2.19 Current through the filter inductor during switching transient . . . . . . . .
41
2.20 Current through the clamp during switching transient . . . . . . . . . . . . .
42
2.21 Power loss in the snubber and clamp diodes for different values of snubber
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.22 Schematic of PWM rectifier along with DC bus filter and LCL filter
. . . .
44
45
2.23 The CM circuit for PWM rectifier DC bus and LCL filter (a) without parasitic
capacitor (b) with parasitic capacitors . . . . . . . . . . . . . . . . . . . . .
48
2.24 Schematic of (a) PWM rectifier with LCL filter and Y-capacitor on DC bus
(traditional method for eliminating CM voltage) (b) The CM circuit of the
topology neglecting the parasitic capacitor. . . . . . . . . . . . . . . . . . . .
49
2.25 Low frequency approximation of common mode circuit with filter. . . . . . .
50
2.26 Frequency response plot of
icom3 (s)
VAF E (s)
for different values of Cb . . . . . . . . . .
2.27 High frequency approximation of common mode circuit with filter.
2.28 Frequency response plot of
iMg (s)
VAF E (s)
51
. . . . .
52
for different values of CMg . . . . . . . . .
52
2.29 Common mode circuit for the entire proposed topology.
. . . . . . . . . . .
53
2.30 Common mode circuit for the high frequency CM current on the motor side.
53
3.1
3.2
3.3
3.4
3.5
Single phase equivalent circuit of LCL filter connected between grid and power
converter. . . . . . . . . . . . . . . . . . . . . . . . . .
vc (s)
Frequency plot of transfer function
. . . . . . . .
vi (s)
iL (s)
Frequency plot of transfer function 1 . . . . . . . .
vi (s)
iL2 (s)
Frequency plot of transfer function
. . . . . . . .
vi (s)
Passive damping method with (a) damping resistor in
. . . . . . . . . . . .
62
. . . . . . . . . . . .
63
. . . . . . . . . . . .
63
. . . . . . . . . . . .
64
series with the filter
capacitor (b) damping branch Rd − Cd across the filter capacitor.
vc (s)
3.6 Frequency plot of transfer function
for damping technique
vi (s)
Fig. 3.5(a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vc (s)
for damping technique
3.7 Frequency plot of transfer function
vi (s)
Fig. 3.5(b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
. . . . . .
shown in
. . . . . .
65
shown in
. . . . . .
66
Passive damping of common mode resonance using (a)Resistance in series with
capacitor (b)series RC network across capacitor . . . . . . . . . . . . . . . .
3.9
64
66
The damping technique addresses (a) only DM resonance when S1 is open (b)
both DM and CM resonance when S1 is closed. . . . . . . . . . . . . . . . .
67
3.10 Low frequency approximate common mode circuit of proposed DC bus CM
filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
3.11 Block diagram of state space control. . . . . . . . . . . . . . . . . . . . . . .
72
xii
List of Figures
3.12 Schematic of the active rectifer controller and active damping loop for resonance due to LCL and CM filter. (a) PWM rectifier controller block diagram
with active damping. (b) Active damping block (i = a, b, c). . . . . . . . . .
75
3.13 Triangular carrier with sampling points indicated. . . . . . . . . . . . . . . .
76
4.1
(Top to bottom) ch2: line to line voltage VRY (500V/div), ch4: line to line
voltage VU V (500V/div), ch1: ground current Icom (5A/div), time 5µs/div. .
4.2
86
(Top to bottom) ch4: line to groung voltage at motor terminal VU g (500V/div),
ch3: pole voltage R-phase inverter terminal to mid-point of DC bus VRO
(500V/div), ch1: R-phase current IR (5A/div), ch2: ground current Icom
(1A/div), time 25µs/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
87
(Top to bottom) ch4: line to groung voltage at motor terminal VU g (500V/div),
ch3: pole voltage R-phase inverter terminal to mid-point of DC bus VRO
(500V/div), ch1: R-phase current IR (5A/div), ch2: ground current Icom
(1A/div), time 10ms/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Voltage measured at neutral of motor w.r.t ground (Common mode voltage)
Vng (500V/div) and the ground current (0.5A/div), time 100µs/div. . . . . .
4.5
89
ch1: R-phase pole voltage VRO (500V/div), ch3: R-phase dv/dt filter capacitor
output VCf (500V/div), time (2.5µs/div). . . . . . . . . . . . . . . . . . . . .
4.7
88
R-phase pole voltage VRO (250V/div), time 250ns/div. The rise time of the
pole voltage is approximately 200ns. . . . . . . . . . . . . . . . . . . . . . . .
4.6
88
90
(Top to bottom) ch1: R-phase pole voltage VRO (500V/div), ch2: R-phase
dv/dt filter capacitor output VCf (500V/div), ch3: Inductor current Ires (10A/div),
ch4: clamp diode voltage VD1 (500V/div), time 10µ s. . . . . . . . . . . . . .
90
4.8
The snubber voltage Vs (25V/div). . . . . . . . . . . . . . . . . . . . . . . .
91
4.9
ch1: dv/dt filter inductor voltage VLf (250V/div), ch3: snubber voltage Vs
(250V/div), time 5µ s/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
4.10 (Top to bottom) ch4: line to line voltage before dv/dt filter VRY (1kV/div),
ch1: line to line voltage after dv/dt filter VU V (1kV/div), ch3: R-phase current
before dv/dt filter ILf (10A/div), ch3: R-phase current after dv/dt filter IU
(5A/div), time 10ms/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
4.11 (Top to bottom) Pole voltage for R, Y and B phase before filter(500V/div),
time 100µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
4.12 (Top to bottom) Pole voltage for R, Y and B phase before filter(500V/div),
time 100µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
List of Figures
xiii
4.13 (Top to bottom) ch2: pole voltage VRO (500V/div), ch3: pole voltage after
dv/dt filter VCf (500V/div), ch4: line to ground voltage at motor terminal
VU g (500V/div), ch1: ground current Icom (1A/div), time 10µs/div. . . . . .
94
4.14 (Top to bottom) ch2: pole voltage VRO (500V/div), ch3: line to ground voltage
at motor terminal VU g (500V/div), ch4: line to neutral voltage at motor
terminal VU g (500V/div), time 10ms/div. . . . . . . . . . . . . . . . . . . . .
94
4.15 (Top to bottom) ch3: line to neutral voltage at motor terminal VU g (500V/div),
ch1: load current IU (0.5A/div), ch4: ground current Icom (0.5A/div), time
25µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
4.16 (Top to bottom) ch3: line to neutral voltage at motor terminal VU g (500V/div),
ch1: shaft voltage at the Drive End (DE) Vsh(DE) (20V/div), ch4: ground current Icom (0.5A/div), time 50µs. . . . . . . . . . . . . . . . . . . . . . . . . .
95
4.17 (Top to bottom) ch1: DC bus voltage VDC (500V/div), ch3: No-load current
IA (5A/div), ch4: common mode voltage VOg (500V/div), time 0.5s/div. . . .
96
4.18 ch4: common mode voltage VOg (500V/div), ch3: ground current due to PWM
rectifier Icom (0.1A/div), time 25µs/div. . . . . . . . . . . . . . . . . . . . . .
97
4.19 ch1: common mode voltage VOg (50V/div), ch2: LCL filter neutral point to
ground voltage VNg (250V/div), ch4: ground current Icom (2A/div) for SPWM,
time 2.5ms/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
4.20 ch1: common mode voltage VOg (50V/div), ch2: LCL filter neutral point
to ground voltage VNg (250V/div), ch4: ground current Icom (2A/div) for
CSVPWM, time 2.5ms/div . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
4.21 FFT around 150Hz of ground current injection into ground due to SPWM in
case of traditional CM elimination method. . . . . . . . . . . . . . . . . . . .
98
4.22 FFT around 150Hz of ground current injection into ground due to CSVPWM
in case of traditional CM elimination method. . . . . . . . . . . . . . . . . .
99
4.23 ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div),
ch4: ground current Icom1 (0.2A/div) for SPWM, time 10ms/div. . . . . . . . 100
4.24 ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div),
ch4: ground current Icom1 (0.2A/div) for SPWM, time 10ms/div. . . . . . . . 100
4.25 ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div),
ch4: ground current Icom1 (0.2A/div) for SPWM, time 250µs/div. . . . . . . 101
xiv
List of Figures
4.26 ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div),
ch4: ground current Icom1 (0.2A/div) for SPWM, time 250µs/div. . . . . . . 101
4.27 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div. 102
4.28 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 1ms/div. . 103
4.29 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div. 103
4.30 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 25µs/div.
104
4.31 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div. 105
4.32 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div. 105
4.33 ch1: common mode voltage appearing between neutral of the winding to
ground Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div. 106
4.34 Converter side current sampled through ADC with and without moving average filter (5A/div), time 5ms/div. . . . . . . . . . . . . . . . . . . . . . . . . 107
4.35 LCL filter R-phase capacitor voltage Vclf (100V/div), time 5ms/div. . . . . . 107
4.36 LCL filter R-phase capacitor voltage Vclf (100V/div), time 5ms/div. . . . . . 108
4.37 The CM voltage from mid-point of DC bus (O) to ground VOg using CSVPWM
(a) with Rd − Cd passive damping network introduced in the LCL-filter (b)
without the damping resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.38 FFT of CM voltage from mid-point of DC bus (O) to ground VOg using
CSVPWM (a) with Rd − Cd passive damping network introduced in the LCLfilter (b) without any damping resistor. . . . . . . . . . . . . . . . . . . . . . 109
4.39 ch1: common mode voltage at the DC side VOg (50V/div), ch2: common mode
current Icom (2.5A/div), time 2.5ms/div . . . . . . . . . . . . . . . . . . . . 110
4.40 ch1: common mode voltage at the DC side VOg (50V/div), ch2: common mode
current Icom (2.5A/div), time 2.5ms/div . . . . . . . . . . . . . . . . . . . . 110
B.1 Voltage response at motor terminal for a step input voltage . . . . . . . . . . 121
C.1 Controller block diagram [23] along with active damping loop and proposed
filter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
List of Figures
xv
C.2 Experimental setup (1) dv/dt filter board - clamp diodes, snubber circuit, CMg
capacitor (2) dv/dt filter inductor (3) CM DC Bus filter capacitor (4) LCL filter126
Chapter 1
Introduction
Variable voltage variable frequency converters are the backbone of motor control industries.
The converters uses IGBT as switching device which makes it easer to control as compared
to thyristor based inverters. Advancement in semiconductor technology have enabled in
developing such sophisticated power converters. The advantages of using IGBT based power
converter are as following,
• High switching frequency.
• Smaller turn-ON and turn-OFF times, this reduces switching losses.
• Advanced PWM techniques can be used for control.
Some of the applications require long cable to connect the motor and the power converter.
In these cases, it has been observed that the voltage at the motor terminal doubles during
the switching transients [1]. This adversely affects the motor. The high dv/dt at the inverter
end leads to problems due to faster turn-ON and turn-OFF times, such as,
• Increased ground currents apart from voltage doubling at motor terminal.
• Bearing damage and insulation failure at load end.
• EMI/EMC concerns.
The DC link capacitor is charged, in traditional drive system, using three phase diode
bridge rectifiers. This resulting in injection of lower order harmonics into grid. As the lower
order harmonics are not desirable, the alternate solution is to use PWM rectifier as FrontEnd converter to charge the DC link capacitor [2, 3]. The advantage of PWM rectifier is as
following,
• Lower order harmonics are eliminated.
1
2
Chapter 1. Introduction
• Regenerative action.
• Increased DC bus voltage.
• Unity factor operation.
Though PWM rectifier eliminates lower order harmonics, it inject high frequency electrical noise due to PWM action. The high dv/dt excites the capacitive coupling which leads
to increased ground currents. The problem becomes predominant as the PWM rectifiers are
usually switched in the range of 5kHz to tens of kilo hertz. The electrical noise produced
by such AFE converter cascades with the noise due to PWM inverter and appear at motor
terminals. This aggravates the problems at the motor end.
Standards such as CISPR22 and IEC specify the limits on the current injection into the
ground by power converter for commercial and domestic applications. NEMA MG-1, part
31 recommends the maximum allowable dv/dt that can be applied at the motor terminal for
safe operation. The definition of common mode voltage and current in a power converter,
problems associated with high dv/dt and the mitigation technique adopted to meet the limits
set by the standards for safe operation are briefly discussed in the following sections.
1.1
Definitions
Fig. 1.1: The common mode and differential mode voltages and currents in a power circuit
with motor load connected.
The differential mode and common mode voltages and currents are as shown in Fig. 1.1.
The common mode voltage is defined as the mean of line to ground voltages. For the system
shown the common mode voltage of load side can be expressed as,
vcom |ac =
vRg + vYg + vBg
3
(1.1)
1.2. Voltage Doubling at Motor Terminal
3
On the DC side the common mode voltage is expressed as,
vcom |dc =
VPg + VNg
2
(1.2)
The common mode current that flows through the circuit as a result of common mode
voltage is defined as sum of the currents circulating from the line to ground and back. The
current flowing can be separated in to differential mode current and common mode current.
For the system shown the common mode current is as expressed as,
icom = iR + iY + iB
(1.3)
The icom current flows through parasitic capacitance and through the ground and grid
back to the DC bus. (This complete loop is not indicated in the Fig. 1.1)
The differential voltage of the system are defined as line to line voltages, line to neutral
voltages. The equations governing the differential mode voltages are,


vRY


 vY B






=


vBR

vRn


 vY n

1 −1
0
−1



1

=

3


 −1

1




vRO


 v

1 −1 
 YO 
0
1
vBO
0 −1
1
0 −1
vBn
0



(1.4)

vRY


 v

0 
 YB 
1
vBR
(1.5)
The differential mode currents are given as,

iRY


 iY B







=


iBR

iR


 iY

iB
1 −1
0
−1



1

=

3


 −1

1
0



iR



 i 
1 −1 
 Y 
0
1
iB
0 −1
1
0 −1



iRY
(1.6)



 i

0 
 YB 
1
iBR
(1.7)
The net voltage to ground can be written as a sum of differential mode voltage and common
mode voltage. Similarly, the net current as a sum of differential mode current and common
mode current.
1.2
Voltage Doubling at Motor Terminal
The phenomenon of voltage doubling effect is predominant in long cable due to transmission line like behavior as a result of fast rise and fall time of switching device like IGBT
4
Chapter 1. Introduction
Fig. 1.2: The characteristic impedance of cable and load with source.
and cable parasitics [1]. To understand this consider the representation of system as two
conductor system with ground as return conductor shown in Fig. 1.2. The losses in the line
are neglected. The transmission line equations for such as system is as following,
∂V (z, t)
∂I (z, t)
= l
∂z
∂t
∂I (z, t)
∂V (z, t)
= c
∂z
∂t
(1.8)
(1.9)
On differentiating (1.8) wrt z and (1.9) with t, substituting (1.9) in (1.8) yields (1.10),
similarly (1.11) can be obtained.
∂ 2 V (z, t)
∂ 2 V (z, t)
=
lc
∂z 2
∂t2
2
2
∂ I (z, t)
∂ I (z, t)
= lc
2
∂z
∂t2
(1.10)
(1.11)
The solution for the above telegraphs equation can be expressed as,
V (z, t) = V + (t − z/v) + V − (t + z/v)
(1.12)
I(z, t) = I + (t − z/v) + I − (t + z/v)
1
1 +
V (t − z/v) − V − (t − z/v)
=
Zc
Zc
(1.13)
(1.14)
where V + (t − z/v) {I + (t − z/v)} is forward voltage (current) traveling wave and V − (t +
z/v) {I − (t + z/v)} is backward voltage (current) traveling wave. Zc is the characteristic
impedance of the cable and v (m/s) is the propagation velocity of forward and backward
traveling wave.
√
1
l
= vl =
c
vc
1
v = √
lc
Zc =
(1.15)
(1.16)
1.2. Voltage Doubling at Motor Terminal
5
The total length of the cable be denoted as L (m). The load characteristic impedance is Zl
(Ω) and that of source is Zs (Ω). The forward and backward traveling voltage wave at load
end are related through load reflection co-efficient ρL .
ρL =
V − (t + z/v)
Zl − Zc
=
V + (t − z/v)
Zl + Zc
(1.17)
The reflected wave is identical to the incident wave at load end multiplied by load co-efficient
ρL . When a step like voltage rich in harmonics is applied at source end (z = 0) the incident
voltage wave (V + (t − z/v)) travels down the line towards the load. The time taken by
L
V + (t − z/v) to reach the load is tp = . The reflected wave will not occur until the delay tp .
v
The reflected wave will reach the source end after the time period of 2tp . For a duration of 2tp
the total voltage and current will only consist of V + (t − z/v) = V (0) and I + (t − z/v) = I(0)
which is related to characteristic impedance as,
Zc =
V (0)
I(0)
0 ≤ t ≤ 2tp
(1.18)
Therefore during this transient the initial magnitude of forward traveling voltage and
current is expressed as,
{
}
Zc
V = Vs
Zc + Zs
}
{
1
I + = Vs
Z c + Zs
+
(1.19)
(1.20)
As Zs ≪ Zc it can be inferred that magnitude of initial forward traveling voltage is same
as the applied source voltage Vs . The reflected wave is initiated when the forward traveling
wave reaches load after time tp . After an additional time tp the reflected pulse reaches the
source end, where reflected voltage gets re-reflected and is related through source reflection
co-efficient ρs ,
ρs =
Zs − Zc
Z s + Zc
(1.21)
which is the ratio of the incoming voltage towards source to the reflected wave heading
towards the load end. This forward traveling wave is identical in shape to the backward
traveling wave multiplied by ρs . This process of repeated reflections happen at the source
and load end.
For a bare conductor the velocity of propagation of wave is equal to velocity of light
(vlight = 3 × 108 m/s). If the cable is coated with insulating material such as PVC etc, with
permittivity ϵ the velocity of propagation of wave changes to,
vlight
v= √
ϵ
(1.22)
6
Chapter 1. Introduction
The impedance offered by load (in this case the motor) is very high compared to the
impedance of the cable i.e Zl ≫ Zc . Hence, the load reflection co-efficient can be approximated as,
ρL ≈ 1
(1.23)
At source end Zs ≪ Zc , hence source reflection co-efficient can be approximated as,
ρL ≈ −1
(1.24)
With this approximation the voltage at the motor terminal ideally will be,
Vm = Vs (1 + ρL )
(1.25)
≈ 2Vs
(1.26)
Practically the load reflection coefficient ρL <1. At the source end the re-reflected forward
traveling wave having magnitude −Vs will be sent towards the load. As the load impedance
is higher than the cable characteristic impedance the reflected wave would have magnitude
identical to that of incident wave resulting in voltage doubling. Comparing the rise time of
IGBT device and propagation time it is easy to show how IGBT inverter aggravates this
problem. Let tr be the rise time of the inverter output voltage (source voltage Vs as shown
in Fig. 1.2). If tr ≤ tp the incident voltage wave magnitude would have raised to the applied
voltage magnitude. Therefore, at the motor terminal the reflected wave adds to the applied
voltage and hence the effective magnitude would double after time tp . If tr ≥ tp , after time
delay tp the applied voltage would only be a fraction of the required voltage magnitude, as a
result the incident wave will only be a fraction of source voltage. The motor terminal voltage
will now be,
k≤1
Vm = kVs (1 + ρL ) = 2kVs
(1.27)
This shows that the rise time of the inverter output voltage plays a crucial role in causing
the voltage doubling at motor terminal. As the present day IGBT switching times are
becoming smaller the problem gets aggravated. Smaller the rise time higher the dv/dt of
output voltage of IGBT inverter. If the insulation of the cable is known then the propagation
time can be approximately calculated. The length of the cable that can be used without
voltage doubling at the motor terminal for a given dv/dt of inverter output voltage is called
critical cable length, given by,
v
1
lc =
=√
tp
ϵ
{
vlight
tp
}
(1.28)
If the rise time is such that the factor k is 0.5, the doubling at motor terminal is avoided and
the electrical distance remains same as mechanical distance (L). It is important to co-relate
1.3. Effect of High Frequency Common Mode Voltage on Motor
7
the rise time and the motor terminal voltage to the insulation (dielectric) withstand of the
motor.
Present day IGBT has rise time of the order 10−9 (s) and if PVC insulated cable is used
the propagation velocity will be roughly 1.6 × 108 (m/s) and hence the propagation time for
a cable length of 10m would be of the order 10−9 (s). Hence even for a cable length of 10m ∼
30m voltage doubling effect can be seen. As the rise time of IGBT gets smaller the problems
related to voltage doubling and ground current gets worse.
1.3
Effect of High Frequency Common Mode Voltage
on Motor
Fig. 1.3: Motor cross-section showing shaft voltage and circulating current.
The PWM inverter switches at high frequency and the output voltage has high dv/dt, this
leads to generation of high frequency common mode voltage resulting in increased ground
currents. The common mode voltage and current are the major cause of bearing and insulation failure in the motors [4–8]. The cross sectional diagram of the motor is as shown
in Fig. 1.3. To understand the adverse effect of high frequency, high dv/dt common mode
voltage it is important to understand the mechanism of generation of bearing currents and
ground currents.
The ground currents occur due to excitation of parasitic capacitor coupling between
stator to ground, rotor to ground as shown in Fig. 1.4. In the recent past the bearing
damage due to bearing current was known due to electro-magnetic induction caused by
magnetic dissymetries [9]. The common mode current produced due to common mode voltage
generates high frequency common mode flux that links the NDE shaft, motor frame and DE
shaft resulting in induced shaft voltage. This results in circulating bearing current. The
capacitive coupling exists between rotor and stator due to lubrication of the bearing. The
voltage that results across the bearing capacitor results in bearing current. The resulting
8
Chapter 1. Introduction
Fig. 1.4: Parasitic capacitor associated with the motor.
shaft voltage can be classified into shaft end to end voltage and shaft to frame voltage [10,11].
Apart from this the rotor to ground displacement current circulates through shaft, bearings
and motor frame. It has been observed that the induced voltage in shaft results in damaging
sensitive equipments coupled to shaft such as encoders [7]. At fundamental line frequency
the maximum shaft voltage to ground is usually designed to be less than 1Vrms, but this
limit is often exceeded when ASD is used to control the motor. The thin lubricant grease
with low dielectric strength around the ball bearings breakdown due to high shaft voltages
resulting in steep rise in the current that affects the ball bearing races. This phenomenon is
called Electric Discharge Machining (EDM). This current results in arcing over ball bearing
creating hot spots that causes microscopic craters on the surface of ball bearing. Further the
dislocated metal particle pollute the lubricant thereby decreasing the dielectric withstand.
The other reason for dielectric breakdown can be accounted due to chemical changes in the
lubricant as a result of being subjected to frequent high dv/dt [12].
PWM converter actuating the motor applies step like steep fronted voltage pulses. Due
to this the distribution of voltage along winding coils is not uniform during the transients.
Higher voltage stress is seen in first few terminal coils. The uneven distribution of voltage
is due to parasitics in the winding [4]. The parasitic capacitor between turn to turn, turn
to ground dominate at high frequency. In a random wound machine the first and last coil
location are not exactly known and thus may differ in different slots. In worst case scenario
the first and last turn may appear adjacent to each other. The insulation will give away due
to the voltage stress. When a long cable is used the matters are further worsened due to
higher voltage at motor terminal during switching transients.
1.4
Common Mode Voltage due to Power Converter
When a diode bridge rectifier is used the common mode voltage is smoothly varying with
three times the supply frequency. The the dv/dt of common mode voltage due to three
phase diode bridge rectifier as converter is low. Therefore at high frequency the effect of
1.4. Common Mode Voltage due to Power Converter
9
diode bridge on ground currents is negligible. However it is not so in case of the power
converter switching at high frequency. The motor drive with diode bridge rectifier as front
end converter and inverter is as shown in Fig. 1.5. The common mode voltage for such a
drive system is defined as,
Fig. 1.5: The inverter with diode bridge rectifier front end.
Vinv =
VRO + VY O + VBO
3
(1.29)
The common mode voltage on the DC bus due to diode bridge rectifier (i.e VOg ) is negligible.
The magnitude of Vinv for possible switching states of the converter is shown in Table. 1.1.
The maximum and minimum value of the common mode voltage is +Vdc /2 and −Vdc /2,
step like waveform with frequency close to switching frequency. This common mode voltage
produced due to switching action of inverter appears at the motor neutral terminal as shown
in Fig. 1.6(a). The motor at high frequency can be approximated to be capacitive (i.e net
capacitance of parasitics shown in Fig. 1.4) on common mode basis, with value of parasitic
capacitor Cp in range of few tens of nanofarad. The current injection into ground is ideally
given by (1.30). The waveform of the common mode voltage and current is as shown in
Fig. 1.6(a) and Fig. 1.6(b)
ig = Cp
dvinv
dt
(1.30)
When the diode bridge rectifier is replaced with PWM rectifier, the common mode voltage
produced at the DC bus cannot be neglected. It gets added with common mode voltage of
the inverter and appears at the neutral of the motor as,
Vcom = Vinv + VOg
(1.31)
This worsens the problem caused due to common mode voltage on the motor. The AFE
converter is switched at high frequency (few tens of kilohertz), where as inverter for high
10
Chapter 1. Introduction
Table 1.1: The switching states, pole voltages and common mode voltage magnitude
Sl.No Switching States
VRO
VY O
VBO
Vinv
1
+−−
+
Vdc
2
−
Vdc
2
−
Vdc
2
−
Vdc
6
2
++−
+
Vdc
2
+
Vdc
2
−
Vdc
2
+
Vdc
6
3
−+−
−
Vdc
2
+
Vdc
2
−
Vdc
2
−
Vdc
2
4
−++
−
Vdc
2
+
Vdc
2
+
Vdc
2
+
Vdc
6
5
−−+
−
Vdc
2
−
Vdc
2
+
Vdc
2
−
Vdc
6
6
+−+
+
Vdc
2
−
Vdc
2
+
Vdc
2
+
Vdc
6
7
+++
+
Vdc
2
+
Vdc
2
+
Vdc
2
+
Vdc
2
8
−−−
−
Vdc
2
−
Vdc
2
−
Vdc
2
−
Vdc
2
power motor is switched at relatively lower switching frequency (upto 5kHz). The PWM
converter common mode voltage due to combined effect of PWM rectifier and inverter is
illustrated in Fig. 1.6(d). The common mode voltage magnitude transits between ±Vdc , ±
2 V 3dc , ±
V dc
,
3
0.
It is apparent that the frequency of current injection into ground is increased shown in
Fig. 1.6(e) as compared to the case illustrated in Fig. 1.6(b). The dv/dt and the parasitics of
the system has not changed except for the frequency due to AFE converter. It is important
to note that practically the current injected to ground would oscillate and die down to zero
eventually. A steep change in voltage can occur before the ground current goes to zero due
to AFE converter operation resulting in ground current adding to the existing current. This
will lead to increased magnitude of ground current. As one of the causes for shaft voltage
to build up is the high frequency flux produced due to common mode current the problem
related to EDM get aggravated.
1.4. Common Mode Voltage due to Power Converter
11
Fig. 1.6: Waveforms illustrating (a) CMV due to drive inverter alone and (b) resulting CMC
due to presence of parasitic capacitance. (c) CMV due to AFE rectifier switching at higher
frequency than inverter (d) CMV due to combined effect of inverter and AFE rectifier (e)
CMC with AFE rectifier ASD due to presence of parasitic capacitance.
12
1.5
Chapter 1. Introduction
Mitigation Techniques
Many different solutions have been proposed and practiced in industry. The mitigation
technique have been proposed at inverter end and motor end [13–19]. These solutions are
sometimes used in combinations to get better results. Some of the well known techniques
are briefly outlined as following,
1. To address voltage doubling at motor terminal.
• Inverter End
(a) Passive filter —Sine filter, reactor, dv/dt-filter etc.
(b) Active filters
• Motor End
(a) Passive filter —shunt filters
(b) Increase the grade of motor insulation.
2. To address bearing damage and ground currents.
• Inverter End
(a) Passive filter —sine filter, reactor, common mode choke etc.
(b) Active filters —addressing common mode voltage, common mode current or
both.
(c) ASD carrier settings and RCMV-PWM techniques
• Motor End
(a) Insulated bearing
(b) Grounding shaft
(c) Increasing conductivity of bearing lubricant
(d) Hybrid bearing
(e) Electro-statically shielded motor
1.6
1.6.1
Filters
Passive Filters
Passive filters address the problems caused due to high dv/dt. Based on the type of the
filter used either common mode voltage, common mode current or both are eliminated.
Traditionally used filters focuses on producing voltage which closely resembles the sinusoidal
1.6. Filters
13
voltage. The trade off made to meet such specifications is cost, size and powerloss. The
design of different passive filters is briefly reviewed [15–19].
1.6.1.1
Output Reactor
The inductor connected at the output for each phase of the inverter is as shown in Fig. 1.7.
Usually the inductance value is chosen 5% on base value. This type of filter helps reducing the
ripple in the current and thereby decreasing the ripple flux. This attenuates the circulating
current produced from the carrier frequency flux. The capacitive currents due to parasitics
of cable and motor also reduced due to reduced dv/dt. However, on the common mode it
may cause resonance. This increases the shaft voltage resulting in higher EDM.
Fig. 1.7: dv/dt reactors
The power loss in this filter is high as it carries fundamental and other harmonic currents.
Its size is large based on the type of core used and the current rating. Though simple to
implement, the high cost and ineffective filtering makes it a low performance solution.
1.6.1.2
Common Mode Filter
This is one of the effective methods of reducing common mode current. The winding on the
core for each phase are wound in the same direction. This cancels out the flux produced by
the line currents and the flux produced due to ground currents add. Therefore the common
mode choke offer ideally zero inductance to line currents and offers a high inductance to
common mode currents. While constructing the CM choke one must separate the first turn
from the last turn otherwise the parasitic capacitance for high frequency shunts the core
which reduces its effectiveness. It does not alter the common mode voltage as the slopes of
the common mode current are altered by selectively introducing common mode inductance.
1.6.1.3
Sine Filters
The basic topology of sine filter is as shown in Fig. 1.8. LC filter bring the voltage and
current close to sinusoidal, therefore, is referred as sine filter. Sinusoidal voltage variation
leads to reduced dv/dt, this eliminates the voltage doubling at motor terminal as well as
addresses the problems related to high dv/dt on motor.
14
Chapter 1. Introduction
The sine filter solves the problem but leads to some new ones. The resonance caused by
sine filter needs to be damped. The losses in a practical filter are high, also it occupies large
space and is expensive.
Fig. 1.8: Sine filter
Most of the standard industrial motor require the motor voltages to be almost sinusoidal.
The effectiveness of the design of such filter to meet this specification depends upon the
resonance frequency.
1
ωr = √
Lf Cf
(1.32)
Usually the resonance frequency is kept less than the lowest harmonic frequency of the
PWM inverter ( i.e. less than switching frequency) and above the maximum fundamental
frequency. This is done so that the harmonics generated by PWM inverter are not amplified
and it is also possible to damp the resonance. The voltage below the resonance frequency
pass without attenuation and voltages above the resonance frequency are attenuated at
40dB/dec. The damping of such filter can be either passive or active. The passive damping
reduces the performance of the filter and increases the overall power loss.
The common mode voltage is not addressed by the sine filter shown in Fig. 1.8. With
slight modification of sine filter both common mode and differential mode voltages and
currents are addressed as shown in Fig. 1.9 and Fig. 1.10. The neutral point of the filter is
connected back to mid-point of the DC bus and in other topology connected to positive DC
bus and Negative DC bus. This arrangement gives a circulating path for the common mode
current due to common mode voltage produced by PWM inverter.
1.6.1.4
Clamp Filters
The main aim of such filter is to address the high dv/dt of PWM converter, therefore, referred
to as dv/dt filter. The dv/dt filter is as shown in Fig. 1.11, many variant of such filter is
1.6. Filters
15
Fig. 1.9: Basic sine filter with neutral point connected to DC bus mid-point O
Fig. 1.10: Basic sine filter with neutral point connected to DC bus positive and negative rail
16
Chapter 1. Introduction
available. The design of filter is such that it changes the slope of PWM converter output.
The resonance frequency is selected above the switching frequency to achieve it. This results
in small value of inductance and capacitance.
The filter alters the rise time this results in decreased dv/dt. Since the filter only suppresses voltage spike it does not address the ripple (i.e differential mode) component. The
overall power loss in the filter is less compared to traditional sine filters. Also the size is
smaller compared to conventional filters and less expensive. The other variant of this filter is
shown in Fig. 1.12. In this topology additional resistance is required to damp the oscillations.
Fig. 1.11: dv/dt filter topology.
Fig. 1.12: A variant of dv/dt filter topology.
1.6.2
Active Filters
To eliminate the common mode voltage or current active complementary power device is
used. The active element can either be used as switch or linear amplifier. To eliminate the
1.7. Other Mitigation Techniques
17
common mode voltage produced due to inverter at load end, a compensating common mode
voltage is superimposed on the inverter output voltage.
As compared to passive filters this technique effectively eliminates common mode component. Also the power loss is less compared to passive filter. Nevertheless, the cost involved
is high. Active filters requires regular monitoring and are less reliable compared to passive
filter.
1.7
1.7.1
Other Mitigation Techniques
Increasing Insulation Grade
One of the methods to tackle the damage of motor insulation without eliminating voltage
doubling is to increase the grade of insulation. This is the method adopted by the motor
manufactures, which is available as PWM inverter grade motors commercially. The cost
of such motors are higher. Increased insulation grade worsens the thermal capacity of the
motor effectively derating the motor for a given frame size and slot geometry.
1.7.2
Insulated Bearing
The bearing of the motor is insulated. By insulating the bearing the conducting path for
the current is eliminated. To effectively prevent the flow of bearing current both the DE
and NDE bearing has to be insulated. This is done to prevent the stress on non-insulated
bearing.
The disadvantage is that the electrical noise source is not eliminated. The circulating
current would be produced through any load or coupled device. This may result in damage
of bearings of connected load. The contamination and aging of insulation calls for regular
maintenance. The insulating material is typically ceramic or polymer coating.
1.7.3
Grounding Shaft
The common mode current is diverted through alternate path by connecting the shaft of
the motor to ground. This is relatively simple technique and the cost is low. The shaft is
connected to ground via electrical contact brush as continuous contact is necessary. This becomes effective as the common mode current now bypasses the bearings resulting in increased
life of bearings.
However, the circulating current due to high frequency flux can flow through the load
which is coupled to motor. Over the time, impedance between shaft and ground increases due
to mechanical wear and tear, the oxidation of contact surface the needs regular maintenance.
18
Chapter 1. Introduction
1.7.4
Conductive Lubricant
If the shaft of the motor is not grounded, the other way to of avoiding the flow of common
mode current through bearing is by introducing conducting grease. Electrically conductive
particles are introduced into bearing lubricant. This reduces the dielectric withstand of the
lubricating grease. This again is a short term mitigation technique that requires maintenance.
The conductive materials cause abrasion resulting in decreased life of bearing.
1.7.5
Electro-statically Shielded Motor
Electrostatic coupling exists between stator and rotor through parasitic capacitor. This
coupling is removed by introducing electrostatic shield between the rotor and stator. This
eliminates the circulating currents that flow through bearing, resulting in increased life of
bearing. However, the rotor and stator are separated by very small air gap which poses
mechanical challenges in introducing the shield. Additional power losses are introduced in
the shield affecting motor efficiency. This is a special construction of motor, and therefore
will not be available in commercial motor from many vendors.
1.7.6
ASD Carrier Setting and PWM Techniques
In this method the lowest possible carrier frequency allowed by the application is selected.
This reduces the frequency of transition of common mode voltage resulting reduced number
of EDM and dv/dt. This just may probably increase the life of the bearing. Though it is
not a preferred method as it increases the ripple on the differential mode.
The common mode voltage due to inverter changes by ±V dc/2 during switch state
change. All the conventional PWM technique exhibit high common mode voltage and current that results in damaging the motor bearings. Various modified PWM strategies have
been developed these result in reduced magnitude of common mode voltage. These are classified as reduced common mode voltage PWM (RCMV-PWM). PWM methods that yield
reduced common mode voltage have been reported in [20]. Some of these methods are Active
Zero State PWM1 (AZSPWM1), AZSPWM2, AZSPWM3, Remote State PWM (RSPWM)
and Near State PWM (NSPWM).
In the conventional PWM method reference vector is generated using the active vectors
adjacent to reference vector and inverter zero vectors. In RCMV-PWM techniques only
active vectors are used. The RCMV-PWM method differs based on how the volt-seconds
is balanced using active vectors. In case of AZSPWM1 and AZSPWM 2 the effective zero
vector is obtained with two near opposing active vectors and for AZSPWM3 using one of the
adjacent active vector and its opposite vector. Fig. 1.13 shows the common mode voltage
1.8. Summary
19
at motor neutral due to AZSPWM1 simulated using Simulink. The common mode voltage
magnitude switches between ±Vdc /6 for RCMV-PWM method. This results in reduced
common mode current. However, the choice of PWM strategy cannot be based only on
Fig. 1.13: The common mode voltage at motor neutral due to AZSPWM1
RCMV as the output current ripple, power loss, voltage linearity, implementation constraints
etc., has to be taken into account. The trade off between the performance parameters have
to be throughly studied before selecting the RCMV-PWM technique. The RCMV-PWM
does not eliminate the common mode voltage.
1.8
Summary
The discussion on issues related to active front end based adjustable speed drive is presented.
The effects of long cable at the motor terminal during switching transients and the effect
of high dv/dt output voltage of PWM inverter on the motor is explained. Comparison of
common mode voltage due to three phase diode based ASD and PWM rectifier based ASD
on the motor terminal is presented in detail.
Different mitigation technique adopted at the motor terminals and at the inverter terminal are discussed briefly. The emphasis is given to filter techniques at the inverter terminal.
Both passive, active filters are discussed with pro and cons. PWM techniques adopted to
reduce common mode voltage are compared with SPWM technique. The modifications in
motor to address the effects of high dv/dt voltage are briefly mentioned.
20
Chapter 1. Introduction
Chapter 2
Filter Design
2.1
Introduction
This chapter gives a brief overview on the high frequency behavior of the induction machine.
Theory and design of dv/dt filter and common mode filter are discussed. The common mode
circuit for the proposed topology is analyzed illustrating the path for common mode current.
The design example for dv/dt filter and CM filter is included in section 2.7.
2.2
High Frequency Behavior of Induction Motor
The PWM inverter excites the motor with steep voltage pulses, the harmonic spectrum of
the output voltage contains fundamental and multiples of switching frequency components.
When such a voltage pulse rich in harmonics is applied, the behavior of motor will be different
for different range of frequencies. The motor behavior can be studied with the help model
for low and high frequency components. The motor behaves inductive for certain range
of frequencies and capacitive beyond certain range when excited with different harmonic
components. The motor, therefore, can be modeled as lumped or distributed circuit based
on the requirement [26, 27].
In this chapter the high frequency behavior of the motor will be discussed along with
the brief discussion on methods of obtaining the value of parasitics of the motor. The
complete distributed circuit parameters contains turn to turn, turn to ground capacitances,
self inductance, mutual inductance and resistance at different frequencies due to skin and
proximity effect. Fig. 2.1 shows three phase winding connected in Y -configuration with turn
to turn, phase to phase and phase to ground parasitic capacitance present in each phase.
The model is studied using lumped network at low frequencies, as it is a small fraction of
wavelength. At lower frequencies the capacitive coupling do not play any significant role. The
High Frequencies (HF) components excite the capacitive coupling, which the low frequency
model does not account. At HF motor model is suitably modified to include the capacitive
21
22
Chapter 2. Filter Design
Fig. 2.1: Three phase Y-connected stator winding with parasitic capacitance.
Fig. 2.2: (a) Turn-turn parasitic capacitance associated with the single winding (b) turnturn, turn- ground parasitic capacitance associated with the single winding
parasitics. The lumped HF model is an approximate model and therefore is not as accurate
as the distributed motor model. In form wound machines the coil arrangements in slot is
uniform, therefore, it is possible to predict the parasitics in the motor based on analytical
expressions obtained using the geometry of motor or through FEA packages. However, for
random wound machine it is extremely difficult to predict the parasitics associated with the
motor analytically, due to random arrangement of the stator winding. The results obtained
through FEA may not be accurate.
The Fig. 2.2(a) and Fig. 2.2(b) show the single winding with the parasitic capacitance
accounting turn to turn capacitance and turn to ground capacitance along with stator resistance and core loss modeled as resistor. The net impedance of the winding shown in
Fig. 2.2(a) is as below,
(
Z12
)
s
R 1+
ω

= ( )2 ( z )
 s

s
+
+1
 ωp

Qωp
(2.1)
2.2. High Frequency Behavior of Induction Motor
23
where,
ωp = √
1
LC
Rres
L + RCRres
Qωp =
Similarly the net impedance of the winding shown in Fig. 2.2(b) is as below,
{(
Z1g =
s
ωz
)2
(
s
+
Qz ωz
)
}
+1
( )

(
)
 s 2

s
+
+1
2sCg
 ωp

Qp ωp
(2.2)
where,
1
ωz = √
L(C + Cg )
Qz ωz =
Rres
L + R(C + Cg )Rres
1
ωp = √
L(C + Cg /2)
Qp ωp =
Rres
L + R(C + Cg /2)Rres
It is possible to obtain the value of the parasitics by suitable high frequency response tests
of the motor [26, 27]. The turn to turn and turn to ground distributed parasitics can be
calculated through frequency response of the motor on differential (line) and common mode
(ground) configuration of motor. The ideal impedance bode plot for DM and CM arrangement obtained using (2.1), (2.2) is shown in Fig. 2.3 and Fig. 2.4. The impedance plot
obtained from experimental results can be matched with the impedance plot obtained theoretically from the lumped model. With this approximate value of the parasitic capacitance
can be calculated. The obtained parasitic values are verified with frequency response obtained for different Y and ∆ configurations .
The frequency response of the motor is obtained experimentally for the following reasons,
1. To study the behaviour of motor over different frequency range.
2. To obtain the value of parasitic capacitance associated with the motor.
The behavior of the motor at high frequency is exploited for designing the filter. This helps
in realizing higher order filter with minimum passive elements. For maximum value of dv/dt
24
Chapter 2. Filter Design
Fig. 2.3: Impedance plot for Y connected DM arrangement of stator windings.
the maximum possible ground current magnitude is estimated using the parasitic capacitance
value. Also distributed winding model can be built to study the voltage doubling due to
long cable and transient voltage distribution among first few coils of the stator winding.
2.2.1
HF behavior of IM on Differential Mode
Fig. 2.5 shows the experimental setup for obtaining impedance plot of motor on the differential mode basis. The Fig. 2.5(a) shows the arrangement for ∆- configuration of motor stator
winding. The impedance plot is obtained between two winding terminal U and V with the
third winding terminal W left open. The winding U V and V W are in series connection and
is in parallel with winding U W . Let impedance of each winding be denoted as ZU V , ZV W
and ZU W . Therefore the net impedance for the winding between U W will be,
Z∆ =
ZU W (ZU V + ZV W )
ZU V + Z V W + ZU W
(2.3)
Assuming all the three windings have identical parasitics ZU V = ZV W = ZU W = Z,
Z∆ =
2
Z
3
(2.4)
The DM configuration in Y-connected winding will result in a net impedance of,
ZY
=
1
Z
3
(2.5)
The net impedance of the winding for all other possible DM configuration is shown in
Table. 2.1. The network analyzer is used in obtaining the impedance plot of the motor. The
2.2. High Frequency Behavior of Induction Motor
25
Table 2.1: Net impedance of the winding for different DM configurations with identical
winding assumption
Configuration
Arrangement Net Impedance
Star-I
Z
Star-II
2Z
Star-III
3
Z
2
Star-IV
1
Z
3
Delta-I
Z
2
Delta-II
2
Z
3
26
Chapter 2. Filter Design
Fig. 2.4: Impedance plot for Y connected CM arrangement of stator windings.
Fig. 2.5: Differential Mode test set up for obtaining the impedance plot (a)∆ connected (b)
Y connected.
injected voltage (v) at the terminal and the current (i) through the winding is measured and
fed back to network analyzer terminals B and A respectively as shown in Fig. 2.5. The ratio
B/A gives the impedance plot over different frequencies. The impedance plot for differential
mode ∆ and Y test configuration is as shown in Fig. 2.6 and Fig. 2.7. It can be seen from
the plot that the motor behavior is inductive for certain frequency range and capacitive for
some other frequency ranges. The parasitic capacitance Ct is shown in Table. 2.2 for Y
configuration.
2.2. High Frequency Behavior of Induction Motor
27
Fig. 2.6: Impedance plot obtained using network analyzer for DM delta configuration (indicated in Fig. 2.5 ). Behavior is inductive for frequencies between 50Hz to 30kHz and
capacitive between 60kHz to 100kHz in ∆-configuration.
Fig. 2.7: Impedance plot obtained using network analyzer for DM star configuration (indicated in Fig. 2.5 ). Behavior is inductive for frequencies between 50Hz to 70kHz and
capacitive between 150kHz to 400kHz in Y-configuration.
28
Chapter 2. Filter Design
Table 2.2: The behavior of motor with 100m long cable and parasitic capacitance between
the turns obtained for differential mode configuration for Y connected winding, the leakage
inductance is obtained using no-load and blocked rotor tests
Configuration
Frequency
Behavior
Resonant
Parasitic
Frequency (kHz)
Capacitance
From
To
DM Star-IV
10kHz
100kHz
Inductive
100kHz
1.05nF (Ct )
CM Star
1kHz
70kHz
Capacitive
79kHz
5.37nF (Cg )
2.2.2
HF behavior of IM on Common Mode
Fig. 2.8: Common mode test set up for obtaining the impedance plot (a)∆ connected (b) Y
connected.
Fig. 2.8 show the experimental setup for obtaining impedance plot of IM on the common
mode basis. The Fig. 2.8(a) shows the arrangement for ∆- configuration of motor stator
winding and Fig. 2.8(b) for Y-configuration. The return path for the current is through
ground via parasitic capacitors. Similar to DM configuration the B/A ratio gives the CM
impedance plots. The impedance plot for the test configuration is shown in Fig. 2.9 and
Fig. 2.10.
The impedance of motor along with the long cable for differential mode and common
mode configuration star connected winding is shown in Fig. 2.11 and Fig. 2.12. The parasitic
capacitance estimated is shown in Table. 2.2. The final value of the parasitic capacitors are
selected after comparing the values obtained from the impedance plot of different DM and
CM configurations. These estimates are also provided by the manufacturers on request.
From the parasitics the value of possible ground current can be estimated approximately.
2.2. High Frequency Behavior of Induction Motor
29
Fig. 2.9: Impedance plot obtained using network analyzer for CM delta configuration (indicated in Fig. 2.8 ). Behavior is capacitive for frequencies between 2kHz to 100kHz.
Fig. 2.10: Impedance plot obtained using network analyzer for CM star configuration (indicated in Fig. 2.8 ). Behavior is capacitive between 200Hz to 70kHz in Y-configuration.
30
Chapter 2. Filter Design
Fig. 2.11: Impedance plot of motor along with long cable obtained using network analyzer
for DM star configuration. Behavior is inductive for frequencies between 100Hz to 60kHz.
Fig. 2.12: Impedance plot of motor along with long cable obtained using network analyzer
for CM star configuration. Behavior is capacitive between 1kHz to 60kHz.
2.3. Filter Design
2.3
31
Filter Design
2.3.1
Filter Design Objectives
The design of a high performance ASD has to account the electrical noises introduced by
modern PWM converters. This demands end-to-end solutions, wherein the electrical noises
are minimized with suitable filter topology as an integral part of the ASD system. The
filter has to address both common mode and differential mode components. The design
procedure has to be independent of the load. However, consideration of constraints imposed
by load helps in mitigating the problem effectively by designing customized filters. Further
to address deleterious effects of CMV the presence of AFE rectifier has to be taken into
account and limit the electrical noises generated within the drive system. This adds to the
complexity in designing the filter. The filter design addresses two aspects:
• Elimination of voltage doubling at motor terminal and minimizing common mode current.
• To eliminate the high frequency CMV effects of AFE rectifier on the load and restrict
the electrical switching noise within the ASD system.
2.3.1.1
Design Objectives for Motor Filter
The proposed dv/dt filter based on LC resonant clamp filter topology is as shown in the
Fig. 2.13 at inverter output. The key aspects of this design are:
1. To eliminate the voltage doubling at the motor terminal by varying the dv/dt of applied
voltage.
2. Minimization of common mode current.
3. Reduce the size and cost of the filter such that it can be integrated with the power
circuit of the converter.
The design should be scalable for high power drives without increasing the cost and size
of the filter significantly. To meet the aforementioned constraints a dv/dt filter is used.
The filter addresses both common mode and differential mode noise with modification in
design procedure. The dv/dt filter design, the dv/dt requirement based on the NEMA
MG 1 standard and cable length, resonating frequency selection, peak current in filter and
semiconductor, resulting power loss is used to select the filter component.
32
Chapter 2. Filter Design
2.3.1.2
Design Objectives For Common Mode DC Bus Filter
To address the CMV due to AFE rectifier capacitors are introduced between DC bus positive
rail to ground and negative rail to ground which eliminates common mode voltage [29], [30].
The proposed filter achieves filtering of the high frequency CMV while preventing the low
frequency third harmonic currents from flowing into the ground.
The proposed DC bus common mode filter is shown in Fig. 2.13. The mid-point M of the
DC bus filter is connected to LCL filter neutral N ′ , which is connected to ground through
capacitor CMg . The key design aspects for the proposed common mode filter are:
1. To eliminate the CMV propagation to load side due to AFE operation, thereby eliminating the increase in CMC current.
2. To circulate the switching and lower order harmonic current within the system. This
allows advance PWM techniques to be adopted for AFE operation.
The DC bus common mode filter is explained along with the methods used to select the
filter components.
mode filter, and dv/dt filter at inverters terminal for the motor load.
Fig. 2.13: Schematic of an active front end motor drive with integrated LCL filter for the active front end rectifier, DC bus common
2.3. Filter Design
33
34
Chapter 2. Filter Design
2.4
2.4.1
Principle and Design of dv/dt Filter
Working of dv/dt Filter
The voltage doubling at the motor terminal can be eliminated by decreasing the dv/dt of the
voltage applied at the motor terminal. To avoid the voltage doubling further the rise time
of the applied voltage should be greater than the propagation time of the forward traveling
voltage wave. Based on the length of the cable appropriate rise time is selected in such a
way that it is greater than the propagation time.
Fig. 2.14: Schematic of dv/dt filter shown for R-phase to illustrate the working of the filter
(a) The circuit when the top device conducts (Sr = 1) (b) the circuit when the clamping
diode (D1 ) conducts with top device still in conduction.
Consider the R- phase of the inverter as shown in Fig. 2.13. To illustrate the working of
dv/dt filter the arrangement for R-phase is shown in Fig. 2.14. If the top device conducts
(i.e. Sr = 1) then the voltage across the filter capacitor starts increasing. Also the resonant
current through the capacitor starts to build. When the capacitor voltage exceeds the sum of
DC bus voltage (Vdc ) and snubber capacitor voltage (Vs ), the R-phase top diode D1 clamps
the filter capacitor voltage to Vdc /2 + Vs . The magnitude of snubber voltage is a small
fraction of DC bus voltage. This maintains the capacitor voltage at the desired value and
increases the rise time, thereby decreasing the dv/dt of voltage applied. At this instant the
resonant current is close to maximum value as shown in Fig. 2.15. The dotted line indicates
the resonant waveform without clamping and the solid line indicates with clamping. Due
to conduction of diode D1 , the snubber voltage appears across the filter inductor as shown
in Fig. 2.14(b). The current through the inductor (resonant current) will now decrease at
a constant rate to zero. The moment resonant current falls to zero the diode D1 stops
2.4. Principle and Design of dv/dt Filter
35
conducting. By proper selection of snubber voltage the resonant current RMS value can
be decreased. This reduces the losses in the filter passive components. This is one of the
advantages of proposed modification in dv/dt filter topology. By adopting the snubber
circuit the losses in diodes can be reduced significantly. Similar action takes place when
the bottom device conducts, the voltage is clamped to −(Vdc /2 + Vs ). By designing the LC
resonant clamped filter the exact magnitude of dv/dt can be controlled. NEMA MG-1 part
31 standard specifies the limit for peak voltage of the output that is acceptable for rated line
to line voltage and specifies a limit for dv/dt.
Fig. 2.15: Voltage across dv/dt filter capacitor and current through dv/dt filter inductor.
In dv/dt filters the resonance frequency is placed above the switching frequency in such
a way that it still meets the required dv/dt limit. In this design the resonance frequency of
filter is selected so that the adverse effects of high dv/dt is reduced and motor behavior to
be inductive so that the overall filter can then be studied as an LCL filter configuration on
DM basis.
2.4.2
Design of dv/dt Filter
The design constrains and governing variables are outlined in the Table 2.3. The DC bus
voltage and the load voltage ratings are fixed as per the requirement of the application. The
key design variable available are resonant frequency ωres , resonant current ires , rise time
trise and the overall power loss. Given the length and type of insulation of the cable the
propagation time can be calculated as,
{
tp =
v
1 vlight
=√
L
ϵ
L
}
(2.6)
36
Chapter 2. Filter Design
Table 2.3: Design constraints and governing design variable for dv/dt filter
Constraint Parameter
Mechanical
Electrical
Variables
Cable Length L (m)
Rise time of output voltage
Size of the filter
Resonant frequency
dv/dt (V/µs)
DC bus and Resonant frequency
Total Power loss (W)
Resonant current
DC bus voltage
Voltage rating of the load
Load behaviour at HF
Resonant frequency
The required rise time trise should be greater than propagation time tp in order to avoid
the voltage doubling at motor terminals.
trise = ktp
k> 1
(2.7)
The single phase equivalent circuit along with the motor leakage inductance is as shown
in Fig. 2.16(a) over frequency range where the motor behaviour is inductive and the motor
turn to turn capacitance is shown in Fig. 2.16(b) where the motor behaviour is capacitive as
seen from the differential mode impedance plot of the motor.
Fig. 2.16: Single phase equivalent circuit of dv/dt filter with (a) motor leakage inductance
taken into consideration for frequency ranges were the motor behaves as inductive (b) motor
turn to turn parasitic capacitance into consideration for frequency ranges were the motor
behaves as capacitive
2.4. Principle and Design of dv/dt Filter
37
In order to have an higher attenuation of switching components on line basis the leakage
inductance of the motor can be exploited so that the effective filtering topology can be studied
as a third order LCL filter. This is possible by selecting suitable resonance frequency ωres
in the region were the motor behaviour is inductive. Consider the LCL filter in Fig. 2.16(a),
the expression for voltage across the capacitor and currents are,
diCf
diLf
+ VCf + LCf
+ iCf RCf
dt
dt
diCf
diL
− iCf RCf
= iLl RLl + Ll l − LCf
dt
dt
= iLl + iCf
dVCf
= Cf
dt
Vdc = iLf RLf + Lf
VCf
iLf
iCf
Where RLf is the ESR of filter inductor, RLl is the resistance offered by the motor, RCf , LCf
are the ESR and ESL of the capacitor. simplifying it further,
diLf
dt
= −
(LCf + Ll )
k2
k3
Ll
iLf + iLl − vCf +
vdc
k1
k1
k1
k1
diLl
dt
1
k2 L f
= −
RLf +
Ll
k1
(
dvCf
dt
=
diCf
dt
= (−RLf +
)
(
iLf
1
k3 Lf
RLl +
−
Ll
k1
)
iLl +
LC
Lf
vcf + f vdc
k1
k1
1
1
iLf −
iL
Cf
Cf l
Lf k2
Lf k2
Lf Ll
Ll
)iLf +
iLl +
vCf − vdc
LCf k1
LCf k1
LCf k1
k1
where,
k1 = Lf LCf + Ll (LCf + Lf )
k2 = −[RLf LCf + Ll (RLf + RCf )]
k3 = [Ll RCf − LCf RLl ]
RCf , RLf are the ESR of the filter capacitor and inductor, LCf is the ESL of the filter
capacitor. The above equations is solved using state space method. The required design can
be obtained with fair accuracy considering only the ideal conditions i.e., ignoring the ESR
and ESL. Therefore the non-ideal conditions of the circuit are neglected, the time domain
equations are as following,
{
vCf (t) = Vdc
}
Ll
(1 − cos(ωres t))
Lf + Ll
(2.8)
38
Chapter 2. Filter Design
(
iLf (t) =
(
iLl (t) =
)
(
)
{
1
Ll
sin(ωres t)
Vdc t +
Vdc
Lf + Ll
Lf (Lf + Ll )
ωres
)
{
(
1
sin(ωres t)
Vdc t −
Lf + Ll
ωres
{
iCf (t) = Vdc
sin(ωres t)
Lf ωres
}
(2.9)
)}
(2.10)
}
(2.11)
When the top device of R-phase is ON (Fig. 2.14) diode D1 clamp the filter capacitor
voltage at instant t = trise i.e., when the filter capacitor voltage magnitude reaches Vdc + Vs .
The expression for rise time can be related to the resonant frequency as,
{
trise =
(
1
Vs
cos−1 1 − 1 +
ωres
Vdc
)(
1+
Lf
Ll
)}
(2.12)
The dv/dt of the filter output is expressed as,
{
}
}
d {
Ll
vCf (t) = Vdc ωres
sin(ωres t)
dt
Lf + Ll
(2.13)
Therefore the maximum value of the dv/dt of filter output will be,
(
dv
dt
)
{
= Vdc ωres
max
Ll
Lf + Ll
}
(2.14)
Also the maximum value of the resonant current (iCf = ires ) will be,
{
(ires )max = Vdc
1
Lf ωres
}
(2.15)
Expressing (2.14) and (2.15) in terms of per unit,
(
dv
dt
)
{
= 2πVdc(p.u) ωres(p.u)
max(p.u)
{
(ires(p.u) )max = Vdc(p.u)
Ll(p.u)
Lf (p.u) + Ll(p.u)
1
Lf (p.u) ωres(p.u)
}
(2.16)
}
(2.17)
By selecting the resonant frequency greater than the switching frequency, the value of filter
inductance can be reduced. The other constraint in selection of resonant frequency is to
reduce the value of the filter inductance much lower than the leakage inductance of the
2.4. Principle and Design of dv/dt Filter
39
motor i.e., Lf ≪ Ll . Therefore (2.12), (2.16) and (2.17) can be further simplified as,
trise(p.u) =
(
dv
dt
{
1
−1
2πωres(p.u)
cos
(
Vs(p.u)
1− 1+
Vdc(p.u)
)}
(2.18)
)
= 2πVdc(p.u) ωres(p.u)
(2.19)
max(p.u)
(ires(p.u) )max = Vdc(p.u)
v
u
u Cf (p.u)
t
(2.20)
Lf (p.u)
The design should also adhere to the dv/dt limit imposed by NEMA MG 1 Part 31. The
selection of ωres therefore is one of the crucial task. The constraints in selection of ωres is
summarized below,
1. trise ≫ tp
2. The motor behaviour should be inductive.
3. Lf ≪ Ll
4.
dv
should be less that limit prescribed by NEMA MG Part 31.
dt
Resonant frequency fixes the rise time trise and the maximum dv/dt.
The other important task in the design procedure is to select peak resonant current (2.17).
This value is assumed based on the power loss in filter, clamping circuit, snubber circuit and
in IGBT module. The Fig. 2.18 shows variation of maximum dv/dt w.r.t cable length (L)
for different values of rise time. The power loss including due to high frequency effects in
filter inductor, snubber, clamp diodes is shown in Fig. 2.17. The loss curve is dependent on
the construction of the filter inductor. Suitable value of resonant current based on the total
power loss is selected. The filter inductor and capacitor value are calculated as,
{
Lf (p.u) = Vdc(p.u)
}
1
(ires(p.u) )max ωres(p.u)







(2.21)







2
2πVdc(p.u)
( )
= 

dv






(i
)


max
res(p.u)

dt max(p.u) 
Cf (p.u) =
2
ωres
1
Lf (p.u)
(2.22)
40
Chapter 2. Filter Design
Fig. 2.17: The variation of resonant current and corresponding power loss in filter for
different values of inductor.
The selection of suitable resonant frequency and current is iterative. The filter capacitor
is selected in such a way that its value is greater than the parasitic capacitor Ct shown in
Fig. 2.16(b). The selection of appropriate clamp diode depends on the peak resonant current
and the loss in diode. A snubber circuit is used in the topology to ensure that the losses in
diode is minimized.
2.4. Principle and Design of dv/dt Filter
41
Fig. 2.18: The allowable dv/dt given the cable length with risetime greater than propagation
time of voltage wave and the dv/dt range for which the motor behavior is inductive is
indicated.
2.4.2.1
Design of Snubber Circuit
The resonant current is reduced to zero at a constant rate with the help of snubber circuit.
When the value of resonant current falls zero the diode stops conducting. This reduces the
RMS value of current which in turn leads to reduced losses in clamping diodes. The flow of
load current through the clamp diode is minimized with the help of snubber circuit. As a
result the current rating of clamp diode is much lesser than the load current rating. Fig. 2.19
Fig. 2.19: Current through the filter inductor during switching transient
shows the resonant current during the switching transient. When the diode conducts the
snubber voltage Vs appears across inductor as shown in Fig. 2.14(b) for R-phase. During this
the current falls at a constant rate from peak resonant magnitude to zero. Similar action
takes place when the bottom switch is ON and bottom diode D2 in conduction, the resonant
42
Chapter 2. Filter Design
Fig. 2.20: Current through the clamp during switching transient
current rises at constant rate to zero. The current through the inductor is expressed as,



 iCf + iload
iLf =
−


 iCf (0 ) +
Diode OF F
VLf
t + iload
Lf
Diode ON
(2.23)
The energy stored in the filter inductor is dissipated in the snubber resistance. The
current through the clamp diode is as shown in Fig. 2.20. The fall time t1 is less than the
switching time of the inverter Tsw(inv) and expressed as
(
t1 =
Lf ires(max)
Vs
)
(2.24)
The average current through the diode is,
IDavg
1
=
2
(
ires(max) t1
Tsw(inv)
)
(2.25)
Under normal operating conditions during the zero states (all top or bottom devices are
ON), all top (or bottom) clamp diodes in the filter circuit conducts, then the total average
current through snubber will be three times the average diode current. Therefore the snubber resistance required will be,
Rs =
Vs
3 IDavg
(2.26)
Defining the ratio D1 = t1 /Tsw(inv) , the expression of snubber resistance is rewritten in terms
of per unit.
Rs(p.u)
2
=
3
(
Vs(p.u)
ires(max(p.u)) D1
)
(2.27)
The RMS value of the inductor current depends on the value of the snubber voltage. There-
2.4. Principle and Design of dv/dt Filter
43
fore the snubber voltage is selected as a fraction of DC bus voltage so that the losses are
within the limits and t1 is less than Tsw(inv) . Fig. 2.17 shows the power loss variation w.r.t
filter inductance for designed value of snubber voltage. To select the snubber capacitance the
worst case scenario is considered wherein the entire load current is assumed to flow through
the clamp diode.
(
Es
)
1(
1
Im
2
=
Lf Im
+ Lf
2
2
2
=
)2
(
1
Im
+ Lf
2
2
)2
)
3(
2
Lf Im
4
(2.28)
In terms of per unit,
(
Es(p.u)
) L I2
3(
b b
2
=
Lf (p.u) Im(p.u)
4
Pb Tb
)
(
)
Lb Ib2
3(
2
Lf (p.u) Im(p.u)
=
4
3Ib2 ωb Lb Tb
=
)
)
1 (
2
Lf (p.u) Im(p.u)
8π
(2.29)
Let the allowable variation in snubber voltage be ∆Vs . The entire energy Es is transferred
to the snubber capacitor. Therefore from energy balance the snubber capacitor is calculated
as,
Es =
{
}
1
Cs (Vs + ∆Vs )2 − Vs2
2
}
)
{
1
3(
2
=
Lf Im
Cs (Vs + ∆Vs )2 − Vs2
4
2
Cs
3
=
2
{
2
Lf Im
∆Vs (2Vs + ∆Vs )
}
(2.30)
In terms of per unit,
Cs(p.u)
3
=
2
{
2
Lf (p.u) Im(p.u)
∆Vs(p.u) (2Vs(p.u) + ∆Vs(p.u) )
}
(2.31)
The selection of snubber parameter plays vital role in the filter design as the total loss curve
44
Chapter 2. Filter Design
Fig. 2.21: Power loss in the snubber and clamp diodes for different values of snubber voltage.
varies with appropriate snubber voltage. The power loss in diode and snubber is shown in
Fig. 2.21. From the plot, as the snubber voltage increases the RMS value of the diode current
reduces, therefore the power loss in snubber and the diodes decreases.
The design procedure is summarized as following,
1. Selection of ωres and ires .
2. Verify dv/dt constraints.
3. Calculation of filter parameters Lf and Cf .
4. Design of snubber parameters Rs and Cs .
5. Overall power loss should be within the desired limits.
Fig. 2.18 shows dv/dt required in order to avoid the voltage doubling at the motor terminals for a desired length of the cable. The rise time is chosen greater than the propagation
time. Hence, for a given rise time the resonance frequency is fixed which limits the dv/dt
as per the constraints of design. The upper and lower limit shown indicate the range of
dv/dt corresponding to resonant frequency where the motor behavior is inductive. Fig. 2.17
shows the overall power loss in the filter for different values of resonant current and filter
inductance. It is desirable to have a lower value of filter inductance to attain compact filter
structure. As the filter inductance is decreased the resonant current magnitude increases,
this increases the overall losses. Selection of snubber voltage alters the power loss curve,
therefore power loss has to be computed once the snubber value is fixed.
2.5. Common Mode Circuit of AFE Converter
45
Fig. 2.22: Schematic of PWM rectifier along with DC bus filter and LCL filter
2.5
Common Mode Circuit of AFE Converter
The power circuit can be represented in an equivalent circuit w.r.t the ground. This equivalent circuit is called common mode circuit. The section describes the method of obtaining
common mode circuit for the power converter topology shown in Fig. 2.13. The CM circuit
is used to design the filter on the DC bus that addresses common mode voltage.
Consider the AFE rectifier topology shown in Fig. 2.22. IEEE 519-1992 standard specifies
the limit on the current ripple that is permissible when the converter is connected to grid.
To achieve this either L filter or LCL filter can be used. The value of the inductor used in
L filter is high in order to meet the IEEE specifications. The LCL filter on the other hand
provides higher attenuation and the value of the passive components are small compared
to L filter. The line side LCL filter is designed as per [24] to minimize the current ripple
injection into grid. The common mode filter capacitors are connected to DC bus and the
neutral point M is connected to neutral of LCL filter N ′ . The common mode filter exploits
the presence of the LCL filter to minimize the passive filter components used in the design.
All the filter components designed are assumed to be identical on each phase. The DC bus
filter capacitor are set to be identical, since its practical to have capacitor of identical values
from manufacturing perspective. However, if required this can be altered with ease in the
design.
The impedance offered by heatsink and ground path is neglected. The relation between
grid voltages to pole voltages can be written after neglecting parasitics and Cd − Rd damping
branch as following,
46
Chapter 2. Filter Design
eag = L1
diL2A
diL1a
+ L2
+ VAO + VOg
dt
dt
(2.32)
ebg = L1
diL1b
diL2B
+ L2
+ VBO + VOg
dt
dt
(2.33)
ecg = L1
diL2C
diL1c
+ L2
+ VCO + VOg
dt
dt
(2.34)
Under balanced condition eag + ebg + ecg = 0. Adding (2.32), (2.33), (2.34) leads to the
following set of equations,
d
d
0 = L1 (iL1a + iL1b + iL1c ) + L2 (iL2A + iL2B + iL2C ) + 3VAF E + 3VOg
dt
dt
0 =
L1 d(icom1 ) L2 d(icom2 )
+
+ VAF E + VOg
3
dt
3
dt
where,
(
VAF E =
icom1 =
icom2 =
(
(
(2.35)
VAO + VBO + VCO
3
iL1a + iL1b + iL1c
)
)
iL2A + iL2B + iL2C
)
The currents in the three phases can be written as,
iL2A = iCa + iL1a
(2.36)
iL2B = iCb + iL1b
(2.37)
iL2C = iCc + iL1c
(2.38)
Summing all the currents in three phase leads to the following set of equations
icom2 = icomC + icom1
where,
icomC = iCa + iCb + iCc
(
dVC
= 3C
dt
)
(2.39)
2.5. Common Mode Circuit of AFE Converter
47
The CM voltage on the DC side is,
Vcom(dc) =
VP g + VN g
2
(2.40)
Which can also be written as,
VP g + VN g
2
Vcom(dc) =
(
1 Vdc
Vdc
=
+ VOg + VOg −
2 2
2
Vcom(dc) = VOg
)
(2.41)
The current on DC side is given by,
icom3 = iCy1 + iCy2
= Cy1
dVCy2
dVCy1
+ Cy2
dt
dt
(2.42)
With Cy1 = Cy2 = Cy , VP M = VCy1 and VM N = VCy2 the equations can be further simplified
as,
VP M = VP O + VOM
(2.43)
VP g = VP O + VOM + VM g
VN g = −
=
Vdc
+ VOM + VM g
2
(2.44)
Vdc
+ VOM
2
VM N = −
Vdc
+ VOM
2
 (
icom3 = Cy 
d VCy1 + VCy2
(
= 2Cy
dt
d (VOM )
dt
)

)
(2.45)
48
Chapter 2. Filter Design
Fig. 2.23: The CM circuit for PWM rectifier DC bus and LCL filter (a) without parasitic
capacitor (b) with parasitic capacitors
icom3 = icomC + iMg
icom3 = icomC + CMg
dVCMg
dt
(2.46)
Using (2.35) ,(2.39) ,(2.46) the common mode circuit for AFE rectifier with filter components
is obtained as shown in Fig. 2.23(a). The CM circuit for AFE rectifier with filter components
and parasitic capacitors are shown in Fig. 2.23(b), where Cp1 and Cp2 are common mode
parasitic capacitance of IGBT device to base plate. The details of the parasitic capacitance
and its value can be obtained from the manufacturers datasheet.
2.6
Design of Common Mode Filter for AFE Converter
One of the advantage of AFE rectifier is to boost the DC bus to the desired value. For
better utilization of DC bus the traditional Sine triangle Pulse Width Modulation (SPWM)
technique is replaced with advanced PWM techniques such as Conventional Space Vector
PWM (CSVPWM), bus clamp PWM techniques etc. The carrier based CSVPWM is realized
by adding a third harmonic component to the modulation signal. This techniques yields peak
value of AC voltage that is 15% higher than with SPWM.
The traditional and effective method adopted to eliminate the common mode voltage
and increase the impedance for the ground currents is to use Y-capacitors on DC bus as
shown in Fig. 2.24(a). The common mode circuit for this topology is shown in Fig. 2.24(b).
When advance PWM technique is used for rectifier operation this topology is not preferred
as lower order current harmonics will be injected to ground. This is due to the common
mode component of modulation signal that appears in the CM voltage due to switching
of rectifier. The proposed filter capacitor is shown in Fig. 2.13, wherein the lower order
harmonic components are circulated within the system along with switching components.
2.6. Design of Common Mode Filter for AFE Converter
49
Fig. 2.24: Schematic of (a) PWM rectifier with LCL filter and Y-capacitor on DC bus (traditional method for eliminating CM voltage) (b) The CM circuit of the topology neglecting
the parasitic capacitor.
Also the high frequency components are attenuated by the overall filter structure.
2.6.1
Selection of Filter Capacitor Cy and CMg
In proposed filter topology, common point M is connected to the neutral of LCL filter N ′ and
to bring the potential of M close to ground suitable value of CMg is selected. Fig. 2.23(a)
show common mode circuit with DC bus filter, where Cb = 2Cy and capacitor (CMg ) is
connected between M to ground. To reduce the amount of current injection to the ground
due to CM voltage, a parallel path has to be provided in a manner that some fraction of
the ground current circulates within the system. This parallel path can be achieved by
introducing DC bus filter Cb and CMg .
The common mode circuit for low frequency components can be approximated as shown
in Fig. 2.25. The inductor L2 of line side LCL filter along with the filter Cy acts as low
pass filter for common mode components. This eliminates the need for additional passive
elements to realize the low pass filter. By suitably selecting the corner frequency of the filter
the lower order harmonics and switching frequency component arising due to different PWM
technique adopted is circulated within the system. The transfer function of the low pass CM
filter is obtained as,
50
Chapter 2. Filter Design
Fig. 2.25: Low frequency approximation of common mode circuit with filter.
icom3 (s)
=
VAF E (s)
(
where, Cs =
Ca Cb
Ca + Cb
(
sCs
2
s Lb Cs + 1
)
(2.47)
)
Bode plot for (2.47) is shown in Fig. 2.26 for different values of Cb . The circuit behaves
as a low pass filter with corner frequency ωcom ,
ωcom = √
1
Lb Cs
(2.48)
The cut-off frequency is selected such a way that most of the low frequency components circulate within the system. Also ωcom should be kept within the switching frequency to avoid
amplification of switching harmonics due to resonance. However the resonance due to the
filter needs to be damped on a common mode basis. Active or passive damping techniques
can be adopted for LCL filter. The damping on LCL filter should be such that it addresses
both CM and DM resonance. Active damping is a zero power loss technique, therefore, it is
generally preferred. If active damping is adopted then ωcom should be atleast less than half
the switching frequency. As L1 , C and L2 are designed as per [24], this imposes following
condition,
ωcom(min) <ωcom <
ωsw
2
(2.49)
where,
ωcom(min) = √
1
Lb Ca
Appropriate value of ωcom is selected which yields the filter capacitor (Cy ) value in terms of
LCL filter parameter as,
2.6. Design of Common Mode Filter for AFE Converter
Fig. 2.26: Frequency response plot of







3
Cy = C  (
2 




icom3 (s)
VAF E (s)
1
ωcom
ωcom(min)
)2
51
for different values of Cb .











− 1

(2.50)
The addition of filter capacitor CMg reduces the potential between M and ground, also attenuates the high frequency components. From Fig. 2.23(a) the transfer function IMg (s)/VAF E (s)
is obtained as,
IMg (s)
=
VAF E (s)
(
αCa
s
)
s La Lb s2 β
+
+1
α
α
4
where,
(
α =
(
β =
1
1
1
+
+
Ca Cb Cg Cb Cg Ca
Lb
La La Lb
+
+
+
Ca Cb Cb Cg
)
)
(2.51)
52
Chapter 2. Filter Design
Fig. 2.27: High frequency approximation of common mode circuit with filter.
Fig. 2.28: Frequency response plot of
iMg (s)
VAF E (s)
for different values of CMg .
The bode plot for different values of CMg is shown in Fig. 2.28. From the bode plot it is
clear that at higher frequencies sufficient attenuation is offered by the filter. The second
resonance at higher frequency is due to CMg which needs to be damped. Ideally at high
frequencies the impedance offered by inductances La and Lb are very high, therefore it acts
as open circuit. Fig. 2.27 shows the high frequency equivalent circuit. The voltage would
now divide between the parasitic capacitors Cp1 , Cp2 and filter capacitor CMg as in (2.52).
V Mg
Cp1
=
VAF E
Cp1 + CMg + Cp2
(2.52)
By keeping the value of CMg reasonably high compared to Cp1 and Cp2 , the voltage VMg
2.6. Design of Common Mode Filter for AFE Converter
53
magnitude is reduced. The values of Cy1 , Cy2 and CMg is shown in Table. 2.6. Estimate
of parasitic capacitance from IGBT to case can be obtained form manufactures of IGBT
module, typically in the range of few pico Farad for high power module.
2.6.1.1
Common Mode Circuit of Proposed Topology
The common mode analysis is extended on the inverter side along with the long cable and
the motor. Fig. 2.29 shows the equivalent common mode circuit for the entire topology. The
clamp diodes on the inverter acts as switch bypassing the capacitor Cf for a duration of t1
during switching transient.
Fig. 2.29: Common mode circuit for the entire proposed topology.
The common mode voltage due to AFE rectifier is concealed within the converter. Therefore at the motor terminal the CMV is only due to inverter. The magnitude of ground currents are significantly reduced due to reduced dv/dt of the applied voltage. Due to the CM
filter the motor ground current sees an alternate path through capacitor CMg . The amount
of current circulated between the load and the converter depends on the impedance offered
by the path. As LCL filter inductances La and Lb offers higher impedance at high frequency,
most of the ground current from motor circulates through CMg . This is shown in Fig. 2.30
Fig. 2.30: Common mode circuit for the high frequency CM current on the motor side.
54
2.7
Chapter 2. Filter Design
Design Example
The design is carried out for the parameters shown in Table. 2.5.
1. The length of the cable is L=100m and the permitivity of PVC insulation is ϵ = 3.5,
therefore the propagation time is,
vp =
3 × 108
√
= 1.6 × 108 m/s
ϵ
tp =
100
= 0.6250µs
1.6 × 108
(2.53)
2. The rise should be greater than the propagation time, trise ≫ tp
trise = 10tp
= 6.25µs
(2.54)
3. An estimate of ωres is obtained as following,
ωres =
π
= 251327rad/s.
2 × trise
(2.55)
fres =
251327r/s
= 40000Hz.
2π
(2.56)
The motor behaves inductive between 50 - 100kHz and the resonant frequency is greater
than inverter switching frequency (fsw(inv) = 2.5kHz). Therefore fres = 40kHz is
selected.
2.5kHz < fres < 100kHz
ωres(p.u) = fres /fb = 800p.u
(2.57)
4. The maximum value of dv/dt (2.16) will be,
(
dv
dt
)
= 2π × 800 × 3.3333
max(p.u)
= 16755 p.u or (= 201V /µs)
(2.58)
This number should be within the limits specified by NEMA MG 1 part 31.
5. The resonant current and snubber voltage is selected based on the overall losses. The
values are ires = 0.5ib (= 7A) and Vs = 0.065Vdc (= 52V ). Therefore the filter
2.7. Design Example
55
inductance (2.21) and capacitance (2.22) is calculated,
Lf (p.u) =
2π × (3.3333)2
0.5 × 16755
= 8.33 × 10−3 p.u
Cf (p.u) =
(2.59)
1
(800)2 × 8.33 × 10−3
= 1.8757 × 10−4 p.u
(2.60)
The inductor and capacitor values are finalized as 0.5mH and 33nF respectively.
6. The Vs ≈ 50V , let the variation in snubber voltage allowed be ∆Vs = 25V. The
maximum load current Im is 20A. The snubber resistor (2.27) and capacitor (2.31) is
calculated as,
t1 =
0.5mH × 7A
= 70µs
50V
(2.61)
D1 = 70µs × 2.5kHz = 0.1750
(
Rs(p.u)
)
0.2083
2
=
= 1.59 p.u
3 0.5 × 0.1750
{
Cs(p.u)
8.33 × 10−3 × (1.45)2
3
=
2 0.1042 × (2 × 0.2083 + 0.1042)
= 0.4841 p.u
(2.62)
}
(2.63)
The snubber resistor and capacitor values are fixed to 30Ω and 100µF respectively.
7. The LCL filter passive components are design as per [24]. These values are shown in
Table. 2.6. The DC bus CM filter capacitor selection is illustrated. Minimum common
mode resonance frequency is,
ωcom(min) = √
fcom(min) =
1
2.5mH × 20µF
= 4472rad/s
4472r/s
= 711Hz
2π
(2.64)
(2.65)
The limits on common mode resonance frequency (2.49) will be,
711 < fcom < 5kHz
(2.66)
56
Chapter 2. Filter Design
The value of fcom = 1.4kHz is selected.


Cy =


3
1
× 20µF ( 1.4kHz )

2
− 1
711Hz
= 10.42µF
(2.67)
The value selected for DC bus filter capacitor is Cy1 = Cy2 = 10µF .
8. From the datasheet of IGBT module the parasitic capacitance between chip to case
value is obtained. The approximate values are Cp1 = Cp1 = 4nF . The ratio is selected
such that the voltage across the capacitor CMg is less than 5% of the common mode
voltage.
0.05 =
4nF
8nF + CMg
CMg =
4nF
− 8nF = 72nF
0.05
(2.68)
The value selected is CMg = 100nF i.e around 3.7% of CM voltage .
9. Based on the filter value selected the parameters are recalculated as,
ωres = √
1
= 246183r/s
0.5mH × 33nF
{
trise
(
dv
dt
)
max
(
50V
1
cos−1 1 − 1 +
=
246183r/s
800V
= 7µs
{
)(
6mH
= 800V × 246183r/s
6mH + 0.5mH
= 181.8V /µs
√
(ires )max = 800 ×
= 6.49A
0.5mH
1+
6mH
)}
(2.69)
}
(2.70)
33nF
0.5mH
(2.71)
From (2.69)- (2.71) it is clear that all the required parameter are well within the design
limits. All the designed values for different resonant frequencies are shown in Table. 2.6.
2.7. Design Example
57
Table 2.4: Base Value used for calculations ActualV alue = P erU nit × BaseV alue
Base Parameter Formula
Value
Power
Pb = 3Vb Ib
10kVA
Voltage
Vb
Current
Ib =
Frequency
fb
Impedance
Zb =
Vb
Ib
17.2Ω
Inductance
Lb =
Zb
2πfb
55mH
Capacitance
Cb =
1
2πfb Zb
184µF
240V
Pb
3Vb
13.8A
50Hz
Table 2.5: Parameters for Filter Design
Sl.No. Parameter
Value
1
Cable length (L)
100m
2
Rise time
7µs
2
Resonant Current (ires )
7A
3
Resonant Frequency
4
Worst case dv/dt limit
5
Peak voltage at load terminals limit
6
CM resonance frequency
2kHz <fres < 50kHz
3320V/µs
1291 V
1kHz<fcom < 5kHz
58
Chapter 2. Filter Design
Table 2.6: Designed value of filter parameter
Sl.No Filter Parameter
Per Unit
Actual
1
LCL filter inductance L1
0.0455
2.5mH
2
LCL filter inductance L2
0.0455
2.5mH
3
LCL filter Capacitance Clf
0.1
20µ F
4
LCL resonance frequency fres
20
1kHz
5
DC Bus CM capacitor Cy1 = Cy2
0.05
10µ F
6
DC Bus CM capacitor CMg
0.0005
100nF
7
CM resonance frequency fcom
28
1.4kHz
8
dv/dt filter inductance Lf
0.0083
0.5mH
9
dv/dt filter capacitance Cf
0.0002
33nF
10
dv/dt filter resonance frequency
800
40kHz
11
Maximum dv/dt
16755
201V/µs
12
Resonant current ires
0.5
7A
13
Snubber Capacitor Cs
0.54
100µF
14
Snubber Resistor Rs
2.31
40Ω
15
Snubber Voltage Vs
0.2083
50V
16
Power Loss (due to ires )
0.018
180W
2.8. Summary
2.8
59
Summary
The need for high frequency model of induction motor and method to obtain the parasitic
capacitor are discussed. Results of high frequency test are presented. To reduce the impact
of high dv/dt and eliminate voltage doubling at motor terminals during switching transient,
dv/dt filter is used. An elaborate design procedure outlining the constraints with different
parameters is presented. The need for using a filter on a line-to-line basis and line-to-ground
basis is discussed. Using advanced PWM strategies for controlling PWM rectifier result in
injection of lower order harmonics into ground. Therefore a suitable CM filter topology
is introduced to restrain the electrical noises generated due to PWM rectifier within the
converter. This allows advanced PWM strategies such as CSVPWM, to control the PWM
rectifier without injecting third harmonics in to ground. The common mode circuit for the
proposed topology is analyzed. The filter topology proposed to address common mode noise
uses minimum passive components to achieve the filtering action. The working, design of
the common mode filter is presented. The entire common mode circuit for the proposed
topology is discussed. A design example used that is used to construct the experimental
prototype is illustrated in detail.
60
Chapter 2. Filter Design
Chapter 3
Active Damping
3.1
Introduction
Limiting switching frequency harmonics is one of the important requirements of obtaining a
high performance AFE converters. Simplest among available methods is to use a inductor
between grid and converter. However, to meet the limits set by the standards, large value of
inductance is necessary. This reduces the dynamic performance of the converter. The cost
and size of the inductor makes it less popular. The other alternative is to use LCL filter. It
achieves the limit set by the standards with lower value of the passive components at lower
switching frequency compared to L-filter.
LCL filter with its complex conjugate poles on the imaginary axis (in s-plane) makes the
system marginally stable. Hence this raises stability concerns due to resonance introduced
by LCL filter. To have a stable system the resonance needs to be damped. This can
be achieved using passive or active damping techniques. The passive damping method is
reliable and simple to implement but has drawbacks such as decrease in performance of the
filter, increased losses. Active damping method has advantage of achieving damping with
zero power loss this makes it more attractive. The result of adopting such method is less
reliability compared to passive method, additional sensors are required and implementation
of complex algorithm in control [41–44].
In this section brief analysis of passive damping is covered. The state feedback based
active damping is described along with proper choice of control gain matrix.
3.2
Transfer Function Analysis of LCL Filter
Fig. 3.1 shows LCL filter without damping structure, the voltages, the currents and the
passive elements are indicated. The parasitic capacitance, ESL and ESR of the passive
components are neglected. To understand the behaviour of the LCL filter for different
frequencies the following three transfer function are derived,
61
62
Chapter 3. Active Damping
Fig. 3.1: Single phase equivalent circuit of LCL filter connected between grid and power
converter.
vc (s) L1
1
{
=
(
) }
vi (s) eg =0
L1 + L2
s 2
1+
ωres
iL1 (s) =
vi (s) eg =0
1
(
)2 }
(3.2)
(
)2 }
{
(
)2 }
(3.3)
and Lp =
L1 L2
L1 + L2
s
s (L1 + L2 ) 1 +
ωres
{
s
1+
ω1
iL1 (s) =
vi (s) eg =0
{
(3.1)
s
s (L1 + L2 ) 1 +
ωres
where,
1
ωres(LCL) = √
Lp Clf
1
ω1 = √
L2 Clf
The bode plot of transfer function (3.1), (3.2) and (3.3) is shown in Fig. 3.2, Fig. 3.3 and
Fig. 3.4 respectively. From the transfer function it can be observed that the LCL filter has
three poles, one at the origin of the s-plane and other two complex poles at the jω-axis.
3.3
3.3.1
Passive Damping
Differential Mode Damping
The damping is introduced in LCL filter by adding a resistor. The resistor can be incorporated into filter at different location, in series with inductor or across it or in series with
capacitor. Alternately RC-branch is connected across filter capacitor to achieve passive
3.3. Passive Damping
Fig. 3.2: Frequency plot of transfer function
Fig. 3.3: Frequency plot of transfer function
63
vc (s)
vi (s)
iL1 (s)
.
vi (s)
64
Chapter 3. Active Damping
Fig. 3.4: Frequency plot of transfer function
iL2 (s)
.
vi (s)
Fig. 3.5: Passive damping method with (a) damping resistor in series with the filter capacitor
(b) damping branch Rd − Cd across the filter capacitor.
damping. The two possible methods are shown in Fig. 3.5(a) and Fig. 3.5(b). The transfer
function (3.1) is modified to include the effect of damping resistor shown in Fig. 3.5(a) as,
vc (s)
L1 (1 + sRd Clf )
=
vi (s)
(L1 + L2 ) (s2 Lp Clf + sRd Clf + 1)
(3.4)
Where,
Rd
ζ=
2
√
Clf
Lp
The bode plot of (3.4) is shown in Fig. 3.6. The damping becomes effective as the resistance
is increased, however the performance of the filter reduces and the losses due to resistor increases. This can be overcome by introducing resistor in LCL filter as indicated in Fig. 3.5(b).
The transfer function (3.1) is modified to include the effect of Rd − Cd branch as,
vc (s)
L1 (1 + sRd Cd )
=
3
vi (s)
(L1 + L2 ) (s Lp Cp Cs Rd + s2 Lp Cp + sRd Cd + 1)
(3.5)
3.3. Passive Damping
Fig.
65
3.6: Frequency plot of transfer function
vc (s)
for damping technique shown in
vi (s)
Fig. 3.5(a).
where,
Cp = Clf + Cd
and Cs =
Clf Cd
Clf + Cd
The bode plot of (3.5) is shown in Fig. 3.7, the damping is optimum when the resistance
is equal to the characteristic impedance of the circuit. Beyond this value of resistance
the effectiveness of damping resonance gradually decreases. The effectiveness of damping
structure is shown for different values of resistance in the plot. However, compared to the
method adopted in Fig. 3.5(a) the performance of filter is efficient and the losses are reduced
as the flow of current through the resistor is decreased. The damping resistor value is selected
as,
√
Rd =
Lp
Cp
v{
u
u
= t
β
β+1
}
L2
Cp
(3.6)
where L1 = βL2 .
3.3.2
Common Mode Damping
The damping resistor introduced to address the DM resonance due to LCL filter appears in
the CM circuit as shown in Fig. 3.8. However, this is not always true and depends on the
66
Chapter 3. Active Damping
Fig.
3.7: Frequency plot of transfer function
vc (s)
for damping technique shown in
vi (s)
Fig. 3.5(b).
Fig. 3.8: Passive damping of common mode resonance using (a)Resistance in series with
capacitor (b)series RC network across capacitor
method in which the damping resistor is introduced into topology. Fig. 3.9 illustrates the
importance of the topology adopted to damp the resonance. Two cases are illustrated with
the help of switch S1 . When the switch (S1 ) is closed, the CM circuit for the topology is
shown in Fig. 3.8(b), where Cd(cm) = 3Cd and Rd(cm) = Rd /3. When the switch (S1 ) is open,
only the resonance due to LCL filter is addressed. This leads to an undamped second order
CM low pass filter. The method of inclusion of damping resistor is vital in cases where the
CM filter is present.
The resonance due to addition of capacitor CMg is separately damped using resistor RMg .
The selection of RMg is as following,
RM gd
v
u
u La
=t
CMg
(3.7)
3.3. Passive Damping
67
Consider the case were the S1 is closed, the actual CM damping resistor seen by the res-
Fig. 3.9: The damping technique addresses (a) only DM resonance when S1 is open (b) both
DM and CM resonance when S1 is closed.
onating circuit is,
Rd
(3.8)
3
However the desired value of the CM damping resistor for optimum damping of CM oscilla′
Rdcm =
tions is,
√
Rdcm =
Lb
Ccm
(3.9)
where,
Ccm =
Ca Cb
Ca + Cb
with Cb = αC,
Ccm =
3CαC
3C + αC
(
=
)
3α
C
α+3
(3.10)
Rdcm is expressed in terms of LCL filter parameters as,
√
Rdcm
√
1  α + 3
=
3
α 
L2
C
(3.11)
The ratio of the desired CM damping resistor to the desired DM damping resistor is given
as,
Rdcm
1
=
Rd
3
Let,
1
γ=
3
√
√
(α + 3) (β + 1)
αβ
(3.12)
(α + 3) (β + 1)
αβ
(3.13)
68
Chapter 3. Active Damping
From (3.12) it clear that the common mode resonance is effectively damped if the common
mode resistance is γ times the differential mode resistance. This value of γ depends on the
filter parameter selection. As per the design of filters, α = 1 and β = 1 this leads to,
√
2 2
γ=
= 0.94
(3.14)
3
The CM resistance required to damp the CM resonance is approximately equal to DM
damping resistor. Comparing (3.8) and (3.12) when only differential mode resistance is used,
1
the desired CM resistance is
that of actual CM resistance(3.8). Also, trying to increase
3γ
the CM damping by increasing the DM resistor results in poor differential mode damping
(Fig. 3.7). The excess resistance required to damp the CM oscillations can be incorporated
on the DC bus filter, but this results in increased losses and deteriorated performance of CM
low pass filter.
It is clear that the different approach to damp the oscillations due to LCL filter and
common mode filter is needed. This motivates to use active damping in order to damp
the oscillations effectively. The possible combinations of using active and passive damping
technique together are,
• DM passive damping (S1 closed) and the CM active damping emulates the excess value
of resistance required to damp CM resonance effectively.
• DM passive damping (S1 open) and the CM active damping emulates the resistance
required to damp CM resonance effectively.
• DM and CM active damping.
To increase the reliability of the system both passive and active methods can be used. The
active damping emulates the excess value of resistance required on the CM low pass filter.
In literature different active damping methods are proposed such as lead-lag method, notch
filter, virtual resistor based method and state space method.
3.4
3.4.1
State Space Representation
LCL Filter
Consider the LCL filter shown in Fig. 3.1. The dynamic equations are as followings,
eg = L 1
diL1
+ vc
dt
vc = L2
diL2
+ vi
dt
3.4. State Space Representation
69
C
dvc
= iL1 − iL2
dt
Re-writing the equations as, in terms of
C
dVc
= −ii + ig
dt
L2
dii
= Vc − Vi
dt
L1
dig
= −Vc + eg
dt
(3.15)
The state variables are x1 = vc , x2 = iL2 and x3 = iL1 . The state space representation is as
following,






 0



x˙1


 1

=

x˙2 
 L2



x˙3


 −1

L1
x˙1 =
−x2 x3
+
C
C
x˙2 =
x1
u1
−
L2 L2
x˙3 =
u2
−x1
+
L1
L1
−1
C
0
0

1

C 



 0




x1


 
−1

 
0 
  x2  + 


  L2



x

3





0


0
0 






u
0  1 


u2



1 
(3.16)
L1
Further representing terms of per-unit,


x˙

 1 


 x˙2 


x˙3
pu
 0





 2π
=
 L
 2pu



 −2π

L1pu
−2π
Cpu

2π
Cpu 

0
0
0
0

0








  x1 
 −2π



 x 

  2  +  L2pu




x3


pu





0
0
0
2π
L1pu








u
1




u
2

pu



(3.17)
70
Chapter 3. Active Damping
Fig. 3.10: Low frequency approximate common mode circuit of proposed DC bus CM filter.
The desired outputs are the three states, where y is a 3 × 1 matrix

1 0 0





x1



y =  0 1 0   x2 



x3
0 0 1
(3.18)
The eigen values of the LCL filter are,
|sI − A| = 0
(3.19)
s1 = 0
j
s2,3 = √
3.4.2
Lp C
Common Mode Filter
The low pass filter of the common mode circuit is as shown in Fig. 3.10. The inductance Lb
along with Ca and Cb act as low pass filter. The dynamic equations describing the filter is
as following,
dicom
+ Vccm
dt
dVccm
= Ccm
dt
VAF E = Lb
icom
(3.20)
(3.21)
Also the common mode current circulating with in the system can be approximated as,
icom = ia + ib + ic
(3.22)
where, ia , ib and ic are the phase currents on the converter side.
The net capacitor voltage Vccm can be either estimated from the (3.21) or calculated from
the capacitor voltage as,
3.5. Active Damping Method
71
Vccm = Vca + Vcb
(
Vcb =
)
Ca
Vca
Cb
)
(
Vccm =
1+
Ca
Vca
Cb
(3.23)
Vca and Vcb are the capacitor voltage across CM capacitors Ca and Cb respectively. The state
variables are x˙4 = Vccm and x˙5 = icom , representation in terms of state space,




 0

=


x˙5
 −1
x˙4
Lb
1 


Ccm 

x
4

0

0


+



 1
x5


(
)

 u
3


Lb
The poles of the common mode circuit are located at s = √
3.5
(3.24)
±j
Lb Ccm
Active Damping Method
The state space method is used to damp the resonance. The state matrices are as following,




A=

0
−1
C
1
L2
−1
L1
0
,
0 

0
0
1
C






B=
0
−1
L2
0



,




1 0 0



C= 0 1 0 


0 0 1
(3.25)
The state space based active damping technique is illustrated. The control law is described
and the necessary gain matrix is derived in terms of filter parameters.
3.5.1
State Space Control Law
The purpose of this control law is to allow design of pole location such that the unstable
(or marginally stable ) pole location are brought to stable region with satisfactory dynamic
response. It is advantageous to use state space method when more than one input is involved
or more than one output are sensed i.e. MIMO systems. The control law used is linear
combination of the state variables,
u = − (K1 x1 + K2 x2 + K3 x3 ) = −K × x
(3.26)
72
Chapter 3. Active Damping
where ,
K=
(
)
K1 K2 K3
The general block diagram is as shown in Fig. 3.11.
Fig. 3.11: Block diagram of state space control.
3.5.2
Control Gain Formula
3.5.2.1
LCL Filter
The state space representation is modified as,
ẋ = (A − BK) x
(3.27)
The new eigen value of the system will be,
|sI − A + BK| = 0

0





 (1 + K )
1

(A − BK) = 

L
2




−1

L1
(3.28)

−1
C
1
C 

K2
L2
K3
L2
0
0












Therefore,






 − (1 + K )
1

|sI − A + BK| = det 

L
2




1

L1

−1
C 

1
C
s
(
s−
K2
L2
0
)
−K3
L2
0





=0






3.5. Active Damping Method
73
solving the above determinant leads to characteristic equation given as,
{
1
K2 2
(1 + K1 )
+
a(s) = s −
s +
L2
L2 C
L1 C
}
3
{
(K2 + K3 )
s−
L1 L2 C
}
=0
(3.29)
The current pole of the system are 0, ±jωres . Let the desired pole location be 0, −σ ± jωd ,
√
where σ = ζωres and ωd = ωres 1 − ζ 2 . Then the characteristic equation with new pole
location will be,
s {(s + σ − jωd )(s + σ + jωd )} = 0
2
s=0
α(s) = s3 + 2σs2 + ωres
(3.30)
Equating (3.29) and (3.30) the co-efficient of gain matrix K can be evaluated.
−K2
= 2σ
L2
K2 = −2ζωres L2
(1 + K1 )
1
+
L2 C
L1 C
(3.31)
2
= ωres
1
=
C
(
1
1
+
L1 L2
)
This is possible iff K1 = 0, and,
K2 + K3
=0
L1 L2 C
⇒ K3 = −K2
(3.32)
The unit of gain K2 , K3 is Ohms (Ω). The control law is now expressed as,
u = − (K2 x2 + K3 x3 )
(3.33)
Input u has the dimension of volts (V) and state x2 and x3 have dimension of current (A).
Therefore in terms of per unit,
u × Vbase = −Ibase (K2 x2 + K3 x3 )
⇒ K2pu = K2 ×
Ibase
Vbase
⇒ K3pu = K3 ×
Ibase
Vbase
74
Chapter 3. Active Damping
Further simplifying the gain leads to a general expression in terms of filter parameters expressed as below,
{√
K2pu = −2ζ
}v
u
1+β u
t L2pu
β
Cpu
(3.34)
The gain matrix in per unit is expressed as,

Kpu =  0
3.5.2.2
{√
−2ζ
}v
u
1+β u
t L2pu
β
{√
2ζ
Cpu

}v
u
u
1 + β t L2pu 
β
Cpu
(3.35)
CM Filter
The similar analysis is extended to CM filter active damping. The control and the gain
matrix for CM resonance damping as following,
u3 = − (Kcm1 x4 + Kcm2 x5 )
(3.36)
The state space representation is modified as,
ẋ = (Acm − Bcm Kcm ) x
(3.37)
Where,

 0
Acm


=

 −1
Lb
1 
Ccm 

0

0



 , Bcm = 


 1







(3.38)
Lb
Equating the desired characteristic polynomial with the modified characteristic polynomial
using control law, the control gain matrix is obtained as,
|sI − Acm + Bcm Kcm | = 0

Kcm(p.u) =  0
v

u
u Lb(p.u)

2ζ t
Ccm(p.u)
(3.39)
The implementation of DM and CM damping block diagram is shown in Fig. 3.12(a)
and Fig. 3.12(b). Some of the challenges in implementing the active damping is to extract
the resonant component from the current waveforms which contains switching component,
fundamental component. Also it is difficult to completely eliminate the DC offset introduced
due to sensors and noise introduced due to ADC.
3.5. Active Damping Method
75
(a)
(b)
Fig. 3.12: Schematic of the active rectifer controller and active damping loop for resonance
due to LCL and CM filter. (a) PWM rectifier controller block diagram with active damping.
(b) Active damping block (i = a, b, c).
3.5.2.3
Sampling Technique
The method adopted to eliminate the switching component is shown in Fig. 3.13. The data
is sampled at higher frequency than the switching frequency and then averaged. This type
of filtering is called moving average filter. The Fig. 3.13 illustrates an example where the
data is sample twice the switching frequency and averaged with the previous value. This
eliminates the switching frequency component more efficiently than sampling at switching
frequency.
76
Chapter 3. Active Damping
Fig. 3.13: Triangular carrier with sampling points indicated.
3.6
Analysis in Discrete Time Domain
The voltages and currents are measured to control the power converter using sensors. The
output of these sensors is an analog signal which is converted into binary form using A/D
converters. The digital control has to act upon the samples of the sensed plant output.
The data is sampled by A/D over a fixed duration called sampling time (T) and f = 1/T
(Hz) is called sample rate. However the sampling time period can be variable based on
the application. Since each sampled value is held constant until the next value is available,
compared to continuous signal the average value of the sampled data lag by T/2. Further the
state matrix coefficients vary based on the sampling rate. For better accuracy of the active
damping the analysis is carried out in discrete time domain. CT to DT transformation is
shown and closed form expressions are derived to understand the dependencies of the state
matrices on the filter parameters and the sampling rate.
3.6.1
Discrete Time Representation
The continuous time state space representation can be can be represented in discrete time
domain as,
x[(k + 1)T ] = Φx[kT ] + Γu[kT ]
y[kT ] = Hx[kT ]
(∫
AT
where, Φ = e
,Γ=
T
(3.40)
(3.41)
)
Aη
e
dη B and H=C, using the impulse invariant transformation
0
approach for transforming from continuous time to discrete time.
3.6.2
Closed Form Expression for Φ and Γ
The Φ and Γ are expressed in terms of infinite series. The closed form expression of Φ and
Γ is derived in this section. This helps in designing the active damping controller without
using simulation packages. The need for simulation packages arise for matrices with large
3.6. Analysis in Discrete Time Domain
77
coefficients. In case of LCL filter the state matrix is a 3 × 3 matrix, therefore, the gain
matrix can be analytically calculated. The representation of Φ and Γ using infinite series is
as given below,
Φ = eAT = I + AT +
=
∫
T
Γ=
eAη dηB =
0
∞
∑
(AT )k
k=0
∞
∑
(AT )2 (AT )3
+
+· · ·
2!
3!
(3.42)
k!
Ak T k+1
B
k=0 (k + 1)!
(3.43)
To derive the closed loop form for Φ and Γ consider the following function defined as
f (AT ) = eAT and g(AT ) be a polynomial such that,
g(AT ) = k0 I + k1 (AT ) + k2 (AT )2
(3.44)
The poles of the continuous time characteristic equation are λ = 0, ±jωres .
f (λT ) = eλT
(3.45)
g(λT ) = k0 + k1 (λT ) + k2 (λT )2
(3.46)
f (0) = 1 ⇒ k0 = 1
when
λ = 0,
when
λ = jωres , ejωres T = 1 + k1 (jωres T ) + k2 (jωres T )2
Equating the real and imaginary parts k1 and k2 can be expressed as,
k1 =
sin(ωres T )
ωres T
(3.47)
k2 =
{1 − cos(ωres T )}
(ωres T )2
(3.48)
Substituting the value of k1 and k2 ,
Φ = eAT = k0 I + k1 (AT ) + k2 (AT )2
{
}
{
}
sin(ωres T )
{1 − cos(ωres T )}
= I+
A+
A2
ωres
(ωres )2
(3.49)
= I + α1 A + α2 A 2
(3.50)
78
Chapter 3. Active Damping
where,
{
α1 (T ) =
{
α2 (T ) =
sin(ωres T )
ωres
}
{1 − cos(ωres T )}
(ωres )2
}
From (3.42) and (3.43), Φ and Γ can be related with following equations as,
Φ = I + AT Ψ
Γ = ΨT B
Ψ =
∞
∑
(AT )k
k=0
(k + 1)!
Expressing Γ in terms of Φ,
Γ = A−1 (Φ − I)B
(3.51)
(Φ − I) = α1 A + α2 A2
Γ = A−1 (α1 A + α2 A2 )B
= α1 B + α2 AB
{
}
{
}
sin(ωres T )
{1 − cos(ωres T )}
Γ =
B+
AB
ωres
(ωres )2
Γ = α1 B + α2 AB
3.6.2.1
(3.52)
(3.53)
Expressing Φ and Γ in terms of Filter Parameters
Substituting for A and B in (3.50) and (3.53),

 0




 1

Φ = I + α1 
 L2




 −1
L1
−1
C
0
0

1

C 










0  + α2 













0
(
1
−1 1
+

L1 L2
 C

)
0
0
−1
L2 C
0
1
L1 C
0





1 


L2 C 




−1 
L1 C
3.7. Reduced order estimator

α2
 1− C





Φ=






79
(
1
1
+
L1 L2
)
−α1
C
α1
L2
1−
−α1
L1
α1
C
α2
L2 C
α2
L2 C
α2
L1 C
1−








 −1 



 + α2 
Γ = α1 

 L2 





















α2
L1 C














(3.54)
Also,


1


 L2 C 


 0 


0
0
0

α2 
 L2 C 





 −α1
Γ=
 L
2














(3.55)
0
The desired pole location in z-domain can be related to s-domain as z = esT . The desired
pole location are s1 = 0, s2,3 = −σ ± ωd their value in z-domain is as following,
z1 = 1
z2 = e−σT (cos(ωd T ) + j sin(ωd T ))
z3 = e−σT (cos(ωd T ) − j sin(ωd T ))
Using the control law, the controller gain matrix can be expressed in terms of filter parameters
in discrete time domain.
|zI − Φ + BK| = (z − z1 )(z − z2 )(z − z3 )
3.7
(3.56)
Reduced order estimator
The state feedback method requires sensor equal to the number of state. As compared to
classical control method the sensors required is more. Though here all the states can be
measured using sensors it is desirable to reduce the number of sensors used. This improves
80
Chapter 3. Active Damping
the reliability of the system. In this section, using the closed form expression for the reduced
order observer gain matrix is derived. The grid side current is estimated based on the
converter side current and capacitor voltage. The algorithm is briefly outlined.

x1 [kT ]





x[kT ] = 
x [kT ]
 2











x
[kT
]
a


=

xb [kT ]



x3 [kT ]
Φ11 Φ12 Φ13


Φ =  Φ21

Φ22 Φ23
Φ31 Φ32 Φ33

Γ11


Γ =  Γ12

Γ13
(3.57)



Φaa

=

Φba

Φab

(3.58)
Φbb




Γa


=

Γb
(3.59)
The estimated state is x3 , the entire matrix is divide into measured states and estimated
state as below,



xa [(k + 1)T ]
xb [(k + 1)T ]

 = 


Φaa Φab
Φba Φbb

xa [kT ]
xb [kT ]

+

Γa

Γb
(
)
u[kT ]
(3.60)
xa [(k + 1)T ] = Φaa xa [kT ] + Φab xb [kT ] + Γa u[kT ]
xb [(k + 1)T ] = Φba xa [kT ] + Φbb xb [kT ] + Γb u[kT ]
Φab xb [kT ] = xa [(k + 1)T ] − Φaa xa [kT ] − Γa u[kT ]
(3.61)
The output equation for reduced order observer is represented by (3.61). The estimated
state is represented as,
x̂b [(k + 1)T ] = Φba xa [kT ] + Φbb x̂b [kT ] + Γb u[kT ] + J {y[kT ] − Φab x̂b [kT ]}
(3.62)
The error matrix is represented as,
x̃b [(k + 1)T ] = (Φbb − JΦab )x̃b [kT ]
The characteristic equation of the error matrix is given by,
(3.63)
3.7. Reduced order estimator
81

|zI − Φbb + JΦab | = z − (1 −
= z−
{(
(
α2
) + J1 J2
L1 C
α1 

)
 C 



α2
J1 α1 J2 α2
1−
−
−
L1 C
C
L2 C


α2 
L2 C
(3.64)
)}
(3.65)
By selecting appropriate values of J1 and J2 the pole of the observer can be placed at desired
location. Estimated state is influenced by capacitor voltage if more weight age is given to J1
1
and by inverter current if weightage is on J2 . The ripple in the capacitor voltage (α 2 ) is
fsw
1
less than the inverter current(α
). Hence giving higher weightage to the capacitor voltage
fsw
J2
fsw
may be reasonable constraint. Also,
=
will be an additional constraint used to obtain
J1
fres
observer gain matrix J. The observer pole can be placed at 2-3 times the resonance frequency
to determine J with satisfactory dynamic response of error in estimated state variable.
82
Chapter 3. Active Damping
3.8
Design Example
The designed value of filter parameters and base value is shown in Table. 2.6. Table. 3.1
shows the values of coefficients α1 and α2 for different sampling time. The values of matrices
Φ and Γ for different sampling time are,
Table 3.1: Value of α1 and α2 for different sampling time
Sampling time (T)
α1 (s)
α2 (s)
5kHz
1.5077 × 10−4
1.7472 × 10−8
10kHz
9.3465 × 10−5
4.8355 × 10−9
20kHz
4.9171 × 10−5
1.2396 × 10−9
Table 3.2: Value of Φ and Γ for different sampling time
Sampling frequency f (kHz)
Φ
Γ

5

 0.9504


 0.0197



−0.0197
−2.4585 2.4585 
0.9752
0.0248


0.0248 



0.9752

10

 0.8066


 0.0374



−0.0374
20
0.9033
0.0967


0.0967 



0.9033

−0.0603

 0.0248 






0






0.0197


−4.6733 4.6733   0.0967 

 0.3011


 0.0603




−7.5387 7.5387 
0.6506
0.3494


0.3494 



0.6506




 −0.0374 






0


 0.3494 






0






0.0603
The gain matrix K for different values of damping coefficients is shown in Table. 3.3 for
CT system. If the sampling time of the system is changed then the control gain matrix in
DT system also varies.
3.9. Summary
ζ
3.9
83
Table 3.3: Values of gain matrix coefficients
√
pole (−ζωres ± jωres 1 − ζ 2 ) K1pu
K2pu
K3pu
0.1
−632 ± j6000
0
-0.1832
0.1832
0.2
−1265 ± j5657
0
-0.3664
0.3664
0.3
−1897 ± j5291
0
-0.5496
0.5496
0.4
−2530 ± j4899
0
-0.7327
0.7327
0.5
−3162 ± j4472
0
-0.9159
0.9159
0.6
−3795 ± j4000
0
-1.0991
1.0991
0.7
−4427 ± j3464
0
-1.2823
1.2823
0.8
−5060 ± j2828
0
-1.4654
1.4654
0.9
−5692 ± j2000
0
-1.6486
1.6486
1.0
−6324 ± j0
0
-1.8313
1.8313
Summary
The need for damping resonance on the line-to-line basis due to LCL filter and on lineto-ground basis due to common mode filter is discussed in details. The passive damping
technique is discussed for LCL filter and its effectiveness for different damping resistors
are presented. The demerits of using a passive damping techniques on line-to-line basis to
address common mode resonance is highlighted.
The need for active damping where both DM and CM resonance are present is discussed.
The analysis of state space based active damping is presented with detail discussion on
selection of controller gain. Analytical expressions are derived for the controller gain in
terms of damping coefficient and filter parameter. Analysis is presented both in continuous
and discrete time domain.
84
Chapter 3. Active Damping
Chapter 4
Experimental Results
4.1
Introduction
This chapter presents the experimental work carried out to validate the filter design and the
active damping technique. The experimental test setup is built to verify the filter design
and achieve overall stable operation of the active front end ASD with active damping. The
sections in this chapter covers the working of dv/dt filter and its effectiveness in eliminating
voltage doubling at motor terminal, effectiveness of CM DC bus filter and the active damping
loop.
4.2
Experimental Test Setup
A three phase 10kVA, 415V back to back connected power converter hardware is built in
the lab for experimental verification. One of the converter acts as PWM rectifier and the
other as PWM inverter. The details of the converter parameter is outlined in Table. 4.2.
To test the effectiveness of the filter a 100m long four core Finolex cable is used to connect
the inverter to motor. The cable voltage withstand capacity is 1.1kV and is PVC insulated.
Table. 4.1 shows the summary of the test configurations.
Table 4.1: Reference to different experimental configuration and results
Arrangement
Results
Inverter with diode front end connected to motor with long cable.
Section 4.3
Choke (L-filter) connected at inverter terminal with diode front end.
Section 4.4.1
dv/dt filter operation connected at inverter terminal with diode front end.
Section 4.4.2
Elimination of voltage doubling at motor terminal.
Section 4.4.2.2
CM filter and LCL filter connection on DC bus with AFE converter.
Section 4.5
CM voltage mitigation at motor terminals due to PWM rectifier.
Section 4.6
Active resonance damping due to LCL filter and CM filter.
Section 4.7
85
86
Chapter 4. Experimental Results
Fig. 4.1: (Top to bottom) ch2: line to line voltage VRY (500V/div), ch4: line to line voltage
VU V (500V/div), ch1: ground current Icom (5A/div), time 5µs/div.
4.3
Voltage Doubling at Motor Terminals
The motor is controlled using V/F scheme. The front end used charging DC bus for this
experiment is diode bridge rectifier. The line to line terminal voltage VRY at inverter end,
the line to line terminal voltage VU V at motor end, the ground current Icom is measured as
shown in Fig. 4.1. The applied step voltage is 600V. During the switching transient the line
to line voltage at the motor terminal is 1.25kV and the ground current magnitude is 7A.
4.4
Mitigation Techniques
The proposed dv/dt filter working and its effectiveness is illustrated. One of the popular
techniques to reduce the effect of voltage doubling is to use a choke at the output of inverter.
The result is presented for this configuration and is compared with the dv/dt filter.
Table 4.2: Converter parameters
Paramerter
Value
Grid Frequency
50Hz
PWM rectifier switching frequency
10kHz
DC bus Voltage
700V
PWM inverter switching frequency
2.5kHz
4.4. Mitigation Techniques
87
Fig. 4.2: (Top to bottom) ch4: line to groung voltage at motor terminal VU g (500V/div),
ch3: pole voltage R-phase inverter terminal to mid-point of DC bus VRO (500V/div), ch1:
R-phase current IR (5A/div), ch2: ground current Icom (1A/div), time 25µs/div.
4.4.1
L filter at Inverter Terminals
As a thumb rule design the choke used is about 5% of the rating. This is done in order to
avoid large voltage drop at fundamental frequency. The Fig. 4.2 compares line to ground
voltage (VU g ) at motor terminal with the pole voltage (VRO ) at inverter terminal, also the
R-phase current (IR ) and ground current (Icom ) are shown. The rise time is increased due
to presence of choke. However, there is no precise control over the rise time as it is now
dependent of the resistance of the winding and parasitic capacitance. The voltage doubling
is avoided but the voltage overshoot is 50% this can exceed the limit NEMA MG Part 31.
Selection of choke may not be an effective solution for all type of motor. The ground currents
magnitude is reduced to 800mA. The frequency reference is set to 50Hz. In Fig. 4.3, VU g ,
VRO , IR and Icom is compared over a cycle. In Fig. 4.4, the common mode voltage at the
motor terminal and common mode current is shown when L filter is used.
4.4.2
dv/dt Filter at Inverter Terminals
The working of dv/dt filter is illustrated followed by its effectiveness in eliminating the voltage
doubling at the motor terminal. The DC bus is charged to 700V using PWM rectifier.
88
Chapter 4. Experimental Results
Fig. 4.3: (Top to bottom) ch4: line to groung voltage at motor terminal VU g (500V/div),
ch3: pole voltage R-phase inverter terminal to mid-point of DC bus VRO (500V/div), ch1:
R-phase current IR (5A/div), ch2: ground current Icom (1A/div), time 10ms/div.
Fig. 4.4: Voltage measured at neutral of motor w.r.t ground (Common mode voltage) Vng
(500V/div) and the ground current (0.5A/div), time 100µs/div.
4.4. Mitigation Techniques
89
Fig. 4.5: R-phase pole voltage VRO (250V/div), time 250ns/div. The rise time of the pole
voltage is approximately 200ns.
4.4.2.1
Working of dv/dt Filter
Fig. 4.5 show the R-phase pole voltage switching from -350V to +350V within 250ns. As per
the definition, the rise time is approximately 200ns. Therefore the dv/dt of the output voltage
is 3500V/µs. Fig. 4.6 compares the R-phase pole voltage before and after dv/dt filter. The
theoretically anticipated rise time matches with the experimental results. This validates the
designed rise time of the output voltage. The dv/dt of the inverter output voltage is precisely
arrested at the desired value. Fig. 4.7 shows the transients of the dv/dt filter, VD1 shows
the clamping action the moment VCf reaches 400V. At this instant the resonant current
magnitude is 6.8A. This validates the anticipated transient condition and the desired values
of design parameters. Fig. 4.8 shows the voltage across the snubber voltage Vs . The design
value of Vs is 50V and the experimental value Vs =55V closely matches the designed value.
Fig. 4.9 shows the voltage across the inductor VLf for R-phase and snubber voltage. The
instant diode D1 conducts the snubber voltage comes across the inductor. This makes the
current through the inductor to fall eventually to zero. Fig. 4.10 compares the line voltages
before and after filter, also the current through the inductor and motor current is compared.
Fig. 4.11 and Fig. 4.12 compares the pole voltages before and after filter for all the three
phases.
90
Chapter 4. Experimental Results
Fig. 4.6: ch1: R-phase pole voltage VRO (500V/div), ch3: R-phase dv/dt filter capacitor
output VCf (500V/div), time (2.5µs/div).
Fig. 4.7: (Top to bottom) ch1: R-phase pole voltage VRO (500V/div), ch2: R-phase dv/dt
filter capacitor output VCf (500V/div), ch3: Inductor current Ires (10A/div), ch4: clamp
diode voltage VD1 (500V/div), time 10µ s.
4.4. Mitigation Techniques
91
Fig. 4.8: The snubber voltage Vs (25V/div).
Fig. 4.9: ch1: dv/dt filter inductor voltage VLf (250V/div), ch3: snubber voltage Vs
(250V/div), time 5µ s/div.
92
Chapter 4. Experimental Results
Fig. 4.10: (Top to bottom) ch4: line to line voltage before dv/dt filter VRY (1kV/div), ch1:
line to line voltage after dv/dt filter VU V (1kV/div), ch3: R-phase current before dv/dt filter
ILf (10A/div), ch3: R-phase current after dv/dt filter IU (5A/div), time 10ms/div.
Fig. 4.11: (Top to bottom) Pole voltage for R, Y and B phase before filter(500V/div), time
100µs.
4.5. Common Mode DC Bus Filter
93
Fig. 4.12: (Top to bottom) Pole voltage for R, Y and B phase before filter(500V/div), time
100µs.
4.4.2.2
Effectiveness of dv/dt Filter
Fig. 4.13 compares pole voltage VRO , dv/dt filter capacitor voltage VCf , line to ground
voltage at motor terminal VU g and shows the CM current Icom . At the motor terminal the
voltage doubling is completely eliminated. Also due to decreased dv/dt of output voltage the
magnitude of current injection to ground reduces significantly from 7A to less than 400mA.
Fig. 4.14 shows the VU g and phase voltage at motor terminal VU n . Fig. 4.15 shows VU g ,
load current IU and the ground current Icom . Here the highlighted portion shows that the
R-phase current carries a part of CM current. Similarly, each phase will carry same amount
of the CM current. The phase current carries load current, switching frequency components,
resonant current due to dv/dt filter, CM current due to parasitic coupling to ground, DM
current due to parasitic coupling between each phase. Fig. 4.16 shows the decreased shaft
voltage at the drive end Vsh(DE) due to reduced dv/dt.
4.5
Common Mode DC Bus Filter
The results are present for the traditionally used CM elimination method on DC side and
for the proposed CM elimination technique. Issues faced in adopting traditional method for
a PWM rectifier is pointed out. The results are obtained for SPWM and CSVPWM. This
helps in understanding the need for such modification. Fig. 4.17 shows the boosting DC bus
from 600V to 700V, corresponding no load current and the CM voltage due to three phase
diode bridge rectifier and PWM rectifier. In case of diode bridge rectifier the CM voltage
94
Chapter 4. Experimental Results
Fig. 4.13: (Top to bottom) ch2: pole voltage VRO (500V/div), ch3: pole voltage after dv/dt
filter VCf (500V/div), ch4: line to ground voltage at motor terminal VU g (500V/div), ch1:
ground current Icom (1A/div), time 10µs/div.
Fig. 4.14: (Top to bottom) ch2: pole voltage VRO (500V/div), ch3: line to ground voltage at motor terminal VU g (500V/div), ch4: line to neutral voltage at motor terminal VU g
(500V/div), time 10ms/div.
4.5. Common Mode DC Bus Filter
95
Fig. 4.15: (Top to bottom) ch3: line to neutral voltage at motor terminal VU g (500V/div),
ch1: load current IU (0.5A/div), ch4: ground current Icom (0.5A/div), time 25µs.
Fig. 4.16: (Top to bottom) ch3: line to neutral voltage at motor terminal VU g (500V/div),
ch1: shaft voltage at the Drive End (DE) Vsh(DE) (20V/div), ch4: ground current Icom
(0.5A/div), time 50µs.
96
Chapter 4. Experimental Results
Fig. 4.17: (Top to bottom) ch1: DC bus voltage VDC (500V/div), ch3: No-load current IA
(5A/div), ch4: common mode voltage VOg (500V/div), time 0.5s/div.
has a lower magnitude and is slowly varying, when the boost operation is started the CM
voltage changes in steps of Vdc /3. Fig. 4.18 shows the CM voltage and the ground current
due to PWM rectifier. It can be seen that the common mode current injection to ground
increases significantly during PWM inverter operation as compared to three phase diode
bridge rectifier.
4.5.1
Traditional Method
To illustrate the problem the DC bus is boosted to 300V using PWM rectifier with the help
of auto transformer on the grid side. The Fig. 2.24(a) shows one of the method traditionally
adopted for eliminating CM voltage. For this method, Fig. 4.19 and Fig. 4.20 show CM
voltage VOg , LCL filter neutral point to ground voltage VNg , the current injection into ground
Icom1 for SPWM and CSVPWM. This is not a preferred topology where higher order filter
and advanced PWM techniques are adopted. Both switching and third harmonic current flow
into ground (Icom1 ) due to advanced PWM technique (CSVPWM). Fig. 4.21 and Fig. 4.22
show the FFT of the ground current injected around 150Hz component for SPWM and
CSVPWM. In case of CSVPWM the common mode injected to the modulating signal is
third harmonic, therefore third harmonic current is injected into ground.
4.5. Common Mode DC Bus Filter
97
Fig. 4.18: ch4: common mode voltage VOg (500V/div), ch3: ground current due to PWM
rectifier Icom (0.1A/div), time 25µs/div.
Fig. 4.19: ch1: common mode voltage VOg (50V/div), ch2: LCL filter neutral point to ground
voltage VNg (250V/div), ch4: ground current Icom (2A/div) for SPWM, time 2.5ms/div
98
Chapter 4. Experimental Results
Fig. 4.20: ch1: common mode voltage VOg (50V/div), ch2: LCL filter neutral point to ground
voltage VNg (250V/div), ch4: ground current Icom (2A/div) for CSVPWM, time 2.5ms/div
Fig. 4.21: FFT around 150Hz of ground current injection into ground due to SPWM in case
of traditional CM elimination method.
4.5. Common Mode DC Bus Filter
99
Fig. 4.22: FFT around 150Hz of ground current injection into ground due to CSVPWM in
case of traditional CM elimination method.
4.5.2
Proposed Method
The proposed topology is as shown in Fig. 2.13. The Fig. 4.23 and Fig. 4.24 shows common
mode voltage VOg , voltage across capacitor VMg , common mode current circulating between
LCL filter and DC bus CM filter Icomc , ground current Icom1 for SPWM and CSVPWM.
The current due to CM voltage circulates between LCL filter and DC bus CM filter and
the potential between the LCL filter neutral point to ground is decreased with addition of
capacitor CMg . Fig. 4.25 and Fig. 4.26 show the expanded view. This arrangement circulates
the harmonics and switching current within the system allowing advance PWM technique
to be adopted on the grid side converters. The results validates the effectiveness of the CM
filter.
100
Chapter 4. Experimental Results
Fig. 4.23: ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div), ch4: ground
current Icom1 (0.2A/div) for SPWM, time 10ms/div.
Fig. 4.24: ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div), ch4: ground
current Icom1 (0.2A/div) for SPWM, time 10ms/div.
4.5. Common Mode DC Bus Filter
101
Fig. 4.25: ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div), ch4: ground
current Icom1 (0.2A/div) for SPWM, time 250µs/div.
Fig. 4.26: ch1: common mode voltage VOg (50V/div), ch2:voltage across capacitor CMg
(VMg ) (50V/div), ch3: current circulating within the systemt Icomc (5A/div), ch4: ground
current Icom1 (0.2A/div) for SPWM, time 250µs/div.
102
Chapter 4. Experimental Results
Fig. 4.27: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div.
4.6
CM Voltage at Motor Terminals
In this section results pertaining to the CM voltage appearing at the motor terminal and the
resulting ground currents with and without filter is presented. To demonstrate the issues
with CM voltage the DC bus is boosted to 400V using PWM rectifier with the help of auto
transformer on the grid side. The motor winding is star connected, therefore the neutral
terminal is accessible. In case of delta connected winding a pseudo neutral point can be
created with the help of resistors connected in star.
Fig. 4.27 shows the CM voltage at the neutral of the motor and resulting ground current
with diode bridge rectifier as front end used to charge the DC bus. The CM voltage changes
in steps of Vdc /3, during this transition however there is overshoot. This is seen during the
step changes. Fig. 4.28 shows the CM voltage at the motor terminal due to PWM inverter
riding on the CM voltage due to diode bridge rectifier.
Fig. 4.29 shows the CM voltage and current when PWM rectifier is used as front end
converter. Here the 10kHz CM voltage rides on the 2.5kHz CM voltage and the magnitude
goes to maximum of Vdc . The resulting CM current magnitude also increases.
Fig. 4.30 shows the CM voltage and current with PWM rectifier as front end and CM
DC bus connected. The CM voltage due to PWM rectifier is attenuated by the DC bus
CM filter, this leads to decreased ground currents. The CM voltage seen at motor terminal
due to PWM rectifier is now comparable with that of (Fig. 4.27) for diode bridge rectifier.
In Fig. 4.31 shown enlarged portion of CM voltage, this shows that during transient the
4.6. CM Voltage at Motor Terminals
103
Fig. 4.28: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 1ms/div.
Fig. 4.29: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div.
104
Chapter 4. Experimental Results
Fig. 4.30: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 25µs/div.
overshoot is still present.
Fig. 4.32 shows the CM voltage at motor terminal and resulting ground current with
motor side dv/dt filter connected along with DC bus CM filter and PWM rectifier as front
end. The dv/dt is arrested resulting in reduced ground currents and during the step change
of Vdc /3 the overshoot is eliminated. Fig. 4.33 shows CM voltage with DC bus voltage 700V,
the magnitude of CM current does not increase significantly as the dv/dt is held constant,
further the voltage overshoot during step change of CM voltage is eliminated. This shows
the effectiveness of the filter at the rated voltage.
4.6. CM Voltage at Motor Terminals
105
Fig. 4.31: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div.
Fig. 4.32: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div.
106
Chapter 4. Experimental Results
Fig. 4.33: ch1: common mode voltage appearing between neutral of the winding to ground
Vng (250V/div), ch3: ground current Icom (0.5A/div), time 100µs/div.
4.7
Active Damping using State Space Method
This section covers damping of resonance due to presence of LCL filter termed as DM
resonance and the other due to CM filter termed CM resonance. Both the resonances are
actively damped using state space method. The switching components on the inverter side
current has to be eliminated. To achieve this moving average filter is used. If the converter
side currents has small magnitude of DC offset then they appear in CM current used for
damping calculated as summation of converter side current. This offset needs to be removed.
The active damping is illustrated for damping co-efficient ζ = 0.3.
4.7.1
Effect of Moving Average Filter
To illustrate the efficacy of the filter, result obtained with two point moving average filter is
shown in Fig. 4.34 for converter side current.
4.7.2
Resonance Damping due to LCL filter
Fig. 4.35 shows the LCL filter R-phase capacitor voltage Vclf with no damping. Fig. 4.36
shows the capacitor voltage and the instant at which active damping loop is activated (shown
as step). The resonant component (1kHz) is effectively eliminated.
4.7. Active Damping using State Space Method
107
Fig. 4.34: Converter side current sampled through ADC with and without moving average
filter (5A/div), time 5ms/div.
Fig. 4.35: LCL filter R-phase capacitor voltage Vclf (100V/div), time 5ms/div.
108
Chapter 4. Experimental Results
Fig. 4.36: LCL filter R-phase capacitor voltage Vclf (100V/div), time 5ms/div.
4.7.3
Resonance Damping due to CM Filter
Fig. 4.37 shows the voltage from mid-point of DC bus (O) to ground VOg with and without
passive damping for LCL filter. Even with the passive damping - Rd − Cd network- the oscillations introduced due to low pass filter is not effectively damped, however, the magnitude
reduces as compared to the case without the damping resistor. Fig. 4.38 shows the FFT of
VOg for the two cases (a) with passive damping for LCL filter (b) without any damping.
Fig. 4.39 shows the common mode voltage at the DC side VOg and current at the instant
where the common mode active damping loop is activated (shown as step) for CSVPWM.
The CM resonance is effectively damped. Similar to CSVPWM case, Fig. 4.40 shows the
CM resonance damping for SPWM.
4.7. Active Damping using State Space Method
109
Fig. 4.37: The CM voltage from mid-point of DC bus (O) to ground VOg using CSVPWM
(a) with Rd − Cd passive damping network introduced in the LCL-filter (b) without the
damping resistor.
Fig. 4.38: FFT of CM voltage from mid-point of DC bus (O) to ground VOg using CSVPWM
(a) with Rd − Cd passive damping network introduced in the LCL-filter (b) without any
damping resistor.
110
Chapter 4. Experimental Results
Fig. 4.39: ch1: common mode voltage at the DC side VOg (50V/div), ch2: common mode
current Icom (2.5A/div), time 2.5ms/div
Fig. 4.40: ch1: common mode voltage at the DC side VOg (50V/div), ch2: common mode
current Icom (2.5A/div), time 2.5ms/div
4.8. Summary
4.8
111
Summary
Experimental results illustrating the effectiveness of the filter are presented. The voltage
doubling at motor terminal is eliminated and the ground currents are reduced significantly
during switching transients due to dv/dt filter. By proper choice of snubber voltage Vs the
oscillations resulting due to LC filter can be decreased.
Due to CM DC bus filter the third harmonic current, high frequency currents due to
PWM rectifier are circulated within the converter cabinet. The common mode voltage due
to PWM rectifier is eliminated at the motor terminal resulting in decreased ground currents.
Table. 4.3 shows the peak current magnitude with and without filter.
Table 4.3: The ground current, inverter output voltage dv/dt, voltage between neutral point
M to ground VMg with and without dv/dt filter and CM bus filter.
Vdc (V)
Filter
700
dv/dt
300
Parameter
No Filter
With Filter
Peak Ground Current (A)
7
0.4
Output dv/dt (V/µs)
3500
100
Peak Ground Current (A)
2.5
0.2
Peak Voltage VMg (V)
150
20
CM
The state space based active damping is effective in eliminating the resonance due to
LCL filter and CM filter. The additional resonance due to addition of filter capacitor CMg
is passively damped.
112
Chapter 4. Experimental Results
Chapter 5
Conclusion
5.1
Summary of Present Work
The commercial motor needs a frequent maintenance due to bearing damage and insulation
failure, more so in the case of long cable connected variable speed drive applications. To
understand the reason behind such failure a detail literature survey was conducted, which is
briefly outlined in chapter 1. To address these issues different solutions proposed in literature
was carefully compared.
The LC resonant clamp filter (also referred as dv/dt filter) is selected as suitable topology
with following objectives,
1. To effectively eliminates ill effects introduced due to AFE based ASD with long cable
by modifying the dv/dt of output inverter voltage. At the same time reduces the size
and cost of the filter compared to traditionally available filter solution.
2. Easily scalable to higher power without much increase in cost and size.
However the design procedure of dv/dt filter is not well addressed in literature. This motivated to study the filter parameters more carefully and present a elaborate design procedure
that highlight the constraints. The design exploits the leakage inductance of the motor to
give a better filtering performance.
An integrated topology of filter is proposed were the electrical noise produced by the
entire ASD is restrained within the system. This minimizes the adverse effect on the load
and avoids polluting the grid. With this perspective, common mode analysis of the entire
system is carried out. This method helps in identifying the key parameters that has to be
accounted in order for the load to function without incurring much damage. A common
mode filter is proposed and its design is elaborately presented. The effect of CM voltage due
to PWM rectifier on the motor is mitigated with the CM filter.
One of the draw backs of using higher order filter is the resonance that needs to damped
for stable operation of the system. A state space based active damping technique is adopted
113
114
Chapter 5. Conclusion
to eliminate the resonance on the line basis due to LCL filter and on the line to ground
basis due to CM filter. Also the importance of damping on DM basis and its impact on CM
resonance is highlighted. Possible ways of using both the passive damping and active damping technique is discussed in order to increase the reliability of the system. The procedure
to select the control gain matrix, the relation between damping coefficient and the control
gains are explained both in continuous time and discrete time.
The advantage of the proposed dv/dt filter are
• The precise control over the dv/dt of output voltage, therefore voltage doubling at
motor terminal during transient can be effectively mitigated.
• It is compact and can be placed within the inverter package, no modifications are
required at the motor end.
• Design exploits the leakage inductance of motor such that higher order LCL filter effect
is seen on line basis.
• Addresses both CM and DM components on motor side.
• The PWM rectifier with an LCL grid side filter need only three additional capacitors
for common mode filtering to realize the proposed DC bus CM filter.
• No additional inductive components such as common mode chokes are necessary.
• The filter topology is effective in preventing the third harmonic component currents
from flowing into the ground.
• The filter topology is effective in preventing common mode voltage due to PWM rectifier appearing at the load terminal.
The method to select suitable and design filter can be summarized as following:
1. When the application does not demand a sinusoidal excitation, the filter that are cost
effective and reduces the effects high dv/dt efficiently should be selected.
2. While designing the filter inductor, the DM and CM behavior has to analyzed. As an
example consider three phase choke used as replacement for three individual inductors
in LCL filter application. Due to three phase choke the CM resonance may come close
to switching frequency due to mutual coupling between the windings. This leads to
excitation of CM resonance due to switching components.
3. The constraints imposed by the load and the ASD has to consider while designing filter
for efficient performance of the filter.
5.2. Suggestions for Future Work
5.2
115
Suggestions for Future Work
1. Impact of dv/dt filter on the life of insulation and bearing of motor can be studied.
2. Filter topologies accounting the complete common mode path can be investigated.
Studying the impact of filters on grid to load leads to a generalized design addressing
most of the concerns due to switching power converters.
3. The realization of resonant clamp filter topologies for high power drives using muti-level
converters can be investigated.
4. CM noise can lead to excitation of DM components, this aspect can be investigated.
5. The common mode resonance due to higher order filters can be further studied by
investigating different damping structure for common mode resonance in detail.
116
Chapter 5. Conclusion
Appendix A
Per Unit System
Per Unit System is a normalization procedure which provides a mathematical basis for
analyzing power networks with relative ease and convenience. The advantage of the per unit
method is that we can generalize the design procedure irrespective power levels comparisons
between different filters can be carried out. The design data can be presented in a more
meaningful way and can be easily correlated.
Per unit quantities are calculated as following:
P er − unit quantity =
Actual value of the quantity
Base value of the quantity
(A.1)
The per unit quantity is dimensionless as the base value and actual value have the same
units. Also the base value is a real number, therefore angle of the per unit quantity is same
as the actual quantity. Usually the line to neutral voltage VLN is selected as the base voltage
and the complex power S (3 phase KVA rating) is selected as base power at any arbitrary
point in the power network. The frequency of grid voltage is selected as base frequency.
Vbase = VLN (V )
(A.2)
Pbase = S(3 − ΦKV Arating) (kV A)
(A.3)
fbase = Grid f requency (Hz)
(A.4)
Ibase =
Pbase
(A)
3 × Vbase
(A.5)
Zbase =
Vbase
(Ω)
Ibase
(A.6)
Lbase =
Zbase
(H)
2 × πfbase
(A.7)
117
118
Appendix A. Per Unit System
Cbase =
1
2 × πfbase Zbase
(F )
(A.8)
The per unit value is computed for the actual value as following,
Vp.u =
Vactual
Vbase
(A.9)
Ip.u =
Iactual
Ibase
(A.10)
Zp.u =
Vp.u
Zactual
=
Ip.u
Zbase
(A.11)
Lp.u =
Lactual
Lbase
(A.12)
Cp.u =
Cactual
Cbase
(A.13)
fp.u =
factual
fbase
(A.14)
Though the base parameters are chosen on the AC side, the analysis can be extended
with power converter as voltage transformer. Assuming the turns ratio to be one, the same
base is used on AC and DC side.
Vdc(p.u) =
Vdc
Vbase
(A.15)
Idc(p.u) =
Idc
Ibase
(A.16)
Consider the following base values,
Vbase = 240 V
Pbase = 10 kV A
fbase = 50 Hz
The other base quantities are derived as,
Ibase =
10kV A
= 13.89A
3 × 240V
119
Zbase =
240V
= 17.28Ω
13.89A
Lbase =
17.28Ω
= 55mH
2 × π50Hz
Cbase =
1
= 184µF
2 × π50Hz × 17.28Ω
The power converter ratings are as following,
Paf e = 10kV A
Vaf e = 240V
Iaf e = 13.89A
fsw(inv) = 2.5kHz
fsw(af e) = 10kHz
Vdc = 700V
The power converter ratings in terms of per unit,
Paf e(p.u) =
10kV A
= 1 p.u
10kV A
Vaf e(p.u) =
240V
= 1 p.u
240V
Iaf e(p.u) =
13.89A
= 1 p.u
13.89A
fsw(inv)(p.u) =
2.5kHz
= 50 p.u
50Hz
fsw(af e)(p.u) =
10kHz
= 200 p.u
50Hz
Vdc(p.u) =
700V
= 2.92 p.u
240V
120
Appendix A. Per Unit System
Appendix B
Guideline from NEMA MG Part 31
The usual commercially available motors are designed for rated sinusoidal excitation. However the Adjustable Speed Drive (ASD) output voltage is a non-sinusoidal waveform similar
to a step like function, rich in harmonics with high dv/dt output voltage. This excites the
parasitic coupling of the motor and results in insulation stress.
NEMA MG Part 31 specifies the peak voltage that can be applied at the motor terminal
for safe operation. When operated under nominal conditions, the limit on peak voltage (line
to line) at motors terminals with base rating voltages (line to line) less than 600V is as
following,
Vpeak ≤ 1.1 × 2 ×
√
2 × Vrated
(B.1)
And the rise time (trise ),
trise ≥ 0.1µs
(B.2)
Fig. B.1 shows voltage response at motor terminal for a step input voltage. Vpeak is single
amplitude zero to peak line to line voltage and Vrated is the rated line to line voltage.
Fig. B.1: Voltage response at motor terminal for a step input voltage
121
122
Appendix B. Guideline from NEMA MG Part 31
Appendix C
Experimental Setup
dv/dt Filter
Components Make
Value
Part No.
0.5mH (21Arms)
GX967/64
Inductors
IISc
Capacitor
Epcos
33nF/1.6kV
B32652
Diode
NXP
1500V
BY359-1500
CM DC Bus Filter
Component Make
Capacitor
Value
ADVANCE 10µF/440Vac
Part No.
5104
LCL Filter
Components Make
Inductors
IISc
Capacitor
ADVANCE
Value
Part No.
2.5mH (15Arms)
GX198-64
10µF/440Vac
5104
123
124
Appendix C. Experimental Setup
Power Converter
Component
Make
IGBT Module
Semikron
Value
Part No.
1200V, 104A
SEMiX101GD128Gs
Controller Parameter
Table C.1: Controller Parameter for system ratings indicated in Table. 4.2
Parameter
Value
Current Sensor Gain kcs
0.4V/A
Voltage Sensor Gain kvs
0.0119
Voltage Controller Gain kv
1.5 p.u
Voltage Controller Time Constant τv
0.1678s
Current Controller Gain kc
0.1388 p.u
Current Controller Time Constant τc
4.6ms
PLL Controller Gain kp
0.2745 p.u
PLL Controller Time Constant τp
12.3ms
125
Fig. C.1: Controller block diagram [23] along with active damping loop and proposed filter
topology.
126
Appendix C. Experimental Setup
Fig. C.2: Experimental setup (1) dv/dt filter board - clamp diodes, snubber circuit, CMg
capacitor (2) dv/dt filter inductor (3) CM DC Bus filter capacitor (4) LCL filter
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