Platform Manager 2 Evaluation Board User Guide
EB93 Version 1.0, June 2015
Platform Manager 2 Evaluation Board
Introduction
Thank you for choosing the Lattice Semiconductor Platform Manager 2 Evaluation Board!
The Platform Manager 2 evaluation board is used to demonstrate, evaluate and design using the Platform Manager 2
(LPTM21) device and the Hardware Management Expander (L-ASC10) device. The board is pre-programmed with a
demo design that highlights the features and flexibility of the LPTM21 and L-ASC10 devices. This demo operates on the
board without any other software or hardware as described in the QuickSTART Guide that is included with the board.
However, a more complete evaluation can be accomplished using the I2C demo / debugging software which is available
from the Lattice website. This software and the demo design can be used to evaluate the following features provided by
the Platform Manager 2 devices: Power Management (Power Sequencing, Voltage Monitoring, Trimming, Margining),
Thermal Management (Temperature Monitoring, Fan Control, Power Control) and Control Plane (Reset Control, Fault
Logging). The use of the software with the demo design is fully described in the user guide which is included with the
software zip file: UG59, Platform Manager 2 I2C Demo Design and GUI User’s Guide.
The QuickSTART Guide
Please use the Platform Manager 2 Board QuickSTART Guide to get started. The QuickSTART Guide provides a
“fast path” for working with the Platform Manager 2 evaluation board and the pre-programmed demo. This user’s
guide augments the QuickSTART Guide by providing detailed descriptions of the on board circuits that support
both the demo and customer evaluation designs.
Features
The Platform Manager 2 evaluation board has been designed to demonstrate and evaluate the following applications:
• Supply Voltage monitoring, sequencing, trimming, VID, and control.
• Current sensing, monitoring and control.
• Temperature sensing, monitoring and control.
• 3-Wire, 4 Wire Fan Control.
• Fault logging to internal UFM or external SPI Flash.
• Scalable monitoring and control of voltages, currents, temperatures.
• Field upgrades via background programming and dual boot.
• GPIO control and expansion.
The Platform Manager 2 evaluation board also allows the user to quickly learn, evaluate, develop and test their own
designs using the LPTM21, L-ASC10 and surrounding circuits and components.
The Platform Manager 2 evaluation board contains the following on-board components and circuits to support the
demo design and customer developed designs:
• Integrated Circuits
— LPTM21 – FTBGA-237 – Platform Manager 2 [U1]
— L-ASC10 – QFN-48 – Hardware Expander [U4]
— AT25DF041AMH -SPI Flash Memory [U3]
— FT2232HL- USB Driver [U6]
— 93C46-WMN6TP –EEPROM Memory [U7]
— NCP1117-LDO [U8]
— LD6836-LDO [U9]
— FSA4157 Analog Switch-SPDT [U10, U11]
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Platform Manager 2 Evaluation Board
• Power Supplies, Connections and Switches
— External 12 V Supply Connector –Coaxial Power Jack [J28]
— External 12 V Supply Connector – Two position Terminal [J25]
— External 5 V Supply Connector – Two position Terminal [J12]
— External 3 V Supply Connector – Two position Terminal [J13]
— +5 V to 2.5 V Trim-able DCDC Converter [DCDC3, DCDC7]
— +5 V to 1.2 V Trim-able DCDC Converter [DCDC4, DCDC8]
• LEDs and LCD Display
— Blue USB Power LED [D42]
— Green +3.3 V Power LED [D44]
— Red LPTM21 (U1 ASC) Output LEDs [D3-D12]
— Red LPTM21 (U1 FPGA) Output LEDs[D22-D36]
— Red L-ASC10 (U4) Output LEDs [D13-D21]
— 3-Digit LCD Display [U5]
— Red ASC # 2 Interface Power LED [D39]
— Red ASC # 3 Interface Power LED [D40]
— Green DC-DC # 3 Power LED [D51]
— Green DC-DC # 4 Power LED [D52]
— Green DC-DC # 7 Power LED [D55]
— Green DC-DC # 8 Power LED [D56]
• Switches, Sliders, Buttons, Sensors and Jumpers
— VID_A 8-position DIP Switch [SW6]
— Restart Push Button Switch [SW4]
— Demo control Push Button Switch [SW1-SW3, SW5]
— Slide Potentiometer [R34, R36, R39, R41]
— Temperature Sensor [Q4, Q6, Q7]
— Temperature Sensor [Q5-with artificial load power resistor]
— 3.3 V supply select Jumper [J1, J3, J4]
— Reset select Jumper [J5]
— Fan Supply Select [J6, J8]
— Enable ASC program Jumper [J31, J32]
— MOSFET Drive Select [J30]
— 5 V supply select jumper [J29]
• Connectors and Interfaces
— JTAG connector [J2]
— I2C/SPI connector [J26]
— External FAN connectors [J7, J9, J10, J11]
— Two Position Screw connector for off board load for DCDC3 and DCDC7 [J19, J23]
— Four position screw connector for off board load for DCDC4 and DCDC8 [J20, J24]
— USB B-mini Connector [J16]
— DSUB 25 Expandable Architecture Connectors for ASC Breakout Board [J14, J15]
— Probe and Test Points
• User Prototyping Area
— 12 x 10 through-Hole array with +12 V, +5 V, +3.3 V, and GND buses
— 24 SMD 0805 footprints
— 8 SMD SOT-23 footprints
— 4 SMD 2512 footprints
— 4 SMD SOIC-8 footprints
— 2 SMD SOT-223 footprints
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Platform Manager 2 Evaluation Board
Mechanical Specifications
Dimensions: 7 in. [L] x 6 in. [W] x 1 in. [H]
Environmental Specifications
The evaluation board must be stored between –40 °C and 100 °C. The recommended operating temperature is
between 0 °C and 55 °C.
Electrical Specifications
• 12 V Input +/– 15% @ 50 mA typical.
• 5 V Input +/– 10% @ 110 mA typical.
• 3.3 V Input +/– 5% @ 150 mA typical.
• 12 V Maximum Current 10 A when using an off board supply and load.
• 5 V Maximum Current 10 A when using an off board supply and load.
• 3.3 V Maximum Current 5 A when using an off board supply and load.
Software Requirements
The pre-loaded demo design on the Platform Manager 2 evaluation board can operate without the need to install
any special software and can be powered using any standard USB port. All control and status information is available on the board using switches, push-buttons, potentiometers, LEDs and the LCD display, as described in the
QuickSTART Guide that was mentioned in the introduction. In order to create and program custom designs or program reference or demo designs, Lattice Diamond 3.4 or later software is required along with a corresponding
license. Within Lattice Diamond®, Platform Designer is a custom tool that is used to create, edit, and build Platform
Manager 2 designs.
Platform Designer Tool-Software
The Platform Designer tool provides an integrated design environment that simplifies building and editing Platform
Manager 2 designs. It supports all of the following and more: implement the hardware management algorithm,
check design rules, compile the design, generate stimulus files, simulate the design, assign pins, and finally generate the JEDEC files used to program and configure the device on the circuit board. Platform Designer also supports the importing of an HDL file to integrate other desired functions.
Figure 1. Platform Designer Software
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Platform Manager 2 Evaluation Board
As shown in Figure 1, the Platform Designer tool contains five main sections: Global, Analog, Components, Control, and Build. Each of the five sections is briefly described below.
• Global – ASC Options and Device Options views are used for configuring global settings for the ASC and the
device.
• Analog – Current, Temperature, and Voltage views are used for configuring the built-in monitoring circuits for
these signals.
• Components – Fan Controller, Fault Logger, Hot Swap, and PMBus Adapter views are used to configure and
instantiate built-in IPs for these functions.
• Control – Ports and Nodes and Logic views are used to name and assign I/O for the design; and to develop and/
or import the control logic.
• Build – DRC, Compile, Pin Assignment, Generate Jedec, Generate Stimulus, and Export Configuration Report
buttons are used for checking design rules, and building the design. A summary view shows the usage and consumption of the design resources available.
Platform Manager 2 I2C GUI - Software
The Platform Manager 2 I2C GUI software and User’s Guide can be downloaded from the Lattice website. This software is provided license free and is used to enhance the demo experience and as a hardware debugging tool; the
main interface is shown in Figure 2. The Demonstration buttons are used in conjunction with the default demo. The
Power Management, Thermal Management, and Control Plane Management buttons can be used independently of
the demo and can also be used with customer board designs (provided an FTDI based USB to I2C interface is
used).
Figure 2. Platform Manager 2 I2C GUI Software
Platform Manager 2 Evaluation Board
LPTM21-Platform Manager 2-Device
As shown in Figure 3, the Lattice Platform Manager 2 device is a fast-reacting, programmable logic based hardware management controller. Platform Manager 2 is an integrated solution combining analog sense and control
elements with scalable programmable logic resources. This unique approach allows Platform Manager 2 to integrate Power Management (Power Sequencing, Voltage Monitoring, Trimming and Margining), Thermal Management (Temperature Monitoring, Fan Control, Power Control), and Control Plane functions (System Configuration, I/
O Expansion, etc.) as a single device.
Architecturally, the Platform Manager 2 device can be divided into two sections – Analog Sense and Control and
FPGA. The Analog Sense and Control (ASC) section provides three types of analog sense channels: voltage (nine
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Platform Manager 2 Evaluation Board
standard channels and one high voltage channel), current (one standard voltage and one high voltage) and temperature (two external and one internal).
Each of the analog sense channels is monitored through two independently programmable comparators to support
both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. In addition, each of the current
sense channels provides a fast fault detect (one µs response time) for detecting short circuit events. The temperature sense channels can be configured to work with different external transistor or diode configurations.
The Analog Sense and Control section also provides ten general purpose 5 V tolerant open-drain digital input/output pins that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as
well as for general purpose logic interface functions. In addition, four high-voltage charge pumped outputs
(HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches.
These HVOUT outputs can also be programmed as static output signals or as switched outputs (to support external charge pump implementation) operating at a dedicated duty cycle and frequency.
The ASC section incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each
power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using
the Digital Closed Loop Control mode of the trimming block.
The internal 10-bit A/D converter can be used to measure the voltage and current through the I2C bus. The ADC is
also used in the digital closed loop control mode of the trimming block.
The ASC section also provides the capability of logging up to 16 status records into its nonvolatile EEPROM memory. Each record includes voltage, current and temperature monitor signals along with digital input and output levels.
The ASC section includes an output control block (OCB) which allows certain inputs and control signals a direct
connection to the digital outputs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to connect the fast current fault detect signal to an FPGA input directly. It also supports functions such as Hot Swap with
a programmable hysteretic controller.
The FPGA section contains non-volatile low cost programmable logic of 1280 Look-Up Tables (LUTs). In addition to
the LUT-based logic, the FPGA section features Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), flexible I/Os, and hardened versions of commonly used functions such as SPI controller, I2C controller
and Timer/counter. The FPGA I/Os offer enhanced features such as drive strength control, slew rate control, buskeeper latches, internal pull-up or pull-down resistors, and open-drain outputs. These features are controllable on a
“per-pin” basis.
The power management, thermal management and control plane logic functions are implemented in the FPGA
section of Platform Manager 2. The FPGA receives the analog comparator values and inputs from the ASC section
and sends output commands to the ASC section through the dedicated ASC-interface (ASC-I/F) high-speed, reliable serial channel. The FPGA hardware management functions are implemented using the Platform Designer tool
inside Lattice Diamond software. The Platform Designer tool includes an easy to use sequence and monitor logic
builder tool and a set of pre-engineered components for functions like time-stamped fault logging, voltage by identification (VID), and fan control.
The Platform Manager 2 is designed to enable seamless scaling of the number of voltage, current and temperature
sense channels in the system by adding external Analog Sense and Control (ASC) Hardware Management
Expanders. The algorithm implemented within the FPGA can access and control these external ASCs through the
dedicated ASC-I/F. Larger systems with up to eight ASC devices can be created by using a MachXO2 FPGA in
place of the Platform Manager 2 device. The companion devices are connected in a scalable, star topology to Platform Manager 2 or MachXO2.
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Platform Manager 2 Evaluation Board
The Platform Manager 2 has an I2C interface which is used by the FPGA section for ASC interface configuration.
The I2C interface also provides the mechanism for parameter measurement or I/O control or status. For example,
voltage trim targets can be set over the I2C bus and measured voltage, current, or temperature values can be read
over the I2C bus.
The Platform Manager 2 device can be programmed in-system through JTAG or I2C interfaces. The configuration is
stored in on-chip non-volatile memory. Upon power-on, the FPGA section configuration is transferred to the on-chip
SRAM and the device operates from SRAM. It is possible to update the non-volatile memory content in the background without interrupting the system operation. For additional details please see DS1043, Platform Manager 2
Data Sheet.
Figure 3. Platform Manager 2 Block Diagram
FPGA Section
Analog Sense and Control Section
MOSFET & Digital I/O Drive
(HVOUTs & GPIO)
DC-DC
Converter
Output Control
Block
Current
Sense
ASC
Interface
(ASC-I/F)
Temperature
Sense
Voltage
Sense
ADC
NonVolatile
Fault Log
I2 C
Interface
ADC
FPGA LUTs
1280
(Hardware
Management
Logic)
FPGA
I/O Ports
SPI
JTAG
I2C
Trim & Margin
Control
L-ASC10-Hardware Expander-Device
As shown in Figure 4, The L-ASC10 (Analog Sense and Control - 10 rail) is a Hardware Management (Power, Thermal,
and Control Plane Management) Expander designed to be used with Platform Manager 2 or MachXO2 FPGAs to implement the Hardware Management Control function in a circuit board. The L-ASC10 (referred to as ASC) enables seamless
scaling of power supply voltage and current monitoring, temperature monitoring, sequence and margin control channels.
The ASC includes dedicated interfaces supporting the exchange of monitor signal status and output control signals with
these centralized hardware management controllers. Up to eight ASC devices can be used to implement a hardware management system.
The ASC provides three types of analog sense channels: voltage (nine standard channels and one high voltage channel),
current (one standard voltage and one high voltage), and temperature (two external and one internal) as shown in Figure 2.
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Platform Manager 2 Evaluation Board
Each of the analog sense channels is monitored through two independently programmable comparators to support both
high/low and in-bounds/out-of-bounds (window-compare) monitor functions. The current sense channels feature a programmable gain amplifier and a fast fault detect (<1 µs response time) for detecting short circuit events. The temperature
sense channels can be configured to work with different external transistor or diode configurations.
Nine general purpose 5 V tolerant open-drain digital input/output pins are provided that can be used in a system for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general purpose
logic interface functions. Four high-voltage charge pumped outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches. These HVOUT outputs can also be programmed as static
output signals or as switched outputs (to support external charge pump implementation) operating at a dedicated duty
cycle and frequency.
The ASC device incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed
Loop Control mode.
The internal 10-bit A/D converter can be used to monitor the voltage and current through the I2C bus. The ADC is also used
in the digital closed loop control mode of the trimming block.
The ASC also provides the capability of logging up to 16 status records into the on-chip nonvolatile EEPROM memory.
Each record includes voltage, current and temperature monitor signals along with digital input and output levels.
The dedicated ASC Interface (ASC-I/F) is a reliable serial channel used to communicate with a Platform Manager 2 or a
MachXO2 FPGA in a scalable star topology. The centralized control algorithm in the FPGA monitors signal status and controls output behavior via this ASC-I/F. The ASC I2C interface is used by the FPGA or an external microcontroller for ASC
background programming, interface configuration, and additional data transfer such as parameter measurement or I/O control or status. For example, voltage trim targets can be set over the I2C bus and measured voltage, current, or temperature
values can be read over the I2C bus.
The ASC also includes an on-chip output control block (OCB) which allows certain alarms and control signals a direct connection to the GPIOs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to connect the fast current fault detect signal to an FPGA input directly. It also supports functions like Hot Swap with a programmable hysteretic
controller. For additional details please see DS1042, L-ASC10 Data Sheet.
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Platform Manager 2 Evaluation Board
Figure 4. Hardware Management Expander L-ASC10 Block Diagram
MOSFET &
Digital I/O Drive
Output Control
Block
Current
Sense
ASC
Interface
(ASC-I/F)
Temperature
Sense
Voltage
Sense
ADC
Non Volatile
Fault Log
I2C
Interface
ADC
Trim & Margin
Control
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Platform Manager 2 Evaluation Board
Platform Manager 2 Board Photos
Photographs of the top and bottom of Platform Manager 2 Board are shown in Figure 5 and Figure 6 below. Component location references are relative to the top of the board with the silk screen text in the readable orientation
(as shown in the photo).
Figure 5. Platform Manager 2 Evaluation Board – Top View
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Platform Manager 2 Evaluation Board
Figure 6. Platform Manager 2 Evaluation Board – Bottom View
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Platform Manager 2 Evaluation Board
Platform Manager 2 Board – Architecture Overview
In this section, the Platform Manager 2 evaluation board is described at the top level. It identifies the main hardware components on the board and briefly describes their functions. Because many of these elements are
described in much more detail in the various Operational Description sections that follow, this section is just a short
overview. Refer to the appropriate Operational Description Section for more details on each block. A block diagram
of the overall system architecture of the Platform Manager 2 evaluation board is shown in Figure 7. Not all blocks
are used by the demo but are provided to evaluate other features of the Platform Manager devices.
Figure 7. Platform Manager 2 Evaluation Board – Block Diagram
U6 – FTDI
Supply Options:
USB, +3.3 V, +5 V, +12 V
USB to
JTAG and I2C
SMD and Thru Hole
Prototyping
Area
DC Buck Converter
U3 – SPI
Memory
2 – Slide
Potentiometers
UI
2 – Temperature
Sensors
8 – Position
DIP Switch
4 – Push Button
Switches
LPTM21
FPGA
and
ASC0
4 – Fan
Connectors
3-Digit LCD and
15 + 10 LEDs
4 – DCDC
Supplies
2 – ASC
Interface
Connectors
ASC2 and ASC3
2 – Slide
Potentiometers
2 – Temperature
Sensors
1 – Push Button
Switch
U4
4 – DCDC
Supplies
L-ASC10
ASC1
9LEDs
As discussed earlier the LPTM21 (U1) and L-ASC10 (U4) are the Platform Manager 2 devices that are highlighted
on this board. Both are connected to a variety of input and output circuits that can be used in demos and customer
evaluations.
LPTM21 (U1) is the primary Platform Manager 2 device. It is referred to as ASC0 in this document when discussing the analog features and as LPTM21 or FPGA when the focus is on the programmable logic.
L-ASC10 (U4) is the secondary Platform Manager 2 device that expands the hardware control and monitoring of
LPTM21 (U1).
SPI Memory (U3) is used for Dual Boot and fault logging.
FTDI USB Interface (U6) is used for programming the Platform Manager devices and to access the I2C bus from
USB.
DC Buck Converter is used to power the board from an optional +12 V supply.
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Platform Manager 2 Evaluation Board
Slide Potentiometers are used to demonstrate voltage monitoring; they simulate power supplies and can be used
to generate either over or under voltage faults.
Temperature Sensors are used to demonstrate temperature monitoring.
8-Position DIP Switch interfaces with the FPGA and can be used for a variety of uses.
Push Button Switches are connected to ASC GPIO and FPGA pins for a variety of uses.
Fan Connectors are used with off board fans.
LCD Display is a three digit seven segment display that is connected to the FPGA for a variety of uses.
LED Indicators are distributed to the ASC GPIO pins and some FPGA pins for user defined functions.
DC-DC Supplies can be enabled, monitored, trimmed, and controlled be VID.
ASC Interface Connectors are provided to connect additional ASC Evaluation boards to expand the level of hardware control and monitoring.
Operational Description
Platform Manager 2 evaluation board supports the demonstration of multiple features, the details of which are
described in this part of user guide. Each of the following sections covers a specific Platform Manager 2 feature
with a focus on the associated circuitry and signals. Some sections are independent while others are combined to
implement the complete Platform Manager 2 solution. The operational sections are organized as follows:
• Voltage Monitor
• Temperature Sense
• Current Monitor
• Hot Swap
• Fan Control
• Fault Logging
• Closed Loop Trim
• VID
• Programming and Configuration
• Dual Boot
• 12 V Buck Converter
• Power Supplies
• ASC Interface
• I2C Bus
• Miscellaneous
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Platform Manager 2 Evaluation Board
Voltage Monitor Operation
One of the key features of the Platform Manager 2 device is the ability to accurately monitor Voltages. The evaluation board has four slide potentiometers connected to Voltage Monitor inputs (VMONs). These potentiometers
function as pseudo power supplies for the demo design and for evaluation of Voltage Monitoring. Most of the
VMONs on the evaluation board have a low value series resistors connected to the on board source such as the
DC-DC outputs, on-board supplies, and the potentiometers. These series resistors are only needed for the evaluation board so that the VMON test points can be driven from off-board sources without damage to either the onboard circuits or the off-board source and without the need to modify the board. Table 1 lists the components and
signals associated with Voltage Monitoring.
Table 1. Components and Signals for Voltage Monitoring
Ref. Des.
Schematic
Sheet
R33, R35
6
1 kOhm slider potentiometer: provides a variable Voltage from zero to 3.3 V. Connected to VMON7 and
VMON8 of U1 with a 1 kOhm series resistor.
Series Resistors2
R34, R36
6
1 kOhm resistor.
Slider Potentiometers1
(POT3 and POT4)
R39, R41
6
1 kOhm slider potentiometer: provides a variable Voltage from zero to 3.3 V. Connected to VMON7 and
VMON8 of U4 with a 1 kOhm series resistor.
Series Resistors2
R39, R41
6
1 kOhm resistor.
Series Resistors2
R1, R2, R3, R4,
R6, R7, R8
2
270 Ohm resistor.
R9
2
680 Ohm resistor.
R10, R11, R12
2
100 Ohm resistor.
R13
9
100 Ohm resistor.
Series Resistors
R23, R24, R25,
R26, R28, R29
5
270 Ohm resistor.
Ground Sense Resistors2
R29, R30, R31
5
100 Ohm resistor.
Ground Sense Resistor2
R32
9
100 Ohm resistor.
A0_VMON1 – A0_VMON9
2
ASC0 VMON inputs (9)
A0_GS_VMON1 –
A0_GS_VMON4
2
ASC0 VMON Ground Sense inputs (4) pulled to
ground with 100 Ohm resistors. Can be connected to
low side of a differential source.
A0_HVMON
2
ASC0 High Voltage VMON input.
A1_VMON1 – A1_VMON9
5
ASC1 VMON inputs (9)
A1_GS_VMON1 –
A1_GS_VMON4
5
ASC1 VMON Ground Sense inputs (4) pulled to
ground with 100 Ohm resistors. Can be connected to
low side of a differential source.
A1_HVMON
5
ASC1 High Voltage VMON input.
Component / Signals
Description
Components
Slider Potentiometers1
(POT1 and POT2)
Series Resistor2
Ground Sense Resistors
2
Ground Sense Resistor2
2
Signals
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
2. Not required for customer designs; allows driving test points with an off-board Voltage source without adding or removing components or
damaging on board circuitry.
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Platform Manager 2 Evaluation Board
Figure 8. Voltage Monitor POT Circuits
ASC1
ASC0
+3.3V
+3.3V
R34
1k
POT1
1
R33
1k
R39
1k
POT3
1
R38
1k
POT1 (2)
2
VMON7
3
POT3(5)
2
VMON7
3
+3.3V
+3.3V
POT2
R36
1k
1
R35
1k
POT4
POT2 (2)
2
R40
1k
VMON8
3
R41
1k
1
2
3
POT4(5)
VMON8
The four slide potentiometers shown in Figure 8 provide a variable Voltage source from zero to +3.3 V. POT1 and
POT2 are connected to LPTM21 (U1) while POT3 and POT4 are connected to L-ASC10 (U4).
Temperature Monitor Operation
Another key feature of the Platform Manager 2 device is the ability to sense and monitor temperatures. Each device
can support up to two external temperature sensors and one internal. The external sensors are diode configured
bipolar transistors that are connected to the TMON (temperature monitor) inputs of LPTM21 and L-ASC10 (U1 and
U4). Table 2 lists the components and signals on the Platform Manager 2 evaluation board to demonstrate temperature sensing and monitoring operation.
Table 2. Components and Signals for Temperature Sense and Monitor
Ref. Des.
Schematic
Sheet
Temperature Sensor 1
Q4
9
2N3906 PNP Transistor, Diode-configured (Beta
Compensated) differential temperature sensor. Connected to TMON1 inputs of LPTM21 U1.
Temperature Sensor 2
Q5
9
2N3904 NPN Transistor, Diode- configured (Differential NPN) temperature sensor. Connected to TMON2
inputs of LPTM21 U1.
Temperature Sensor 3
Q6
9
2N3906 PNP Transistor Diode- configured (Beta
Compensated) differential temperature sensor. Connected to TMON1 inputs of L-ASC10 U4.
Temperature Sensor 4
Q7
9
2N3904 NPN Transistor Diode- configured (Differential NPN) temperature sensor. Connected to TMON2
inputs of L-ASC10 U4.
Heater (Pseudo IC)1
R203
9
2.7 Ohm 1 W power resistor is mounted over Q5 for
demo purposes. The amount of heat generated
depends on the output of DCDC4 and the state of
Q43.
Heater Power Switch1
Q43
9
Connects the output of DCDC4 to the heater (R203)
when A0_HVOUT is active.
C1, C2, C24,
C25
2 and 5
150 pF Input filter capacitors for temperature monitoring signals to reject external noise. Located near U1
and U4.
Component / Signals
Description
Components
Sensor Filter Capacitors
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Platform Manager 2 Evaluation Board
Component / Signals
Ref. Des.
Schematic
Sheet
Description
Signals
TEMP_SENSE1P /
TEMP_SENSE1N
2 and 6
Differential temperature sensor inputs to TMON1 of
LPTM21 U1.
TEMP_SENSE2P /
TEMP_SENSE2N
2 and 6
Differential temperature sensor inputs to TMON2 of
LPTM21 U1.
TEMP_SENSE3P /
TEMP_SENSE3N
5 and 6
Differential temperature sensor inputs to TMON1 of
L-ASC10 U4.
TEMP_SENSE4P /
TEMP_SENSE4N
5 and 6
Differential temperature sensor inputs to TMON2 of
L-ASC10 U4.
A0_HVOUT4
2 and 6
HVOUT output from LPTM21 to turn on/off transistor
(Q43) in order to control the current flowing into resistor (R203) which provides temperature for demo purpose.
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
Figure 9. Temperature Monitor Circuits
ASC0
(2,9,12) OUT_DCDC4
R249
100
NDT3055LCT
Q43
(2) A0_HVOUT4
ASC1
TEMP_DEMO
TEMP_SENSE1P (2)
2N3906
Q4
TEMP_SENSE3P (5)
2N3906
Q6
TEMP_SENSE1N (2)
Temperature Sensor 1
TEMP_SENSE3N (5)
Temperature Sensor 3
TEMP_SENSE2P (2)
R203
2.7
1W
TEMP_SENSE4P (5)
Q5
2N3904
Temperature Sensor 2
Q7
2N3904
Temperature Sensor 4
TEMP_SENSE2N (2)
TEMP_SENSE4N (5)
On the Platform Manager 2 evaluation board there are four external temperature sensors as shown in Figure 9.
Two sensors (Q4 and Q5) are connected to LPTM21 (U1) and two sensors (Q6 and Q7) are connected to L-ASC10
(U4). The evaluation board demonstrates two different configurations for the temperature sensors. Q5 and Q7 are
configured as Differential NPN diodes while; Q4 and Q6 are configured as Beta Compensated PNP diodes. The
Beta Compensated PNP configuration is similar to a substrate diode connection and is able to take advantage of
the Platform Manager 2 built-in beta compensation for more accurate temperature monitoring. All of the temperature sensors have filter capacitors connected across the differential signals to improve noise-immunity and they are
located close to the Platform Manager 2 devices (U1 and U4). All of the temperature sensors have test points
nearby to support off-board sensors after the on-board sensor has been removed.
The circuit in Figure 9 shows a power resistor (R203) mounted thermally close to sensor 2 (Q5). This 1-watt power
resistor is a pseudo IC load to demonstrate thermal management in the demo design. The resistor is powered
when both the MOSFET switch (Q43) is biased ON and DCDC4 is enabled. Q43 is turned on when HVOUT4 of
LPTM21 (U1) is turned ON; HVOUT4 needs to be in Charge Pump mode with the following settings: 8 V, 100 uA
source, 3000 uA sink, and static mode. Using the Platform Manager 2 I2C GUI with the demo, the output of DCDC4
16
Platform Manager 2 Evaluation Board
can be adjusted or fan #2 can be controlled (or both) in order to reduce the power and lower the temperature of the
sensor. For details on using the demo and GUI please refer to the Platform Manager 2 I2C Demo Design and GUI
User’s Guide. For additional information regarding temperature monitoring please refer to TN1278, Temperature
Monitoring and Fan Control with Platform Manager 2.
Current Monitoring Operation
Another key feature of the Platform Manager 2 device is the ability to monitor current. Each device has two current
monitoring (IMON) inputs and each input has two pins that connect to an external current sensing resistor. One
current sensing input is designed to monitor current at high voltage (12 V typical) and shares a pin with the high
voltage VMON (HIMONN_HVMON). The second current sensing input is designed to monitor lower voltage (5 V
typical or lower) currents. Table 3 lists the components and signals associated with current monitoring operation on
the Platform Manager 2 board.
Table 3. Components and Signals for Current Monitoring Operation
Ref. Des.
Schematic
Sheet
Current sense resistor
R54
10
20 milli-Ohm ¼ W Resistor for load side current monitoring with IMON1 inputs of LPTM21 (U1).
Current sense resistor
R57
10
20 milli-Ohm ¼ W Resistor for supply side current
monitoring with IMON1 inputs of L-ASC10 (U4).
Isolation Resistor
R261
10
Zero Ohm Resistor isolates the ASC3_IMONP net
from the +3.3 V supply net to support Kelvin layout.
Test Connector1
J31, J32
10
Connect an external load resistor between pin 2 and
ground to provide a measurable current.
Power Switch MOSFET1
Q13, Q14
10
N-Channel Power MOSFET, used to enable power to
loads either on/off or Hot Swap mode.
ASC2_IMONP
ASC2_IMONN
2, 10
The current monitoring signals to LPTM21 (U1) connected across the current sense resistor R54.
ASC3_IMONP
ASC3_IMONN
5, 10
The current monitoring signals to L-ASC10 (U4) connected across the current sense resistor R57.
Component / Signals
Description
Components
Signals
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
Figure 10. ASC0 IMON1 Monitors ASC2 Current and Supports Hot Swap Circuits
+3.3V
(2,3,4,5,6,7,8,9,11,12,13,14,16)
+3.3V
R53
100
TP9
ASC2_+3.3V
Q13
(2) ENABLE_ASC2_3.3V
1
NDT3055LCT
ASC2_+3.3V
(2) ASC2_IMONP
J14
0.020
R54
(2) ASC2_IMONN
C29
330uF
10V
13
25
(8,9,12,14,16) +5V
12
+5V
11
+12V
24
(2) ASC2_3V_SOFTS
(2,8,9,11,13,16) +12V
10
+3.3V
J31
Program J14
2
1
(4,7) LED_14
(2,3,4,5) I2C_SDA
(2,3,4,5) I2C_SCL
9
R172
0
A2_5V_OVERCURRENT_SENSE
21
R173
0
A2_5V_OVERCURRENT_SHUTDOWN
20
R257
22
8
7
19
R258
I2C_WRITE_PROTECT (2,3,5)
18
22
5
LPTM2_RESETb (2,3,5)
17
4
ASC2_WRCLK (3)
3
ASC2_RDAT (3)
2
ASC2_WDAT (3)
16
(4,7) LED_13
8MHz
6
(3) ASC2_RESET
(4,7) LED_12
+11.3V (2,9)
22
(3) ASC2_BOARD_SENSE
(4,7) LED_7
D39
Green
23
R174
R175
0 A2_12V_OVERCURRENT_SENSE
0 A2_12V_OVERCURRENT_SHUTDOWN
15
14
1
CONN DSUB 25-R
17
SM_LED_0603
R55
470
R56
1k
Platform Manager 2 Evaluation Board
The current sense resistor (R54) shown in Figure 10 is used to monitor the current through power switch MOSFET
(Q13). When Q13 is turned on, +3.3 V is supplied to loads both on and off board and R54 is used to monitor the
combined load current. The signals ASC2_IMONP and ASC2_IMONN are connected to R54 using Kelvin connections and differential signaling layout techniques to maximize the current sensing accuracy at the IMON1 inputs of
U1 (sheet 2). The signals are named because they can be used to monitor off board current drawn by the ASC2
interface connector J14.
The N-channel MOSFET (Q13) is controlled by the HVOUT2 of U1 (sheet 2) either on/off control or Hot Swap
based on the design. The gate resistor (R53) is mounted physically close to Q13 to minimize parasitic oscillations.
The programming jumper (J31) by-passes Q13 when installed to support programming ASC2 via J14; the jumper
should be removed for Hot Swap operation.
The on-board loads consist of the following components: C29, D39, R55, and R56. While they provide a path to
ground for Q13 and R54, they are not designed to provide a significant load. Alternatively, an external load resistor
can be attached between pin 2 of J31 and ground to provide a more significant load to be measured. The external
load resistor should draw less than 200 mA when the board is powered by USB and less than 3 A when the board
is powered from a bench supply connected to J12 (sheet 9). The function of LED D39 and bias resistor R55 is to
indicate that +3.3 V is available for the ASC2 interface connector. R56 is designed to discharge the Hot Swap load
capacitor C29 when power is removed. The Hot Swap load capacitor C29 only draws current when it is charging up
which is discussed in the Hot Swap Operation section.
Figure 11. ASC1 IMON1 Monitors ASC3 Current and Supports Hot Swap Circuits
+3.3V
J32
Program J15
R261
1
2
0
(5) ASC3_IMONP
R57
0.020
TP8
ASC3_+3.3V
1
(5) ASC3_IMONN
R58
100
(5) HOTSWAP_ASC3_3.3V
Q14
ASC1
NDT3055LCT
(2) ENABLE_ASC3_3.3V
ASC0
1
2
3
ASC3_+3.3V
C30
330uF
10V
D40
Green
J15
R60
470
R61
1k
13
25
+5V
SM_LED_0603
12
+5V
24
J30
Mosfet Drive Select
+12V
(4,7) LED_11
(4,7) LED_10
+12V
10
+11.3V
22
(3) ASC3_BOARD_SENSE
(2,5) ASC3_3V_SOFTS
11
23
9
R176
0
A3_5V_OVERCURRENT_SENSE
21
R177
0
A3_5V_OVERCURRENT_SHUTDOWN
20
8
7
I2C_SDA
R259
22
19
I2C_SCL
R260
22
18
ASC3_+3.3V
8MHz
I2C_WRITE_PROTECT
6
5
4
16
(4,7) LED_8
(4,7) LED_9
LPTM2_RESETb
17
(3) ASC3_RESET
R178
R179
0
A3_12V_OVERCURRENT_SENSE
0 A3_12V_OVERCURRENT_SHUTDOWN
ASC3_WRCLK (3)
3
ASC3_RDAT (3)
2
ASC3_WDAT (3)
15
14
1
CONN DSUB 25-R
The current sense resistor (R57) shown in Figure 11 is used to monitor the current through the power switch MOSFET (Q14). When Q14 is turned on, +3.3 V is supplied to loads both on and off board and R57 is used to monitor
the combined load current. The signals ASC3_IMONP and ASC3_IMONN are connected to R57 using Kelvin connections and differential signaling layout techniques to maximize the current sensing accuracy at the IMON1 inputs
of U4 (sheet 5). The signals ASC3_IMONP and ASC3_IMONN are named because they can be used to monitor off
board current drawn by the ASC3 interface connector J15. Since R57 is used to monitor the current on the high (or
supply side), a zero Ohm jumper (R261) is used to generate a sensing net that is isolated from the power net. This
separate net supports differential signal layout from the sensing resistor to the IMON inputs.
18
Platform Manager 2 Evaluation Board
The N-channel MOSFET (Q14) can be controlled by either HVOUT3 of U1 (sheet 2) for simple on/off control or
HVOUT3 of U4 (sheet 5) for Hot Swap control, based on the position of a jumper (J30). Hot Swap is only supported
when the current sense and MOSFET control are connected to the same ASC; in this case ASC1 (U4). The gate
resistor (R58) is mounted physically close to Q14 to minimize parasitic oscillations. The programming jumper (J32)
by-passes Q14 when installed to support programming ASC3 via J15; the jumper should be removed for Hot Swap
operation.
The on-board loads consist of the following components: C30, D40, R60, and R61. While they provide a path to
ground for Q14 and R57, they are not designed to provide a significant load. Alternatively, one can attach a load
resistor between pin 2 of J32 and ground to provide a load to be measured. The resistor should draw less than 200
mA when the board is powered by USB and less than 3 A when the board is powered from a bench supply connected to J12 (sheet 9). The function of LED D40 and bias resistor R60 is to indicate that +3.3 V is available for the
ASC3 interface connector. R61 is designed to discharge the Hot Swap load capacitor C30 when power is removed.
The Hot Swap load capacitor C30 only draws current when it is charging up which is discussed in the Hot Swap
Operation section.
Hot Swap Operation
The Hot Swap operation can be demonstrated on the Platform Manager 2 evaluation board using the IMON1 current sense inputs and the HVOUT MOSFET driver outputs. The default demo does not include Hot Swap operation. However, this section is provided for future demos and customer evaluations. Table 4 lists the components and
signals associated with the Hot Swap operation on the Platform Manager 2 evaluation board
Table 4. Components and Signals for Hot Swap Operation
Ref. Des.
Schematic
Sheet
Current sense resistor
R54
10
20 milli-Ohm ¼ W Resistor for load side current monitoring with IMON1 inputs of LPTM21 (U1).
Current sense resistor
R57
10
20 milli-Ohm ¼ W Resistor for supply side current
monitoring with IMON1 inputs of L-ASC10 (U4).
Isolation Resistor
R261
10
Zero Ohm Resistor isolates the ASC3_IMONP net
from the +3.3V supply net to support Kelvin layout.
Gate Resistors
R53, R58
10
100 Ohm Resistor to reduce parasitic MOSFET oscillations on Q13 and Q14.
LED Bias Resistors
R55, R60
10
470 Ohm Resistors to limit the current in LEDs D39
and D40.
MOSFET Switch
Q13
10
N-Channel MOSFET Supply-side hot-swap switch
supplies power to load capacitor C29 and ASC2 interface connector (J14).
MOSFET Switch
Q14
10
N-Channel MOSFET Load-side hot-swap switch supplies power to load capacitor C30 and ASC3 interface
connector (J15).
LEDs
D39, D40
10
LEDs Green, indicate when hot-swap power is on or
programming jumpers are in place.
Load Capacitors1
C29, C30
10
330 uF 10 V Bulk capacitance emulates a hot-swap
load.
Discharge Resistors1
R56, R61
10
1 kOhm Resistor discharges load capacitor between
hot-swaps.
J30
10
J31, J32
10
Component / Signals
Description
Components
Three-Pin Header1
2-Pin Header
1
19
Install jumper to bypass hot-swap circuits and provide
power during programming of ASC2 and/or ASC3.
Platform Manager 2 Evaluation Board
Component / Signals
Ref. Des.
Schematic
Sheet
Description
Signals
ENABLE_ASC2_3.3V
2, 10
HVOUT2 signal from LPTM21 (U1) to control Q13.
Can be used in hot-swap or simply as on/off control.
ENABLE_ASC3_3.3V
2, 10
HVOUT3 signal from LPTM21 (U1) to control Q13.
For use as on/off control when L-ASC10 (U4) is powered down.
HOTSWAP_ASC3_3.3V
5, 10
HVOUT3 signal from L-ASC10 (U4) to control Q14.
Can be used in hot-swap or simply as on/off control.
2, 10
The current monitoring signals to LPTM21 (U1) connected across the current sense resistor R54.
ASC3_IMONN
5, 10
The current monitoring signals to L-ASC10 (U4) connected across the current sense resistor R57.
ASC2_3V_SOFTS
2, 10
Voltage monitoring signal for Hot Swap or sequencing
connected to VMON6 of LPTM21 (U1).
ASC3_3V_SOFTS
5, 10
Voltage monitoring signal connected to VMON9 of
LPTM21 (U1) for sequencing and VMON9 of 
L-ASC10 (U4) for Hot Swap.
ASC2_IMONP
ASC2_IMONN
ASC3_IMONP
ASC2_+3.3V
TP9
10
Hot-swap power bus for ASC2 interface connector
(J14) and loads. Test point on board is labeled with
the signal name.
ASC3_+3.3V
TP8
10
Hot-swap power bus for ASC3 interface connector
(J15) and loads. Test point on board is labeled with
the signal name.
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
There are two Hot Swap circuits provided on the Platform Manager 2 evaluation board; one is controlled LPTM21
U1 and the other is controlled by L-ASC10 U4. The supporting Hot Swap circuitry for U1 is shown in Figure 10 and
for U4 in Figure 11. Neither Hot Swap circuit is used in the default demo but, they are described for future demos
and customer evaluations.
The circuit in Figure 10 illustrates a Supply based Hot Swap with the MOSFET Q13 connected between the supply
and the current sensing resistor R54. The N type MOSFET Q13 is controlled by HVOUT2 of LPTM21 (sheet 2) and
the gate resistor R53 is located physically close to Q13 to reduce turn on oscillations. The signals ASC2_IMONP
and ASC2_IMONN are connected to R54 using Kelvin connections and differential signaling layout techniques to
maximize the current sensing accuracy at the IMON1 inputs of LPTM21 (sheet 2). The signal ASC2_3V_SOFTS
can be used by the Hot Swap function to monitor the load capacitor C29 voltage and is connected to VMON6 of
LPTM21 using R7 (sheet 2). The Hot Swap function monitors the load capacitor C29 voltage for the following reasons: 1) to see that C29 is charging up and there is not a short or open in the circuit, 2) see that C29 has reached
a voltage where a higher current limit can be used, 3) to know when C29 is close to the supply value – Hot Swap is
complete. When Hot Swap is disabled R56 provides a discharge path for C29 to prepare the circuit for a subsequent Hot Swaps. LED D39 and bias resistor R55 gives a visual indication that the Hot Swap process is complete.
The circuit In Figure 11 illustrates a Load based Hot Swap with the MOSFET Q13 connected between the current
sensing resistor R74 and the load. The N type MOSFET Q14 is controlled by HVOUT3 of L-ASC10 (sheet 5) and
the gate resistor R58 is located physically close to Q14 to reduce turn on oscillations. The signals ASC3_IMONP
and ASC3_IMONN are connected to R57 using Kelvin connections and differential signaling layout techniques to
maximize the current sensing accuracy at the IMON1 inputs of L-ASC10 (sheet 5). The signal ASC3_3V_SOFTS is
used by the Hot Swap function to monitor the load capacitor C30 voltage and is connected to VMON9 of L-ASC10
using R28 (sheet 5). The Hot Swap function monitors the load capacitor C30 voltage for the following reasons: 1) to
see that C30 is charging up and there is not a short or open in the circuit, 2) see that C30 has reached a voltage
20
Platform Manager 2 Evaluation Board
where a higher current limit can be used, 3) to know when C30 is close to the supply value – Hot Swap is complete.
When Hot Swap is disabled R61 provides a discharge path for C30 to prepare the circuit for a subsequent Hot
Swaps. LED D40 and bias resistor R60 gives a visual indication that the Hot Swap process is complete.
Note the series resistors R7 (sheet 2) and R28 (sheet 5) are not required for Hot Swap or VMON operation; in a
typical design the VMON input is connected directly to the Voltage source being monitored. The value of the series
resistor (270 Ohms) is a compromise; it is low enough that the voltage sensing accuracy during Hot Swap is not
affected but, it is also high enough that another supply can be connected directly to VMON test point without significant current flowing between the supplies. The function of R7 and R28 is to support prototype circuits that may be
built using the Platform Manager 2 evaluation board without having to remove components or cut traces.
For Hot Swap operation the Platform Designer tool must be used to configure ASC0 and ASC1 (U1 and U4) so that
the HVOUT output is controlled by the status of the IMON1 inputs. This internal connection provides hysteretic control such that the MOSFET is modulated to restrict the current below the IMON1 trip point. If the sensed current is
below the trip point then the MOSFET bias is increased; and if the sensed current exceeds the trip point then the
MOSFET bias is reduced. For additional information please see the Hot Swap Application Note.
Note that for the Hot Swap operation to work properly, no significant off board load should be enabled or attached
to J31 or J32 or the ASC interface connectors J14 and J15. A significant load would draw more than 20% of the Hot
Swap current. Also J30 should be in the ASC1 position.
Fan Control Operation
The Platform Manager 2 evaluation board provides four channels of fan control for a variety of thermal management demos and the kit includes a loose un-mounted 5 V 3-wire fan. Table 5 lists the components and signals
associated with fan control operation of the Platform Manager 2 board.
Table 5. Components and Signals for Fan Control Operation
Component / Signals
Ref. Des.
Schematic
Sheet
Description
Components
5V 3-Wire Fan
Not mounted on the board but, included with the kit
for various demos. Has a 3x1 connector for use with
FAN1 or FAN2.
3x1 Header
J7, J9
8
Headers to connect external 3 Wire fans. (FAN1 and
FAN2). Supports both +5 V and +12 V fans.
6x1 Header
J10, J11
8
Headers to connect external fans (FAN3 and FAN4).
Supports both +5 V and +12 V also 3-wire and 4-wire
fans.
3x1 Header1
J6, J8
8
Headers to select from either +5 V or +12 V supply for
FAN1 and FAN2.
3x1 Header1
J27
8
Provides options to connect various filter capacitors
to the supply pin of FAN1.
High-Side Drive Filter Capacitor2
C69
8
0.22 uF capacitor – Default filter for PWM frequencies
40 kHz or more. No jumper on J27.
High-Side Drive Filter Capacitor2
C74
8
2.0 uF capacitor – Optional filter for PWM frequencies
between 10 kHz and 26 kHz. Jumper pins 2-3 on J27.
High-Side Drive Filter Capacitor2
C75
8
10 uF capacitor – Optional filter for PWM frequencies
below 10 kHz. Jumper pins 1-2 on J27.
NPN Transistor – SOT-23
Q8
8
2N3904 NPN Transistor inverts the FAN1_PWM signal from LPTM21 U1 and shifts the drive level up to
+12 V.
P-Channel MOSFET – SOT-23
Q3
8
IRLML6402 P-Channel MOSFET provides high-side
switching for FAN1 based on the inverted (by Q8)
FAN1_PWM signal.
21
Platform Manager 2 Evaluation Board
Ref. Des.
Schematic
Sheet
Q10, Q11, Q12
8
NDT3055LCT – N-Channel MOSFET provides lowside drive based on PWM signal from LPTM21 U1.
R212, R214,
R228
8
470 Ohm resistor to isolate the MOSFET input capacitance from the LPTM21 I/O bank to minimize ground
and supply bounce. Also suppresses MOSFET turnon oscillations.
R47, R49, R51
8
10k Ohm resistor to keep MOSFETs turned off by
default.
Gate Pull Up Resistor
R44
8
1 kOhm ¼ W Resistor to provide a fast turn-off of Q3.
The power rating is required for operation at +12 V.
Tach Pull Up Resistor
R45, R46, R48,
R50
8
10 kOhm resistor to bias the open-drain tachometer
feedback signal from the fans.
Base Pull Down Resistor
R43
8
10 kOhm resistor to keep Q8 turned off by default.
Base Bias Resistor
R42
8
1 kOhm resistor to limit the current from the LPTM21
U1 output when turning on Q8.
4, 8
The PWM signals to control the fan speed, FPGA output from LPTM21 U1.
4, 8
The Tachometer or fault signal from fan to FPGA
input of LPTM21 U1.
Component / Signals
N-Channel MOSFET – SOT-235
Gate Resistor
Gate Pull Down Resistor
Description
Signals
FAN1_PWM,
FAN2_PWM,
FAN3_PWM,
FAN4_PWM
FAN1_TACH,
FAN2_TACH,
FAN3_TACH,
FAN4_TACH
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
2. Actual values may vary for customer designs; several values are provided to support demonstrations on the evaluation board.
The control circuit shown in Figure 12 for Fan 1 is the most complex fan drive circuit on the board. This is to support a
wide variety of design evaluations. High-side drive is implemented for Fan 1 using Q3 to modulate the supply to the
fan. The FAN1_PWM signal from LPTM21 (U1) is inverted and level shifted by Q8. The low impedance (1 kOhm) of
R44 is needed to turn Q3 off quickly and because of operation at +12 V the ¼ watt package is required. The high-side
drive benefits from having a filter capacitor in the circuit and J27 provides the means to change the filter value based
on the PWM frequency. The PWM frequency is selected in Platform Designer Fan Component view. A jumper needs
to be installed on J6 to select the fan supply voltage. +5 V can be provided by the USB cable to power the included
fan. Alternatively +5 V can be supplied from J12, J14, or J15 (sheets 9 and 10) based on type of evaluation being
done. If a +12 V fan is used the voltage must be supplied from an off-board supply via J28, J25, J14, or J15 (sheets 9
and 10) because +12 V is not generated from the USB +5 V. The 10k pull-up resistor (R45) is connected to +3.3 V to
provide bias for fans that have an open-drain tachometer or fault output and to interface with the LPTM21 (U1) FPGA
inputs.
22
Platform Manager 2 Evaluation Board
Figure 12. Fan 1 PWM Control Circuit
+5V
J6
3
2
1
+12V
FAN 1 Voltage Select
R44
1k
0.25W
R42
1k
Q3
IRLML6402
Q8
2N3904
(4) FAN1_PWM
1
2
3
R43
10k
J7
3
2
1
J27
Fan1_Capacitor
FAN 1
C75
10uF
(2,3,4,5,6,7,9,10,11,12,13,14,16)
C74
2uF
C69
0.22uF
+3.3V
R45
10k
(4) FAN1_TACH
FAN 1 - 3 WIRE HIGH SIDE DRIVE
The control circuit shown in Figure 13 for Fan 2 provides a low-side drive circuit where Q10 modulates the ground
connection to the fan. The signal FAN2_PWM comes from the FPGA output of LPTM21 (U1) through a series
resistor (R212). The series resistor minimizes both the capacitive loading on the LPTM21 outputs and the tendency
for Q10 to oscillate during turn-on; it is located physically close to Q10 on the board. The pull-down resistor R17
keeps the MOSFET Q10 turned off by default. A jumper needs to be installed on J8 to select the fan supply voltage.
+5 V can be provided by the USB cable to power the included fan. Alternatively +5 V can be supplied from J12,
J14, or J15 (sheets 9 and 10) based on type of evaluation being done. If a +12 V fan is used the voltage must be
supplied from an off-board supply via J28, J25, J14, or J15 (sheets 9 and 10) because +12 V is not generated from
the USB +5 V. The 10 kOhm pull-up resistor (R47) is connected to +3.3 V to provide bias for fans that have an
open-drain tachometer or fault output and to interface with the LPTM21 (U1) FPGA inputs.
23
Platform Manager 2 Evaluation Board
Figure 13. Fan 2 PWM Control Circuit
+5V
J8
3
2
1
+12V
FAN 2 Voltage Select
+3.3V
R46
10k
J9
(4) FAN2_TACH
3
2
1
(4) FAN2_PWM
Q10
NDT3055LCT
Fan 2
R212
470
R47
10k
FAN 2 - 3 WIRE LOW SIDE DRIVE
Figure 14. Fans 3 and 4 PWM Control Circuits
+3.3V
+5V
+12V
J10
R48
10k
6
5
4
3
2
1
(4) FAN3_TACH
FAN 3
(4) FAN3_PWM
R214
470
R49
10k
Q11
NDT3055LCT
FAN 3 - 4 WIRE or
3 WIRE LOW SIDE DRIVE
+5V
+12V
(2,9,10,11,13,16) +12V
(9,10,12,14,16) +5V
+3.3V
J11
R50
10k
6
5
4
3
2
1
(4) FAN4_TACH
FAN 4
(4) FAN4_PWM
R51
10k
R228
470
Q12
NDT3055LCT
FAN 4 - 4 WIRE or
3 WIRE LOW SIDE DRIVE
24
Platform Manager 2 Evaluation Board
The control circuits shown in Figure 14 for Fan 3 and 4 provide low-side drive for both fans; Q11 modulates the
ground connection for Fan 3 based on the FAN3_PWM signal and Q12 modulates the ground connection for Fan 4
based on the FAN4_PWM signal. Both signals come from LPTM21 (U1) FPGA outputs and use series resistors of
470 Ohms (R214 and R228) to minimize the capacitive loading. The series resistors are also mounted physically
close to the MOSFETs (Q11 and Q12) to minimize parasitic oscillations. Both circuits have 10 kOhm pull-down
resistors to keep the MOSFETs turned off by default. Unlike Fans 1 and 2 there is not a separate jumper to select
the fan supply voltage; both the +5 V and +12 V supplies are available on the six-pin headers (J10 and J11) so that
the fan connector can be wired to select the supply voltage. The six-pin headers also provide the PWM signals
directly on pin three to support 4-wire fans. Both fan circuits have 10 kOhm pull-up resistors to +3.3 V on the TACH
signals to support fans with open-drain tachometer outputs and to interface with the LPTM21 (U1) FPGA inputs.
The Platform Designer tool has a configurable Fan Controller component which can be implemented within the
LPTM21 (U1). The fan controller can be configured to work with 2-wire, 3-wire, or 4-wire fans, and a maximum of
sixteen fans can be controlled. The fan controller IP generates a pulse width modulated (PWM) signal, which is
used to control the speed of the fan. It also monitors the tachometer input from the fan to detect a faulty condition.
For additional information regarding fan control please refer to TN1278, Temperature Monitoring and Fan Control
with Platform Manager 2.
Fault Logging Operation
One of the main features of any Platform Manager is the ability to log faults in non-volatile memory for later retrieval
and analysis. The Platform Manager 2 evaluation board supports three methods of fault logging: 1) internal LASC10 storage only, 2) internal LPTM21 storage, and 3) external storage in SPI flash memory. The board also provides hold-up circuits so the Platform Manager 2 has time to log faults in the event of a primary supply failure.
Table 6 lists the components and signals associated with Fault Logging operation of the Platform Manager 2 evaluation board.
Table 6. Components and Signals for Fault Logging OperationComponents and Signals for Fan Control
Operation
Ref. Des.
Schematic
Sheet
4 MB Flash Memory
U3
3
SPI Flash memory to store Fault log data from
LPTM21. LPTM21 has built-in SPI master which
enables data transfer. This is the same memory that
is used for Dual Boot.
5 V Blocking Diode
D41
15
Schottky Diode. Prevents external loads or supply
from draining the hold-up capacitor.
5 V Passing Diode
D43
15
Schottky Diode. Allows the hold-up capacitor to provide full current to down-stream supply.
5 V Hold-up Capacitor
C59
15
47uF Capacitor. Keeps U1, U3, and U4 alive after 
+5 V power outage to store faults.
5 V Charging Resistor
R120
15
100 Ohm Resistor. Prevents large in-rush current
charging the hold-up capacitor at power up.
12 V Blocking Diode
D37
9
Schottky Diode. Prevents external loads or supply
from draining the hold-up capacitor.
12 V Passing Diode
D38
9
Schottky Diode. Allows the hold-up capacitor to provide full current to down-stream supply.
12 V Hold-up Capacitor
C27, C28
9
47 uF and 220 uF Capacitors. Keeps U1, U3, and U4
alive after +12 V power outage to store faults.
12 V Charging Resistor
R52
9
100 Ohm Resistor. Prevents large in-rush current
charging the hold-up capacitor at power up.
Component / Signals
Description
Components
25
Platform Manager 2 Evaluation Board
Figure 15 shows the hold-up circuit for the USB +5 V supply. If the USB +5 V supply suddenly fails, this hold-up circuit will power the Platform Manager 2 and flash memory long enough to store the fault. The USB +5 V can fail for
several of the following reasons: the USB cable is unplugged, the USB hub is powered down, the FTDI (U6) device
is told to power down and Q2 is turned off. The signal +5V_USB_SW is connected to VMON5 of LPTM21 (U1 on
sheet 2) for early detection of a 5 V fault. Small signal Schottky diodes are used for the blocking and passing
diodes as the power required for the Platform Manager 2 and flash memory is fairly low. The size of the hold-up
capacitor (C59) should be increased for fault logging support if significant loads are added to the +3.3 V supply.
The charging resistor (R120) prevents large in-rush currents when the supply is connected or turned on.
Figure 15. Fault Log Hold-Up Circuit for 5 V
+5V_USB_SW
+5V_USB_SW (2,9)
+5V_USB
Q2
IRLML6402
D41
NSR0530P2T5G
R118
1M
R119
2.2k
+3.3V_USB_SW
U8
3
R120
100
D43
NSR0530P2T5G
IN
C60
10uF
10V
OUT
TAB
2
4
GND
1
NCP1117
+3.3V_USB_SW (2)
C61
6.8uF
16V
C58
0.33uF
C59
47uF
16V
D42
Blue
PWR_ENABLEb
R237
10k
Figure 16 shows the hold-up circuit for the +12 V supply; it is similar to the 5 V circuit described above. The +12 V
supply is monitored by the HIMONN_HVMON pin of the LPTM21 (U1 on sheet 2) for early detection of supply failure. The small signal Schottky diodes are used for blocking and passing the charge on the hold-up capacitors (C27
and C28). The charging resistor R52 prevents large in-rush currents when the supply is connected or turned on.
Figure 16. Fault Log Hold-Up Circuit for 12V
+11.3V
+12V
PWR JACK
1
2
3
+12V (2,8,10,11,13,16)
+11.3V (2,10)
J28
D37
J25
NSR0530P2T5G
B
A
D45
SMBJ22CA
2 Position Terminal Block
R52
100
D38
NSR0530P2T5G
C27
47uF
25V
C28
220uF
25V
Both the LPTM21 and L-ASC10 devices have non-volatile EEPROM and volatile registers available to store fault
log data. In addition, the LPTM21 device can store fault log data either internally in the User Flash Memory (UFM)
of the FPGA section of U1 or externally in the SPI Flash Memory (U3). The Platform Manager 2 evaluation board
has an external SPI 4 MB flash (U3) connected to the LPTM21 SPI interface to communicate with the memory as
shown in Figure 21. This memory can be used for both Dual Boot and Fault Logging. The Platform Designer tool
has a Fault Logging component which is used to configure what is logged and how it is stored. For additional information regarding fault logging please refer to TN1277, Fault Logging Using Platform Manager 2.
26
Platform Manager 2 Evaluation Board
Close Loop Trim Operation
A differentiating feature of the Platform Manager 2 is the Closed Loop Trim (CLT) feature which is used to accurately trim and margin power supplies. The Platform Manager 2 evaluation board provides CLT circuits for up to
eight DC-DC power supplies; four (DCDC1 – DCDC4) are controlled by LPTM21 (U1) and four (DCDC5 – DCDC8)
are controlled by L-ASC10 (U4). Table 7 lists the installed components and signals associated with CLT operation
on the Platform Manager 2 evaluation board.
Table 7. Installed Components and Signals for Closed Loop Trim Operation
Ref. Des.
Schematic
Sheet
DC-DC Converter
DCDC3, DCDC4
12
Dual-footprint +5 V input adjustable output power
supply. NQR002A0X4Z SIP installed.
DC-DC Converter
DCDC7, DCDC8
14
Dual-footprint +5 V input adjustable output power
supply. NQR002A0X4Z SIP installed.
Q48,Q49,
Q54,Q55
12, 14
FDV301N N-Channel MOSFET. Inverts the DC-DC
enable signal from ASC GPIO for SIP.
D51, D52, D55,
D56
12, 14
LED to indicate output of DC-DC is active.
R185,R186,
R189, R190
12, 14
470 Ohm resistor limits the LED current.
Q36,Q37,Q40,
Q41
12, 14
2N3904 NPN Transistor drives LED on when DC-DC
output is active.
R193, R194,
R197, R198
12, 14
4.7 kOhm resistor limits the base current of NPN transistor.
Tantalum Cap 1
C35, C37, C43,
C45
12, 14
22 uF, 10 V capacitor +5 V DC-DC input filter.
Ceramic Bypass Cap
C83, C84, C86,
C87,C95,C96,
C98,C99
12, 14
100 nF 16 V capacitor +5 V DC-DC input and output
filter.
Tantalum Cap1
C36, C38, C44,
C46
12, 14
22 uF, 10 V capacitor +5 V DC-DC output filter.
DC-DC Output Load Resistor1
R82, R89,
R110,R117
12, 14
470 and 330 Ohm resistors pull DC-DC output down
to zero when disabled.
DC-DC 3 Trim Resistors1
R76 – R81
12
Resistor values based on Platform Designer Trim Calculator. Three installed.
DC-DC 4 Trim Resistors1
R83 – R88
12
Resistor values based on Platform Designer Trim Calculator. Three installed.
DC-DC 7 Trim Resistors1
R104 – R109
14
Resistor values based on Platform Designer Trim Calculator. Three installed.
DC-DC 8 Trim Resistors1
R111 – R116
14
Resistor values based on Platform Designer Trim Calculator. Three installed.
C82, C85, C94,
C97
12, 14
Phoenix 2-Terminal Connector DCDC 3 and 7
J19, J23
9
Wire to board connectors to apply off-board loads to
DC-DC.
Phoenix 4-Terminal Connector DCDC 4 and 8
J20, J24
9
Wire to board connectors to apply off-board loads to
DC-DC with remote sensing.
Ground Sense Resistor
R13, R32
9
100 Ohm resistor: default ground sense connection
when off-board sensing is not used.
VMON Series Resistor
R14, R59
9
100 Ohm resistor: default VMON connection when
off-board sensing is not used.
Component / Signals
Description
Components
N-Channel MOSFET – SOT-23
Green LED
LED Bias Resistor
NPN Transistor – SOT-23
NPN Bias Resistor
Ceramic Cap1
27
10 nF 10 V capacitor: trim network filter.
Platform Manager 2 Evaluation Board
Ref. Des.
Schematic
Sheet
2x5 Header
J35
12
Header to connect PM bus controller for DC-DC convertors (DOSA supplies).
1x2 Header
J29
9
Jumper to provide +5 V to the DC-DCs from USB.
Component / Signals
Description
Signals
A0_LED5
2, 11
DCDC1 enable signal from ASC0_GPIO5. Safe state
is low.
A0_LED6
2, 11
DCDC2 enable signal from ASC0_GPIO6. Safe state
is low.
A0_LED3
2, 12
DCDC3 enable signal from ASC0_GPIO3. Safe state
is low.
A0_LED4
2, 12
DCDC4 enable signal from ASC0_GPIO4. Safe state
is low.
A1_LED5
2, 13
DCDC5 enable signal from ASC1_GPIO5. Safe state
is low.
A1_LED6
2, 13
DCDC6 enable signal from ASC1_GPIO6. Safe state
is low.
A1_LED8
2, 14
DCDC7 enable signal from ASC1_GPIO8. Safe state
is high.
A1_LED9
2, 14
DCDC8 enable signal from ASC1_GPIO9. Safe state
is high.
TRIM_DCDC1
2, 11
DCDC1 Trim signal from ASC0_TRIM1.
TRIM_DCDC2
2, 11
DCDC2 Trim signal from ASC0_TRIM2.
TRIM_DCDC3
2, 12
DCDC3 Trim signal from ASC0_TRIM3.
TRIM_DCDC4
2, 12
DCDC4 Trim signal from ASC0_TRIM4.
TRIM_DCDC5
5, 13
DCDC5 Trim signal from ASC1_TRIM1.
TRIM_DCDC6
5, 13
DCDC6 Trim signal from ASC1_TRIM2.
TRIM_DCDC7
5, 14
DCDC7 Trim signal from ASC1_TRIM3.
TRIM_DCDC8
5, 14
DCDC8 Trim signal from ASC1_TRIM4.
OUT_DCDC1
2, 11
DCDC1 Output connected to ASC0_VMON1 via R1.
OUT_DCDC2
2, 11
DCDC2 Output connected to ASC0_VMON2 via R2.
OUT_DCDC3
2, 12
DCDC3 Output connected to ASC0_VMON3 via R3.
OUT_DCDC4
2, 9, 12
DCDC4 Output connected to ASC0_VMON4 via R4.
OUT_DCDC5
5, 13
DCDC5 Output connected to ASC1_VMON1 via R23.
OUT_DCDC6
5, 13
DCDC6 Output connected to ASC1_VMON2 via R24.
OUT_DCDC7
5, 14
DCDC7 Output connected to ASC1_VMON3 via R25.
OUT_DCDC8
5, 9, 14
DCDC8 Output connected to ASC1_VMON4 via R26.
DCDC4_SENSE
9, 12
DCDC4 Sense input connected to DCDC4 output via
R14.
DCDC8_SENSE
9, 14
DCDC8 Sense input connected to DCDC8 output via
R59.
4, 11 - 14
DOSA DC-DC Synchronization signals: support for
operating the supplies at different phases to minimize
switching noise from the primary supply.
11 - 14
PM Bus control signals for DOSA DC-DC convertors.
DCDC1_SYNC – DCDC8_SYNC
PMBUS_SDA, PMBUS_SCL,
SMB_ALERT
1. Value is subject to change and/or may not be required based on customer design.
28
Platform Manager 2 Evaluation Board
Generic Overview of Trim and Margin Operation
The Platform Manager 2 evaluation board can support up to eight DC-DC modules. All eight are similarly designed
and laid out so we will detail the generic similarities rather than provide a separate section for each DC-DC. The
Platform Manager 2 evaluation board provides two footprints for each DC-DC: one is for a Single Inline Package
(SIP) and the other is for the Distributed Open Source Alliance (DOSA) compliant package. The SIP footprint is
populated for DCDC3, DCDC4, DCDC7, and DCDC8. The other DCDC locations are unpopulated to support user
evaluation of other DC-DC supplies of either footprint. In addition, all of the surrounding components are also
unpopulated for DCDC1, DCDC2, DCDC5, and DCDC6 to support the design and evaluation of different devices
and values with Platform Manager 2.
ASC0 (U1) is used to enable, monitor, and trim DCDC1 – DCDC4 which are located on the left side of the board
and ASC1 (U4) is used to enable, monitor, and trim DCDC5 – DCDC8 which are located on the right side of the
board. The top four DC-DC supplies are powered by +12 V (DCDC1, DCDC2, DCDC5, and DCDC6) while the bottom four DC-DC supplies are powered by +5 V (DCDC3, DCDC4, DCDC7, and DCDC8). The installed DC-DC supplies can only be powered and demonstrated using an off board +5 V source. For light loads the +5 V from the USB
cable can be used by installing a jumper on J29, while heavier loads may require a bench supply connected to J12.
The Platform Manager 2 evaluation board provides footprints and circuit connections for six trimming resistors for
each DCDC. These six resistors are shared by both the SIP and DOSA footprints because only one supply can be
populated at a time. The resistors are organized in an “H” pattern both in the schematic and on the board layout. The
resistors are named in the schematic to match the names used in the Platform Designer Trim-view calculator. The
names are listed and described in Table 8 below. Typically only three resistors are suggested by the calculator; a pull
up, a pull down, and a series resistor. The exact population of the “H” pattern depends on many factors that the calculator takes into account such as type of DC-DC, output voltage, and range of trim. The Platform Manager 2 evaluation
board provides pads and connections to support any result from the Trim Calculator. However, with certain supplies
and by adjusting the options, the calculator can produce a result that only uses two resistors: a pull down and a series
resistor. The DC-DCs on the Platform Manager 2 Evaluation board are populated with the two resistor solution. A key
requirement for the calculator to produce a two resistor solution is the Bi-Polar Zero (BPZ) voltage of the Trim Cell has
to match the DC-DC’s internal reference voltage. Otherwise the calculator will add a pull up or pull down resistor in
attempt to offset the imbalance and still keep the Trim DAC code near 80h (the BPZ value, halfway between –127 and
+128). For more information on the Trim interface and Calculator please see AN6074 Interfacing the Trim Output of
Power Manager II Devices to DC-DC Converters and the Platform Designer User Guide.
The Platform Manager 2 evaluation board uses two resistors for Rseries, Rs1 and Rs2, and places a 10nF capacitor in between them to form a low pass filter. The sum of Rs1 and Rs2 should equal the Rseries value calculated by
Platform Designer. This filter network is recommended by some DOSA supply data sheets however, other supplies
can also benefit from the additional filtering.
Table 8. Trim Resistor "H-Network" Names.
Schematic Name
Calculator Name
RpupS
RpupSupply
Description
RpdnS
RpdnSupply
Rs1
Rseries
Series resistor (½ between Trim DAC output and filter)
Series resistor (½ between filter and DC-DC Trim input)
Pull up resistor at DC-DC Trim input
Pull down resistor at DC-DC Trim input
Rs2
Rseries
RpupD
RpupDAC
Pull up resistor at Trim DAC output
RpdnD
RpupDAC
Pull down resistor at Trim DAC output
In order for the CLT circuits within the ASC to operate properly the output of the supply needs to be monitored by
the correct VMON input. The Platform Manager 2 evaluation board illustrates the correct trimming connections by
using TRIM1 with VMON1, TRIM2 with VMON2, all the way to TRIM4 with VMON4. As discussed in the Voltage
Monitor Operation section, the DCDC outputs are connected to the VMON inputs using a series resistor with a
value of 270 Ohms (see sheets 2 and 5). The series resistor is not required in customer designs; the only function
on the evaluation board is to isolate the DCDC outputs from the VMON test points. The VMON series resistor
29
Platform Manager 2 Evaluation Board
allows another voltage source to be applied to the VMON test point directly. If the voltage source has a high output
impedance, the VMON series resistor should be removed for accurate operation.
Each of the DCDC supplies has a dummy load resistor connected to the output. The dummy load resistor is not
required in customer designs as the supply is connected to a real load. The dummy load resistor is only used on
the evaluation board to prevent the output of the supply from “creeping up” when the supply is disabled. Without the
dummy load resistor, an output of around 1 V can appear at the output of disabled supplies. The dummy load resistors are sized based on the target DCDC supply output voltage; lower values for lower voltages and higher values
for higher voltages. In all circuits they are 1/10 watt packages because there is minimal heat generated.
DCDC1 – Enable and Trim Operation
In this section we will analyze the specific circuits that support DCDC1. The circuits for DCDC2, DCDC5, and
DCDC6 are similar to DCDC1 and therefore will not be discussed in detail. In Figure 17 the control signal
A0_LED5, which comes from ASC0’s GPIO5 output, is inverted and level shifted by a small signal N-channel MOSFET (Q15 FDV301N). For +12 V supplies a buffer or inverter is needed because the ASC GPIOs can only be pulled
up to +5.5 V. All the GPIOs of the ASC have a “safe state” which defines the behavior independent of configuration
during Power-On-Reset (POR) or during programming; the safe state of GPIO5 is low. The DOSA supply is
enabled when the On-Off pin is low (negative enable logic), so the inverter Q15 prevents the supply from turning on
during POR or programming. Similarly, the SIP supply is enabled when the On-Off pin is high (positive enable logic)
so, the second MOSFET inverter Q45 prevents the SIP from turning on during POR or programming. Both MOSFETs use a 20k pull-up resistor to +12 V to insure a full logic swing at the enable inputs of the supplies.
Figure 17. Power On Indication, Enable, and Trim Circuits for DCDC1
(2,3,4,5,6,7,8,9,10,12,13,14,16)
+3.3V
R183
470
DCDC1_A
NQR002A0X4Z
(2,8,9,10,13,16) +12V
2
R162
20K
Vout
Vin
D49
Green
SM_LED_0603
4
SIP
5V @ 2A
R213
20K
C31
22uF
16V
1
On-Off Control
Trim
5
GND
Q45
FDV301N
Q34
2N3904
C78
100nF
3
R191
4.7k
C77
100nF
DOSA
5V @ 3A
PDT003A0X3
DCDC1
2
1
PMBUS_SCL
TP10_SYNC
(4) DCDC1_SYNC
SMB_ALERT
PMBUS_SDA
8
9
10
11
14
15
VOUT
VS+
VIN
ON_OFF
TRIM
CLK
SEQ
PGOOD
SYNC
ADDR0
ADDR1
SMBALERT
DATA
GND GND
3
7
VS-
4
5
R62
open
RpupS
R66
open
RpupD
R64
5.6k
Rs2
R65
5.6k
Rs1
6
16
17
R63
2.74k
RpdnS
12
R67
open
RpdnD
SIG_GND
13
R204
130k
Q15
FDV301N
(2,7) A0_LED5
ASC0 GPIO5
(2) TRIM_DCDC1
ASC0 TRIM1
30
R205
23.7k
C76
10nF
OUT_DCDC1 (2,9)
ASC0 VMON1
C32
22uF
10V
R68
1K
Platform Manager 2 Evaluation Board
The control signal A0_LED5 is also used to turn on a red LED (D7) when it is low and is pulled up to +3.3 V by a
2.2k Ohm resistor (RN11B see sheet 7). Because the installed supply could use either positive or negative enable
logic, the illumination of LED D7 may not correspond to the supply being enabled. A separate green LED (D49) is
used to indicate when the supply is enabled. An NPN transistor (Q34) is used to turn the green LED on when the
supply has enough voltage to bias the emitter-base junction (slightly more than 0.7 V).
Supply filtering is provided by a 22 uF and 100 nF pair of capacitors, both at the input and output, that are located
close to both DC-DC footprints to be effective for either. For DCDC1 the input capacitors are C31 and C77 while the
output capacitors are C32 and C78. A load resistor (R68) is used to pull the DCDC output low when it is disabled.
Note, these values may not be optimal for all supplies and loading conditions; specific filtering requirements should
be followed from the supply data sheet.
All the DOSA supply footprints on the Platform Manager 2 evaluation board have provision to set the PMBus
address with pull-down resistors; for DCDC1 these are R204 and R205. The PMBus signals (PMBUS_SDA,
PMBUS_SCL, SMB_ALERT) are bussed to all the DCDCs and are brought out on connector J35. Each DOSA
supply footprint also has a SYNC connection to demonstrate the PMBus feature of DC-DC phasing; where the
switching circuits of different DC-DCs is synchronized out-of-phase to minimize the peak power requirements of the
power source.
DCDC4 – Enable and Trim Operation
In this section we discuss the circuits for the +5 V input supplies with a focus on DCDC4. The circuitry for all the
DCDCs is very similar, so this discussion will be limited to the key differences from the +12 V input supplies
described in the previous section (DCDC1). The support circuits with DCDC4 are shown in Figure 18.
Figure 18. Power On Indication, Enable, and Trim Circuits for DCDC4
+3.3V
2
C37
22uF
10V
C86
100nF
R186
470
DCDC4_A
NQR002A0X4Z
+5V
Vout
Vin
D52
Green
SM_LED_0603
4
SIP
1.2V @ 2A
R165
10K
1
C87
100nF
Trim
On-Off Control
5
Q37
2N3904
GND
DCDC4_SENSE (2,9)
3
(11,13,14) PMBUS_SCL
TP13_SYNC
(4) DCDC4_SYNC
(11,13,14) SMB_ALERT
(11,13,14) PMBUS_SDA
8
9
10
11
14
15
VIN
ON_OFF
VOUT
VS+
CLK
SEQ
PGOOD
SYNC
TRIM
ADDR0
ADDR1
SMBALERT
DATA
GND GND
3
R83
open
RpupS
DOSA
1.2V @ 3A
PDT003A0X3
DCDC4
2
1
A0_GS_VMON4 (2,9)
7
VS-
4
5
R87
open
RpupD
R85
19.6k
Rs2
R86
19.6k
Rs1
R84
20.0k
RpdnS
R88
open
RpdnD
OUT_DCDC4 (2,6,9)
ASC0 VMON4
6
16
17
12
SIG_GND
13
R194
4.7k
R210
130k
Q49
FDV301N
(2,7) A0_LED4
ASC0 GPIO4
(2) TRIM_DCDC4
ASC0 TRIM4
31
R211
84.5k
C85
10nF
C38
22uF
10V
R89
330
Platform Manager 2 Evaluation Board
The circuits for DCDC3, DCDC7, and DCDC8 are similar to DCDC4 and therefore will not be discussed in detail.
The significant difference from the circuit for DCDC1 shown in Figure 17 is the +5 V input supply power for DCDC4
instead of +12 V. At this voltage level the On-Off pin of the SIP can be connected directly to the GPIO4 output of
ASC0 without the need for a buffer. The inverter (Q49) is still used to keep the DOSA supply turned off during POR
and programming.
One other unique feature of DCDC4 (and DCDC8) is the support for remote sensing when the DOSA supply is
installed after removing the SIP. The V+ and V- pins of the DOSA are routed to a four pin screw connecter (J20 and
J24 on sheet 9) instead of directly to the output and ground. Resistors with the value of 100 Ohms (R13, R14 and
R32, R59 on sheet 9) are used to connect the sense pins to the output and ground when off-board connections are
not used. When a four-wire off board load is used, the 100 Ohms is bypassed by a direct short and the V+ and Vpins sense the voltage at the load.
One difference from Figure 18 for DCDC7 and DCDC8 is the connections for the enable inverter. Since the safe
state for GPIO8 and GPIO9 is high-impedance, the inverter transistors are used on the SIPs for DCDC7 and
DCDC8 instead of the DOSAs (see sheet 14).
Table 9 provides a summary of the installed DCDCs, the connections, logic levels, and voltages for a quick reference for designers.
Table 9. Summary of DCDC Trim Circuits.
DCDC
Package
Vin
Vout
Control
Signal
ASC
GPIO
On Logic
Level
VMON
RpdnS
Rseries
11
n/a
12 V
n/a
A0_LED5
ASC0
GPIO5
n/a
1
n/a
n/a
1
2
n/a
12 V
n/a
A0_LED6
ASC0
GPIO6
n/a
2
n/a
n/a
3
SIP
5V
2.5 V
A0_LED3
ASC0
GPIO3
1
3
6.34k
22k
4
SIP
5V
1.2 V
A0_LED4
ASC0
GPIO4
1
4
20k
39.2k
51
n/a
12 V
n/a
A1_LED5
ASC1
GPIO5
n/a
1
n/a
n/a
1
6
n/a
12 V
n/a
A1_LED6
ASC1
GPIO6
n/a
2
n/a
n/a
7
SIP
5V
2.5 V
A1_LED8
ASC1
GPIO8
0
3
6.34k
22k
8
SIP
5V
1.2 V
A1_LED9
ASC1
GPIO9
0
4
20k
39.2k
1. Values shown in the schematic for these DC-DC converters is for example only – they are not installed.
The Platform Manager 2 evaluation board has four DC-DC trim circuits that are unpopulated to allow customization
and evaluation of different circuits and devices, Table 10 lists the un-installed components to support custom
designs.
32
Platform Manager 2 Evaluation Board
Table 10. Un-Installed Components for Closed Loop Trim Operation1
Ref. Des.
Schematic
Sheet
DC-DC Converter
DCDC1, DCDC2
11
Dual-footprint +12 V input adjustable output power
supply.
DC-DC Converter
DCDC5, DCDC6
13
Dual-footprint +12 V input adjustable output power
supply.
N-Channel MOSFET – SOT-23
Q15 – Q18
11, 13
FDV301N N-Channel MOSFET. Inverts the DC-DC
enable signal from ASC GPIO and shifts the level up
to +12 V.
N-Channel MOSFET – SOT-23
Q45,Q47,Q51,Q
53
11, 13
FDV301N N-Channel MOSFET. Inverts the DC-DC
enable signal from DOSA to SIP.
Green LED
D49,D50,D53,D
54
11, 13
LED to indicate output of DC-DC is active.
LED Bias Resistor
R183,R184,R18
7,R188
11, 13
470 Ohm resistor limits the LED current.
NPN Transistor – SOT-23
Q34,Q35,Q38,Q
39
11, 13
2N3904 NPN Transistor drives LED on when DC-DC
output is active.
NPN Bias Resistor
R191,R192,R19
5,R196
11, 13
4.7k Ohm resistor limits the base current of NPN transistor.
Tantalum Cap2
C31,C33,C39,C
41
11, 13
22 uF, 16 V capacitor +12 V DC-DC input filter.
Ceramic Bypass Cap
C77,C78,C80,C
81,C89,
C90,C92,C93
11, 13
100 nF 16 V capacitor +12 V DC-DC input and output
filter.
Tantalum Cap2
C32,C34,C40,C
42
11, 13
22 uF, 10 V capacitor +12 V DC-DC output filter.
DC-DC Output Load Resistor2
R68,R75,R96,R
103
11, 13
1k and 680 Ohm resistors pull DC-DC output down to
zero when disabled.
R204 – R211,
R218 – R225
11, 12,13, 14
Various resistor values to set PMBus address based
on DOSA DC-DC data sheet.
DC-DC 1 Trim Resistors2
R62 – R67
11
Resistor values based on Platform Designer Trim Calculator. None installed.
DC-DC 2 Trim Resistors2
R69 – R74
11
Resistor values based on Platform Designer Trim Calculator.
DC-DC 5 Trim Resistors2
R90 – R95
13
Resistor values based on Platform Designer Trim Calculator.
DC-DC 6 Trim Resistors2
R97 – R102
13
Resistor values based on Platform Designer Trim Calculator.
Ceramic Cap2
C76, C79, C88,
C91
11, 13
Phoenix 2-Terminal Connector
DCDC 1, 2, 5, and 6
J17,J18,J21,J22
9
Components
DC-DC PMBus Address Setting
Resistor2
Description
10 nF 10 V capacitor: trim network filter.
Wire to board connectors to apply off-board loads to
DC-DC.
1. Not installed to allow customer development on the evaluation board.
2. Value is subject to change and/or may not be required based on customer design.
33
Platform Manager 2 Evaluation Board
VID Operation
Voltage Identification (VID) is supported by Platform Designer and the Platform Manager 2 evaluation board. In the
Platform Designer Voltage view, VID can be configured and added to any Trim output. The Platform Manager 2
evaluation board has DC-DC supplies, switches, and connections to support VID operation. Table 11 lists the components and signals associated with VID operation on the Platform Manager 2 board.
Table 11. Components and Signals for VID Operation
Ref. Des.
Schematic
Sheet
DC-DC Convertor
DCDC3, DCDC4
12
Dual-footprint +5V input adjustable output power supply. NQR002A0X4Z SIP installed.
DC-DC Convertor
DCDC7, DCDC8
14
Dual-footprint +5V input adjustable output power supply. NQR002A0X4Z SIP installed.
DC-DC Trim Resistors 2
R76 – R81,
R83 – R88
12
Resistor values based on Platform Designer Trim Calculator. Three installed.
DC-DC Trim Resistors 2
R104-R109,
R111-R116
14
Resistor values based on Platform Designer Trim Calculator. Three installed.
8- position DIP switch1
SW6
6
Switch is used to change the VID Select Bus.
Push Button Switch1
SW2
6
Switch is used to create a VID strobe signal.
Components / Signals
Description
Components
Signals
VIDA_1 to VIDA_8
4, 6
Signals used as the VID Select Bus.
VIDA_SW
4, 6
Signal used to strobe the VID Select Bus into the VID
IP.
1. Installed to allow demos and development on the evaluation board customer designs can use other methods.
2. Value is subject to change and/or may not be required based on customer design.
When VID is added to a Trim channel in Platform Designer the software adds the VID IP to the design. The function
of the VID IP is to read the Select Bus when the strobe signal is active and then send the target voltage to the corresponding ASC via I2C. The VID IP translates the Select Bus value to the target voltage using a look-up table that
is defined in the Platform Designer software. The Closed Loop Trim (CLT) circuits within the ASC then drive the
Trim DAC output pin which adjusts the DC-DC output to the target voltage as read by the VMON input pin. For a
more complete explanation of VID operation please see AN6092, Implementing VID Function with Platform Manager 2.
Figure 19. Switches for VID
VID A
+3.3V
+3.3V
SW6A
1
16
VIDA_1
1
10k
10
RN1A
2
15
VIDA_2
2
10k
RN1B
3
14
VIDA_3
3
10k
RN1C
4
13
VIDA_4
4
10k
RN1D
5
12
VIDA_5
6
10k
5
RN1E
6
11
VIDA_6
7
10k
RN1F
7
10
VIDA_7
8
10k
RN1G
8
9
VIDA_8
9
10k
RN1H
R242
10k
SW6B
SW6C
VIDA_SW (4)
1
SW6D
4
SW2
VID_A
SW6E
2
SW6F
SW6G
SW6H
VIDA_[1:8] (4)
34
3
Platform Manager 2 Evaluation Board
Two switches are provided on the Platform Manager 2 evaluation board as shown in Figure 19; one is an eight position piano-style DIP switch (SW6) and the other is a momentary push button switch (SW2). As seen in Figure 5,
SW6 is located in the lower right of the board. When the switch lever is up the signal is high (1) and when the switch
lever is down the signal is low (0). It is up to the design as to the number and order of the switch positions used to
generate the VID Select Bus. The eight position switch can easily support two VID channels of four bits each or a
slightly more complex design could use three bits to multiplex the strobe signal to eight VID channels and use the
other five bits as a common VID Select Bus. The push button switch SW2 can be used to generate a falling edge
“VID Strobe” signal which triggers the VID IP to sample the VID Select Bus and update the target voltage. For
design support the VID signals are defined in the preference file listing in Appendix B.
Programming and Configuration
The two featured devices on the Platform Manager 2 evaluation board are the LPTM21 and L-ASC10 (U1 and U4).
Both devices have non-volatile memory that can be erased and reprogrammed numerous times to support demos,
development, and testing. They can also be configured from the SPI memory (U3). The primary method of reprogramming U1, U3, and U4 is with Diamond Programmer using a USB cable. Table 12 lists the components and signals associated with programming and configuring the LPTM21, L-ASC10, and SPI devices on the Platform
Manager 2 evaluation board.
Table 12. Components and Signals for Programming.
Ref. Des.
Schematic
Sheet
USB connector
J16
15
USB Mini connector for connecting with USB cable
(included).
FT2232H
U6
15
FTDI chip converts USB to JTAG signal for programming U1 directly and U4 via the JTAG to I2C bridge
within U1; also ASC2 and ASC3 if connected. The
FTDI device also converts USB to I2C for software
utilities.
R158
3
4.7k Ohm Resistor. Connected between +3.3 V and
JTAGENAB pin of LPTM21.
Zero Ohm Jumper1
R122 – R125
15
Zero Ohm Resistor. Connects FTDI to JTAG signals.
Remove to disconnect U6 from JTAG.
Zero Ohm Jumper1
R126 – R127
15
Zero Ohm Resistor. Connects FTDI to I2C bus.
Remove to disconnect U6 from I2C bus.
Zero Ohm Jumper1
R248
15
Zero Ohm Resistor. Connects I2C-Enable signal to
FTDI. Remove to use J33 in manual mode.
Red LED
D57
15
Red LED indicates when FTDI U6 is the I2C master.
LED Bias Resistor
R264
15
470 Ohm Resistor. Limits the current in D57 when
Q42 is on.
LED Drive Transistor
Q42
15
2N3904 NPN Transistor. Drives LED D57 on when
USB_I2C_EN signal is active.
Components / Signals
Description
Components
JTAG Enable Pull-up Resistor
Transistor Bias Resistor
R263
15
4.7k Ohm Resistor. Sets the base current of Q42.
U10, U11
3
FSA4157 Analog Switch. Used to disconnect the
FTDI I2C ports from the bus when FTDI is not the
master.
I2C Address Resistor
R27
5
A pull down resistor of 2.2K connected to I2C_ADDR
pin of L-ASC10. This sets the LSBs for I2C slave (LASC10) address to ”001”.
Atmel 4MB Flash Memory1
U3
3
SPI Flash memory to store “Golden Bitstream” for
Dual Boot Programming operation.
2 x 1 Header
J33
3
Unpopulated header provides manual control of
USB_I2C_EN.
I2C MUX1
35
Platform Manager 2 Evaluation Board
Ref. Des.
Schematic
Sheet
8 x 1 Header
J2
3
Unpopulated header provides JTAG access for
optional programming with JTAG cable (not included).
8 x 1 Header
J26
3
Unpopulated header provides access to I2C and SPI
signals.
Components / Signals
Description
Signals
USB_TCK,
USB_TMS,
USB_TDO,
USB_TDI
3, 15
The 4 JTAG signals for programming LPTM21 and
ASC devices via the JTAG to I2C bridge within U1.
USB_I2C_EN
3, 15
Controls the I2C MUX. When this signal is high the I2C
pins of the FTDI device U6 are connected to the I2C
bus.
FTDI_SDA,
FTDI_SCL
3, 15
Branch off the main I2C bus connected using a MUX.
SPI_CS0,
SPI_CLK,
SPI_IN,
SPI_OUT
3
Bus between memory and SPI port of LPTM21 for
Dual boot programming operation.
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
The Platform Manager 2 evaluation board provides both a JTAG and I2C programming interface for LPTM21 and LASC10. A portion of the schematic which supports programming is shown in Figure 20 below.
VPHY
VPLL
49
1
VCC
7
8
2
3
DD+
4
5
NC
GND
6
7
8
9
CASE
CASE
CASE
CASE
10nF
SHLD
R230
2.2k
14
R231
12k
6
C47
R235
63
62
61
100k
10
11
MH1
MH2
2
+3.3V_USB
20
31
42
56
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
RESET#
REF
EECS
EECLK
EEDATA
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSCI
C56
18pF
3
3
2
OSCO
4
12MHZ
C55
18pF
13
TEST
U7
8
7
6
5
VCC
NC
ORG
GND
CS
SK
DIN
DOUT
M93C46-WMN6TP
1
2
3
4
EECS
EESK
EEDATA
1
R234
2
FTDI High-Speed USB
FT2232H
2.2k
10
SOIC-8
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
PWREN#
SUSPEND#
16
17
18
19
21
22
23
24
+3.3V
0
0
0
0
USB_TCK (3)
USB_TDI (3)
USB_TDO (3)
USB_TMS (3)
0
USB_I2C_EN (3)
R264
470
D57
Red
SM_LED_0603
R248
26
27
28
29
30
32
33
34
Q42
2N3904
R263
4.7k
R126
R127
38
39
40
41
43
44
45
46
0
0
FTDI_SCL (3)
FTDI_SDA (3)
48
52
53
54
55
57
58
59
60
PWR_ENABLEb
36
GND
GND
GND
GND
GND
GND
GND
GND
C57
100nF
VREGOUT
DM
DP
X1
1
R236
10k
+3.3V_USB
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VREGIN
AGND
TYPE_B
50
R217
0
USB_MINI_B
R122
R123
R124
R125
1
5
11
15
25
35
47
51
J16
VCCIO
VCCIO
VCCIO
VCCIO
4
9
U6
FT2232HL
USB Connection
VCORE
VCORE
VCORE
+3.3V_USB
L2
Ferrite_bead
12
37
64
Figure 20. USB Programming Interface
The mini-USB connector (J28) provides the USB connection to a computer running Lattice Diamond Programmer
software. The FTDI device (U6) provides the interface between USB and JTAG signals (on AD BUS) and I2C signals (on BD BUS). The FPGA within the LPTM21 device is programmed directly from the JTAG signals. All the ASC
devices are programmed over the I2C bus using the LPTM21 built in JTAG to I2C bridge. When the LPTM21 device
is the I2C master the MUX is needed to disconnect the I2C pins of the FTDI device (U6) from the bus. This is
because the FTDI pins do not support multi-master mode and will load down the bus and prevent proper operation.
The MUX can be controlled either by the FTDI device (U6 - bit 0 on the AC BUS) or the jumper J33 setting the level
of USB_I2C_EN. The Platform Manager I2C Software Utility controls the MUX automatically. When other software
is used that does not drive the USB_I2C_EN signal, the user must control the MUX manually with J33. When the
signal USB_I2C_EN is high the I2C pins of the FTDI device (U6) are connected to the I2C bus and the red LED
(D57) is illuminated.
36
Platform Manager 2 Evaluation Board
The zero Ohm resistors (R122 – R127) connected to the FTDI device (U6) pins are installed to support the on
board connections. If off-board JTAG or I2C sources are used the zero Ohm resistors should be removed to prevent
the I/O pins of the FTDI device (U6) from loading down the signals.
To support dual boot the 4Mbit SPI Flash Memory device (U3) is connected to the SPI pins of the LPTM21 device
(U1). The memory is programmed using Diamond Programmer and the JTAG to SPI interface built into the FPGA
of U1. The SPI signals are also brought out to the unpopulated header J26 to support alternate programming
sources.
On sheet 5 the LSBs of the I2C slave address for the L-ASC10 device (U4) are determined by the value of resistor
R27 connected between the I2C_ADDR pin and ground. The 2.2k Ohm resistor value corresponds to ASC1 and
LSBs of “001”.
For additional information regarding programming the LPTM21 and L-ASC10 please refer to AN6091, Powering Up
and Programming Platform Manager 2 and L-ASC10.
Dual Boot Operation
The Platform Manager 2 devices are designed to support field updates. In the event that an update is terminated
prematurely either by power outage or communication interruption, a back-up boot image can be recalled from the
SPI flash memory. This back-up boot image is called the default or “Golden” bit-stream and is used to boot the
LPTM21 and L-ASC10 devices. Thus the system can operate from this default design at a basic support level until
another field update can be completed. Table 13 lists the components and signals associated with the dual boot
operation.
Table 13. Components and Signals for Dual Boot Operation.
Ref. Des.
Schematic
Sheet
U3
3
SPI Flash memory to store “Golden” bit-stream for
Dual Boot Programming operation. This is the same
memory that is used for Fault Logging.
Pull-up Resistor
R159
3
1k Ohm Resistor. Strong pull-up is required for SPI
Clock.
Pull-up Resistor
R19
3
10k Ohm Resistor. Weak pull-up is required for SPI
Chip Select.
RC Delay Resistor
R265
3
100k Ohm Resistor. Used to delay INITN pin of
LPTM21 during power up.
RC Delay Capacitor
C102
3
10 uF Capacitor. Used to delay INITN pin of LPTM21
during power up.
SPI_CS0,
SPI_CLK,
SPI_IN,
SPI_OUT
3
SPI signals to read the “Golden” bit-stream from the
external memory into the LPTM21 and L-ASC10
devices.
Proto_INITN
3
Signal used to delay the external boot process of the
LPTM21.
Components / Signals
Description
Components
Atmel 4MB Flash Memory
Signals
Dual boot support requires two key circuits which are shown in Figure 21; 1) a memory device to store the “Golden”
bit-stream and 2) a delay circuit to prevent reading data from the SPI memory at power-on when the supply is still
ramping up. A simple RC delay circuit is all that is needed to prevent the LPTM21 from reading the “Golden” bitstream from the SPI memory until the supply is stable. The Platform Manager 2 evaluation board is built with the
RC delay circuit attached to the INITN pin. However, either the INITN pin or the PROGRAMN pin can be used to
delay the configuration. Without the delay the LPTM21 and SPI memory may come out of power-on-reset (POR) at
different voltage levels and the data transfer between them can be corrupted causing the configuration to fail. The
37
Platform Manager 2 Evaluation Board
SPI memory (U3) should be connected to the SPI pins of the LPTM21 (U1) with short and similar length traces as
the clock frequency is around 25 MHz. Because the drive strength of the clock and chip select pins on the LPTM21
are similar, the SPI_CLK signal has a more substantial pull-up (R159) than the SPI_CS0 signal (R19) in order to
improve the reliability of the interface with the SPI memory. For more information on the dual boot operation please
see TN1284, Dual Boot and Background Programming with Platform Manager 2.
Figure 21. Dual Boot Circuitry
12 V Buck Converter Operation
A key feature of the LPTM21 (U1) device is the built-in control circuitry to implement a DC-DC Buck converter. It
only takes a few external components connected to the LPTM21 to implement a regulated step-down DC-DC Buck
converter with an output of +3.3 V. The Buck converter can operate with an input voltage ranging from 13.2 V down
to 4.5 V. The components used on the Platform Manager 2 evaluation board are designed for a typical load of 200
mA; this is more than enough power for the on-board devices and one L-ASC10 evaluation board. The components
and signals associated with a Buck converter operation on the Platform Manager 2 evaluation board are listed in
Table 14 below.
38
Platform Manager 2 Evaluation Board
Table 14. Components and Signals for 12 V Buck Converter.
Ref. Des.
Schematic
Sheet
Fast MOSFET Switch
Q1
2
TP0202K-T1-E3 P-Channel MOSFET power switch
for Buck converter operation.
Q1 Driver MOSFET
Q19
2
IRLML2803TRPBF N-Channel MOSFET signal
switch that drives Q1.
Schottky Diode
D2
2
Schottky Diode for Buck converter operation.
Power Inductor
L1
2
270 uH Inductor for Buck converter operation.
Q1 Drive Resistor
R129
2
10 Ohms Resistor, Limits peak drain current for Q19
and sets bias voltage for Q1.
Q1 Drive Resistor
R128
2
100 Ohms Resistor, Sets bias voltage and turns Q1
off quickly.
Components / Signals
Description
Components
Filter Capacitor
C6
2
47 uF Capacitor, output low-pass filter.
Filter Capacitor
C7
2
100 nF Capacitor, output low-pass filter.
RC Filter Resistor
R250
2
2 Ohms Resistor, output low-pass filter.
RC Filter Resistor
R216
2
1 Ohm Resistor, output low-pass filter.
Capacitor
C5
2
35 uF Capacitor, input filter.
Filter Capacitor
C8
2
1 uF Capacitor, input filter.
R226
2
220 Ohms Resistor, limits drive current for PWM signal and reduces Q19 parasitic oscillations.
Q19 Gate Resistor
Fuse
F1
250mA Fast-blow Fuse, Protects Buck converter
from short and +3.3 V loads from over-voltage.
Zener Diode
D48
2
3.9V Zener Diode, protects all 3.3V devices in the
event of short across Q1 or other malfunction where
too high a voltage is applied to the +3.3V bus.
3 x1 Header
J1
2
Jumper to select the board’s +3.3 V source; The Buck
converter output (2-3), The USB regulator (1-2), off
board supply (open).
2 x 1 Header
J3
4
Jumper to connect the +3.3 V Buck converter output
to the LPTM21 supply pins for feedback control of the
PWM. This jumper can also be replaced with an
Ammeter to measure the U1 current during operation.
2
215 kHz Buck converter PWM drive signal output
from the HDRV pin of LPTM21 U1
Signals
PWM
+11.3 V
2, 9, 10
Diode OR’d supply from various +12 V sources. Provides power for Buck converter operation and VDC
pin of LPTM21 U1.
+3.3 V
2, 4,
(All)
The output of the Buck converter is monitored by the
supply pins of U1 to close the feedback loop and
adjust the PWM duty cycle.
39
Platform Manager 2 Evaluation Board
Figure 22. +12V Buck Converter Circuit
The Buck converter circuit shown in Figure 22 shows how a 12V source can be used to provide the 3.3 V required
for the LPTM21 and supporting circuits (external ASC and SPI memory). The circuit is designed to provide approximately 200mA which is more than enough for most Platform Manager 2 demonstrations using this board.
Because this is an evaluation board, and it is likely that component values may be changed, the +3.3 V bus is protected using a 250 mA fast-blow fuse (F1) and 3.9V Zener diode (D48). If the wrong device is installed for Q1 or a
short from drain to source occurs then 11 V or more would be applied to the +3.3 V bus. In such a case, the Zener
diode will limit the voltage and cause the current to exceed the rating of the fuse and the devices on the +3.3 V supply bus will be protected. It is recommended that customer designs include these protection devices (F1 and D48)
at least for prototypes; then in production the fuse could be replaced with a zero Ohm jumper (a resistor in parallel
with the fuse) and the Zener could be left off the board, if cost is an issue. Note that a 3.6V Zener has significant
leakage at 3.3 V which is why the 3.9 V Zener diode is used.
The Buck converter in Figure 22 is powered by +11.3 V because there are numerous +12 V sources on the board
which may or may-not be used as part of a demo design. Thus, all the +12 V sources connect to the +11.3 V bus
with a small diode so the Buck converter can be active no matter where the +12 V is supplied from. The VDC pin of
LPTM21 U1 is powered by the +11.3 V and enables the Buck converter control circuits to drive the external powerswitch (Q1) and monitor the +3.3 V supply pins.
As in most DC-DC converters one design goal is to minimize turn-on and turn-off times of the N-channel power
MOSFET (Q1). This is accomplished in a cost effective manner using low impedance resistors and a P-channel
driver MOSFET (Q19). The 100 Ohms of R128 rapidly drains the charge from the gate of Q1 when Q19 is turned off
which will quickly turn Q1 off. Similarly the 10 Ohms of R129 quickly charges the gate of Q1 for a fast turn on time.
The divider ratio of the two resistors is 1:10. This provides ample bias voltage for Q1 to reach saturation, which is
also a desirable goal in DC-DC converters. By minimizing the turn-on and turn-off times and by driving Q1 into saturation the power loss is low enough that a SOT-23 device can be used as the Buck converter power-switch.
The rest of the Buck converter components (L1, D2, C6, and C7) perform their standard functions. The inductor L1
stores energy when Q1 is on. The ‘catch diode’ D2 provides a low-loss path for the inductor L1 to dump the energy
when Q1 is off. The output filter C6 and C7 hold the energy for the load to use. The unique feature of this output filter is the integration of a two pole low-pass filter. R250 with C6 form a low-pass filter with a corner frequency
40
Platform Manager 2 Evaluation Board
around 1.7 kHz and R216 with C7 form a low pass filter with a corner frequency around 1.6 MHz. The net effect of
the combined filters is a very low ripple (typically less than 30 mV-pp) on the output which is most desirable when
powering the analog circuits within LPTM21 and L-ASC10.
When J1 has the shorting jumper installed on pins 2-3 then the green LED (D44) will indicate that the Buck converter is operational.
Power Supplies
The Platform Manager 2 evaluation board has multiple options to power the board. The power provided over the
USB cable is sufficient for most demos, programming, and evaluation. However, USB is typically only able to supply
5 V at 500 mA. To support evaluations that require more current or higher voltage a variety of connections are available around the board for other power sources and loads. Table 15 lists the components and signals associated
with the power supplies and connections on the Platform Manager 2 evaluation board.
Table 15. Components and Signals for the Power Supplies
Ref. Des.
Schematic
Sheet
USB mini interface
J16
15
USB connecter to provide +5 V for the board operation. Board is functional with this interface.
Low Drop Out (LDO) Linear Regulator
U8
15
Generates +3.3 V supply for the board from the USB
+5 V power.
12 V Buck Regulator
n/a
2
Circuit and components described in DC-DC Converter section.
3 x 1 Header
J1
2
Jumper to select either Buck converter output or LDO
output for +3.3 V supply or neither when using J13.
Phoenix 2-Terminal Screw Connector 1
J13
9
Wire to board connector. For use with a bench supply
for +3.3 V.
2 x 1 Header1
J3
4
Jumper to provide +3.3 V to LPTM21 (U1). Can also
be used as test points to measure current drawn by
U1.
2 x 1 Header1
J4
5
Jumper to provide +3.3 V supply for L-ASC10 (U4).
Can also be used as test points to measure current
drawn by U4.
Coaxial PWR Jack 1
J28
9
External +12 V supply from wall adapter.
Phoenix 2-Terminal Screw Connector 1
J25
9
Dual function. For off-board +12 V hot-swap load or to
provide +12 V from a bench supply to power the
board.
Phoenix 2-Terminal Screw Connector 1
J12
9
Dual function. For off-board +5 V hot-swap load or to
provide +5 V from a bench supply to power the board.
Phoenix 2-Terminal Screw Connector 1
J13
9
To provide +3.3 V from a bench supply to power the
board.
Transient Suppressor
D45
9
Transient Voltage suppressor to protect the board
from inductive spikes.
D37,D46
9
To implement Power Supply OR-ing between +12 V
and +5 V supplies with a minimal voltage drop (typically 0.4 V).
J29
9
Jumper to connect USB +5 V to DCDC3, DCDC4,
DCDC7, DCDC8, ASC Interface, and Fan connectors.
Components / Signals
Description
Components
Schottky Diodes
2 x 1 Header 1
Signals
+3.3 V
2 - 16
3.3 V supply to the whole board
+3.3V_UB_SW
2, 15
3.3 V generated by LDO from USB power.
41
Platform Manager 2 Evaluation Board
Components / Signals
+5 V
+11.3 V
+12 V
Ref. Des.
Schematic
Sheet
8,10,12,
14,16
2, 10
2,8,10,11,
13, 16
Description
Supply for DCDC3, DCDC4, DCDC7, DCDC8, ASC
Interface and Fan connectors. Can be the supply for
built in Buck Converter. Also the load side of the ASC
evaluation board +5 V in a hot swap demo.
Supply to VDC pin of LPTM21 for Buck Converter
operation.
Supply for DCDC1, DCDC2, DCDC5, and DCDC6.
Also supply for built in Buck Converter. Also the load
side of ASC evaluation board +12 V hot swap demo.
1. Not required for customer designs; this is only needed to support demonstrations on the evaluation board.
For most applications the Platform Manager 2 board can simply be powered by the +5 V supply from the USB connection. J29 can be installed to provide power to the DC-DCs for low power loads. D47 is a protection diode for the
USB interface in the event that +5 V is supplied to the board from another source. The Buck Regulator (described
in the previous section) should not be powered from the USB through the series of diodes (D47 and D46). The
combined diode drops with a marginal USB supply may provide too low a Voltage for proper Buck Regulator operation. The Buck Regulator can operate with single Schottky diode drop (D46) when the +5 V bus is powered by J12
or the ASC Interface connectors (discussed in the next section).
When additional power or operation from a bench power supply is required several connectors and jumpers are
available on the Platform Manager 2 board. A variety of options are available for operation from +12 V. Power can
be supplied from J28, J25, or the ASC interface connectors. J25 can also be used to attach an off board load when
+12 V is supplied from the ASC Interface connectors. As shown in Figure 23 a Transient Voltage suppressor [D45]
is mounted on the board to absorb high voltage spikes from either the +12 V supply itself or from inductive spikes
produced from an over-current shut-down by the hot swap circuits on the ASC evaluation board connected to the
ASC Interface connector.
42
Platform Manager 2 Evaluation Board
Figure 23. Platform Manager 2 Evaluation Board Power Supply Connections
To ensure reliable operation of the board, power supply ORing is implemented using diodes D37 and D46 between
+5 V and +12 V supply. The +11.3 V after diode drop from +12 V is connected to VDC input of LPTM21 for Buck
Regulator operation. The Hot swap demonstration might require high current therefore external +5 V should be
used, the +5 V from USB should be disconnected by removing jumper J29.
43
Platform Manager 2 Evaluation Board
ASC Interface Connectors
The Platform Manager 2 evaluation Board has two DB25 connectors that are designed to interface with L-ASC10
evaluation Boards. Table 16 lists the components and signals associated with the interface connectors.
Table 16. Components and Signals for ASC Interface Connectors
Ref. Des.
Schematic
Sheet
DB 25 Pin Connector
J14
10
DSUB 25 pin connector to plug-in ASC2 evaluation
board.
DB 25 Pin Connector
J15
10
DSUB 25 pin connector to plug-in ASC3 evaluation
board.
2 x 1 Header
J31
10
Jumper to bypass the hot swap / soft start circuits and
provide +3.3 V supply for programming ASC2 evaluation board.
2 x 1 Header
J32
10
Jumper to bypass the hot swap / soft start circuits and
provide +3.3 V supply for programming ASC3 evaluation board.
Zero Ohm Jumper
R172 – R179
10
Zero Ohm Resistor. Allows the LED drive signals to
support the ASC evaluation board hot swap signals.
I2C Series Resistor
R257 – R260
10
22 Ohm Resistor. Passive buffer to isolate the ASC
evaluation board and connector from the I2C bus.
Components / Signals
Description
Components
Signals
(See Table 18 for the signal names and descriptions)
The ASC2 interface connector J14 and associated circuitry are shown in Figure 10. The ASC3 interface connector
J15 and associated circuitry are shown in Figure 11. Both circuits include a two pin jumper (J31 and J32) that must
be installed to provide +3.3 V to the interface ASC boards for programming. During programming the HVOUT pins
of U1 and U4 will be in safe state (weak pull down) so Q13 and Q14 will be turned off. Also the jumper must be in
place if the +3.3 V power is provided from an ASC evaluation board; such as in a +12 V hot swap demo. The ASC
Breakout Boards are programmed via the I2C signals on the DB25 connector. The ASC devices are integrated into
the system using the ASC-I/F signals that connect to the FPGA of U1, also on the DB25 connector. The +12 V and
+5 V signals use multiple pins for handling higher currents. Further details of the interface connector pins and signals are provided in Table 17. The ASC interface connectors help demonstrate the concept of scalable architecture
using In-System Programmable Hardware Management Expanders (L-ASC10 devices).
44
Platform Manager 2 Evaluation Board
Table 17. ASC Interface Connector Pin Descriptions
Pin #
Name
Description
1
GND
2
ASC_WDAT
Common ground for all boards.
ASC-I/F Signal – is connected to FPGA PIO and must be assigned in Diamond
3
ASC_RDAT
ASC-I/F Signal – is connected to FPGA PIO and must be assigned in Diamond
4
ASC_WRCLK
ASC-I/F Signal – is connected to FPGA PIO and must be assigned in Diamond
5
MANDATORY_RESET
RESETb signal from ASC evaluation board. Wire-ORed with ASC0 and other
mandatory ASC’s RESETb pins and is connected to FPGA PIO pin and must be
assigned Diamond.
6
GND
7
I2C_WRITE_EN
Connected to GPIO1 on ASC evaluation board for optional ASC Write Protect
feature. It is connected to FPGA PIO and must be assigned in Diamond if this
feature is used.
8
ASC_CLK
8 MHz Clock Output from ASC0. Not used on Platform Manager 2 evaluation
board; LPTM21 uses the 8 MHz clock from internal ASC0.
9
+3.3V
Common +3.3 V supply rail. Can be provided by either ASC evaluation board or
Platform Manager 2 evaluation board.
10
+11.3V
Common +11.3 V supply. It is the pre hot swap supply from ASC evaluation
board and is used by LPTM21 Buck converter. It is generated from multiple diode
ORing supplies both on ASC evaluation board and Platform Manager 2 evaluation board.
11
+12V_HS
Common +12 V supply rail. Output from 12 V hot swap circuit or input for DCDC1
and DCDC2 on ASC evaluation board.
12
+5V_HS
Common +5 V supply rail. Output from 5 V hot swap circuit or input for DCDC3
and DCDC4 on ASC evaluation board.
13
GND
14
ASC_12V_OC_SHUTDOWN
15
12V_OC_SENSE
Common ground for all boards.
Common ground for all boards.
Connected to fast shutoff transistor of 12 V hot swap circuit on ASC evaluation
board. Driven from an output of the FPGA.
Output from ASC HIMONN_HVMON on ASC evaluation board. Used as fast
shutdown alarm for 12 Volt hot swap demo. Connected to an input of the FPGA.
16
GND
17
OPTIONAL_RESET
Common ground for all boards.
18
I2C_SCL
I2C Clock Signal.
19
I2C_SDA
I2C Data Signal.
20
ASC_5V_OC_SHUTDOWN
21
5V_OC_SENSE
22
ASC_BOARD_PRESENT
23
+12V_HS
Common +12 V supply rail. Output from 12V hot swap circuit or input for DCDC1
and DCDC2 on ASC evaluation board.
24
+5V_HS
Common +5 V supply rail. Output from 5V hot swap circuit or input for DCDC3
and DCDC4 on ASC evaluation board.
25
+5V_HS
Common +5 V supply rail. Output from 5V hot swap circuit or input for DCDC3
and DCDC4 on ASC evaluation board.
RESETb signal from ASC evaluation board. Is connected to individual FPGA PIO
and must be assigned in Diamond.
Connected to fast shutoff transistor of 5V hot swap circuit on ASC evaluation
board. Driven from an output of the FPGA.
Output from ASC IMON1 on ASC evaluation board. Used as fast shutdown alarm
for 5 Volt hot swap demo. Connected to an input of the FPGA.
Grounded on ASC evaluation board and connected to an input of the FPGA to
sense when the board is attached or removed.
45
Platform Manager 2 Evaluation Board
I2C Bus
The Platform Manager 2 evaluation board supports an I2C bus with multiple masters, slaves, and connectors. This
bus is used to program the ASC devices, dynamically reconfigure the ASC devices, customize the sequence, and
monitor status and signals. Table 18 lists the components and signals associated with I2C bus on the Platform Manager 2 evaluation board.
Table 18. Components and Signals of I2C Bus.
Ref. Des.
Schematic
Sheet
LPTM21
U1
2, 3, 4
Master: JTAG to I2C bridge is used to program the
ASC devices; also the FPGA logic can read and control the ASC devices from here.
Analog Slave: Programming connection for ASC0.
Logic Slave: Soft I2C interface to the FPGA control
logic.
FT2232H
U6
15
FTDI chip converts USB to either JTAG or I2C based
on the software being used. The ACBUS0 pin can be
used to automatically connect the FTDI pins to the
I2C bus.
R15, R16
3
2k Ohm Resistors. Slightly stronger than typical pullup to match the series and filter resistors used by U1.
Filter Resistors
R180,R181
3
150 Ohm Resistors. Provide an RC low-pass glitch filter with C73 and C72.
Filter Capacitor
C72
3
120 pF Capacitor. About 18 ns delay with R181 for
primary SDA of U1. Slightly shorter delay on Data
than Clock to prevent false re-starts.
Filter Capacitor
C73
3
150 pF Capacitor. About 22.5 ns delay with R180 for
primary SCL of U1. Slightly longer on Clock than
Data to prevent false re-starts.
Series Resistor
R253,R254
3
50 Ohm Resistors. Isolates the filter capacitor from
the I2C pins when U1 is driving the bus, and provides
secondary noise filter when U1 receiving from the
bus.
Filter Resistors
R240,R241
4
150 Ohm Resistors. Provide an RC low-pass glitch
filter with C100 and C101.
Filter Capacitor
C100
4
120 pF Capacitor. About 18 ns delay with R241 for
secondary SDA of U1. Slightly shorter delay on Data
than Clock to prevent false re-starts.
Filter Capacitor
C101
4
150 pF Capacitor. About 22.5 ns delay with R240 for
secondary SCL of U1. Slightly longer on Clock than
Data to prevent false re-starts.
Series Resistor
R251, R252
4
50 Ohm Resistors. Isolates the filter capacitor from
the I2C pins when U1 is driving the bus, and provides
secondary noise filter when U1 receiving from the
bus.
Series Resistors
R20, R21, R232,
R233, R255,
R256,
R257, R258,
R259, R260
2, 3, 5, 6
22 Ohm Resistor. Isolates the bus capacitance from
the I2C pins, provides minor noise filtering, and can
be removed to disconnect selected devices from the
bus; either for development or debugging.
U10, U11
3
Used to disconnect the FTDI I2C pins from the bus
during programming.
J33
3
When installed enables FTDI I2C interface.
Components / Signals
Description
Components
Pull Up Resistors
Analog Mux
2- pin header
46
Platform Manager 2 Evaluation Board
Ref. Des.
Schematic
Sheet
NPN Transistor – SOT-23
Q42
15
2N3904 NPN Transistor drives LED (D57) on when
FTDI pins are connected to the I2C bus.
Red LED
D57
15
Illuminates to indicate the FTDI pins are connected to
the I2C bus.
LED Bias Resistor
R264
15
470 Ohm Resistor. Limits the current in D57.
NPN Bias Resistor
R263
15
4.7k Ohm Resistor. Limits the base current of Q42.
Components / Signals
Description
Signals
USB_I2C_EN
3, 15
FTDI I2C MUX control signal. High to connect the
FTDI I2C pins to the bus; Low to isolate the FTDI I2C
pins from the bus. Controlled by U6 and software or
J33.
3, 15
FTDI I2C bus signals.
2, 3, 5, 10
I2C bus signals.
FTDI_SDA,
FTDI_SCL
I2C_SCL,
I2C_SDA
Programming the ASC Devices
The primary function of the I2C bus on the Platform Manager 2 evaluation board is to program the on-board and offboard ASC devices. Diamond Programmer will send the programming data over the USB connection (J16) to the
FTDI (U6) device which drives the JTAG signals into the LPTM21 (U1). The LPTM21 device has a JTAG to I2C
bridge that translates the data from the JTAG connections to the I2C Master in Bank 0 (note JTAG signals are not
shown in Figure 22 to place focus on the I2C Bus route). The following ASC devices can be programmed Via I2C:
ASC0 within U1, ASC1 (U4), ASC2 via J14, and ASC3 via J15. The I2C pins of the FTDI (U6) device are not fully
I2C compliant. Specifically they do not support multi-master mode and must be disconnected from the bus when
not in use. That is the function of two solid state switches U10 and U11; they only connect the FTDI I2C pins to the
bus when U6 is the master.
Demo and Debugging Software
The I2C Demo and Debugging Software for the Platform Manager 2 evaluation board is available for download from
the Lattice website. This software automatically drives the USB_I2C_EN signal to connect the FTDI I2C pins to the
bus. The software configures the FTDI (U6) device to translate USB to I2C. The LED (D57) illuminates when the
software is actively driving the I2C bus. Using the FTDI (U6) as the I2C master the software can read and write the
ASC registers and communicate with the slave port in Bank 1 of the LPTM21 (U6) device as shown in Figure 24.
Customer based software that does not automatically drive the USB_I2C_EN can still be supported by installing
J33 to force the MUX to connect the I2C pins to the bus. Alternatively, an off board I2C master can be connected to
the bus using J26. Note that neither J33 nor an off board I2C master should be active when programming the board
via USB / JTAG.
47
Platform Manager 2 Evaluation Board
Figure 24. I2C Bus Route
J26
I2C / SPI
Header
+3.3V
USB_I2C_EN
R262
R255
R256
1k
J33
(2-Pin Header)
U6
FTDI
R126
R127
22
0
+3.3V
R257
R258
J14
ASC2
22
R15
R16
R202
U10, U11
10k
R259
R260
2k
R20
R21
U1
Bank 0
R180, R181
(Master)
150
Bank Analog
J15
ASC3
22
22
U4
ASC1
R232, R233
(ASC0 Slave)
22
Bank 1
R240, R241
(Slave)
150
VID Control
Another function of the I2C bus is to support the VID feature of the Platform Manager 2 system. The VID feature
(described in the VID Section above) uses the I2C port in Bank 0 of U1 as the master to send target voltage data to
the respective ASC devices. Note that when using the VID feature J33 should not be installed and the I2C Demo
Debugging software should not be used as bus contentions may occur.
Dual Boot Control
The I2C bus can also be used to support the Dual Boot feature of the Platform Manager 2 system. The Dual Boot
feature uses the I2C port in Bank 0 of U1 as the master to send configuration information to all the ASC devices in
the system. Note that when using the Dual Boot feature J33 should not be installed and the I2C Demo Debugging
software should not be used as bus contentions may occur.
48
Platform Manager 2 Evaluation Board
Figure 25. I2C Noise Filter Circuit
Filters and Series Terminations
Throughout the I2C bus route shown in Figure 24 most of the devices are connected to the I2C bus either by a filter
or series termination resistor. The noise filter is shown in Figure 25 and is an effective compromise to the 50 ns
glitch filter called for in the I2C specification. This is because a full 50 ns low-pass filter results in too slow a rise time
for the signals at the inputs of the FPGA. The 150 Ohm resistors with the capacitors values correspond to 18 ns to
22.5 ns which is enough filtering to block most of the high frequency noise. The data (I2C_SDA) has a shorter
delay than the clock (I2C_SCL) by design to prevent false re-starts. False re-starts can occur when the rising edge
of the data and clock happen at the same time with certain data patterns. The I2C pins of the FTDI (U6) device and
external software based interfaces tend to drive the clock and data transitions at the same time, so the offset in
delays prevents false re-starts. The 50 Ohm series resistors provide a second low-pass filter of about 0.8 ns using
the input capacitance of the FPGA pins. More importantly the 50 Ohm resistor isolates the filter capacitor and limits
the current when the FPGA is driving the bus. All of the slave devices and connectors also have a 22 Ohm series
resistor on both the data and clock lines. These series resistors have multiple benefits. First, they isolate the slave
device from having to drive the capacitance of the bus and they also minimize the effect of adding more pin capacitance to the bus; so it works both ways. Furthermore, series resistors are easier to remove than a slave device
when debugging an I2C issue.
49
Platform Manager 2 Evaluation Board
Miscellaneous
The Platform Manager 2 evaluation board has other significant components used for indication, status information,
and control in various designs by the user. These components and signals are listed in Table 19 below.
Table 19. Components and Signals for Miscellaneous Operation.
Ref. Des.
Schematic
Sheet
U5
7
LCD 3-Digit display driven by LPTM21 (U1) for demonstration purpose. See Appendix D and E for connections.
LED_1 to LED_15
D22 – D36
7
LEDs Red (15) for demonstration purpose connected
to LPTM21 (U1 BANK1 and BANK3) on the board.
See Appendix D and E for connections.
A0_LED1 to A0_LED10
D3 – D12
7
LEDs Red (10) for demonstration purpose connected
to LPTM21 (U1 ASC section) on the board.
A1_LED1 to A1_LED10
D13 – D21
7
LEDs Red (9) for demonstration purpose connected
to L-ASC10 (U4) on the board. Note A1_LED7 and
GPIO7 do not exist.
Push Button Switches
SW4, SW3
6
Switches push button (2) connected to LPTM21 on
BANK2. The nets have pull-up resistors. See Appendix D and E for connections.
Push Button Switch
SW1
6
Switch push button connected to GPIO10 of ASC0
(ASC section of LPTM21 U1). The net is shared by
A0_LED10 and has a pull-up resistor.
Push Button Switch
SW5
6
Switch push button connected to GPIO10 of ASC1
(U4). The net is shared by A1_LED10 and has a pullup resistor.
Components / Signals
Description
Components
LCD
Signals
Ordering Information
Description
Ordering Part Number
Platform Manager 2 Evaluation Board
China RoHS Environment-Friendly
Use Period (EFUP)
LPTM-BPM-EVN
Technical Support Assistance
Submit a technical support case via www.latticesemi.com/techsupport.
Revision History
Date
Version
June 2015
1.0
Change Summary
Initial release.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
50
Platform Manager 2 Evaluation Board
Appendix A. Bill of Materials (Installed)
Table 20. Bill of Materials - Populated on Evaluation Board
Reference
Designator
Quantity
Description
Package
Manufacturer
Part Number
ICs
1
U1
Platform Manager 2 Device
1
U3
4 Mbit Flash Device
1
U4
ASC Device
1
U5
LCD 3 Digit
1
U6
High Speed USB
Interface
FTBGA-237
Lattice
Semiconductor
LPTM21-1AFTG237C
UDFN-8
Adesto Technologies
AT25DF041A-MH-T
TQFN-48
Lattice
Semiconductor
L-ASC10-1SG48I
LCD_301
Lumex Opto
LCD-S301C31TR
TQFP-64
FTDI
FT2232HL-REEL
1
U7
1 Kbit EEPROM
SOIC-8
ST Microelectronics
M93C46-WMN6TP
1
U8
3.3 V LDO Regulator 1 A
SOT223
On Semi
NCP1117ST33T3G
1
U9
3.3 V LDO Regulator 0.3 A
5STOP
NXP
LD6836TD/33P
2
U10,U11
Dual Analog Switch
6-TSSOP
Fairchild
FSA4157P6X
Capacitors
2
C55,C56
18 pF 50 V 5% NP0
SM_C_0603
Kemet
C0603C180J5GACTU
2
C73,C101
120 pF 50 V 5% NP0
SM_C_0603
Samsung
CL10C121JB8NNNC
6
C1,C2,C24,
C25,C72,C100
150 pF 50 V 5% NP0
SM_C_0603
Murata
GRM1885C1H151JA01D
9
C26,C47,C48,
C82,C85,C94,
C97,C103,C104
10 nF 50 V 10% X7R
SM_C_0603
Kemet
C0603C103K5RACTU
36
C4,C9,C10,C11,C12, 100 nF 16 V 10% X7R
C13,C14,
C15,C16,C17,
C18,C19,C20,
C21,C22,C23,
C50,C52,C53,
C54,C57,C62,
C63,C64,C65,
C66,C67,C68,
C83,C84,C86,
C87,C95,C96,
C98,C99
SM_C_0603
Murata
GRM188R71C104KA01D
1
C69
220 nF 16 V 10% X7R
SM_C_0603
Murata
GRM188R71C224KA01D
1
C58
330 nF 16 V 10% X7R
SM_C_0603
Murata
GRM188R71C334KA01D
3
C8,C70,C71
1 uF 16 V 10% X5R
SM_C_0603
Murata
GRM188R61C105KA93D
1
C74
2.2 uF 16 V 10% X7R
SM_C_1206
Kemet
C1206C225K4RACTU
1
C51
3.3 uF 10 V 10% Tantalum
SM_C_1206
Kemet
T491A335K010AT
1
C49
4.7 uF 10 V 10% Tantalum
SM_C_1206
Kemet
T491A475K010AT
1
C61
6.8 uF 16 V 10% Tantalum
SM_C_1206
Kemet
T491A685K016AT
1
C102
10 uF 10 V 10% X7R
SM_C_0603
Kemet
C0603C104K8RACTU
1
C75
10 uF 16 V 10% X5R
SM_C_1206
Kemet
C1206C106K4PACTU
1
C60
10 uF 10 V 10% Tantalum
SM_C_1206
Kemet
T491A106K010AT
8
C35,C36,C37,
C38,C43,C44,
C45,C46
22 uF 10 V 20% Tantalum
SM_C_1206
Kemet
T491A226M010AT
1
C5
33 uF 25 V 20% Aluminum
SM_C_Can
Panasonic
EEE-FP1E330AP
2
C6,C59
47 uF 16 V 20% Aluminum
Thru Hole
Panasonic
ECE-A1CKS470
EEE-FP1E470AP
1
C27
47 uF 25 V 20% Aluminum
SM_C_Can
Panasonic
1
C28
220 uF 25 V 20% Aluminum
SM_C_Can
Rubycon
25YXG220MEFC6.3X11
2
C29,C30
330 uF 10 V 20% Aluminum
SM_C_Can
Rubycon
10ZLH330MEFC6.3X11
51
Platform Manager 2 Evaluation Board
Reference
Designator
Quantity
Description
Package
Manufacturer
Part Number
Diodes
1
D2
MicroSMP
Vishay
MSS1P3L-M3/89A
35
D3,D4,D5,D6,D7,D8, Red LED Clear
D9,D10,D11,D12,
D13,D14,D15,D16,
D17,D18,D19,D20,
D21,D22,D23,D24,
D25,D26,D27,D28,
D29,D30,D31,D32,
D33,D34,D35,D36,
D57
Schottky 30 V 1 A
SM_LED_0603
Lite-On
LTST-C190KRKT
7
D39,D40,D44,
D51,D52,D55,
D56
Green LED Clear
SM_LED_0603
Lite-On
LTST-C190GKT
1
D42
Blue LED Clear
SM_LED_0603
Lite-on
LTST-C191TBKT
1
D45
22 V 600 W 5% TVS
DO-214AA
Bourns
SMBJ22CA
6
D37,D38,D41,
D43,D46,D47
Schottky 30 V 0.5 A
SOD_923
On Semiconductor
NSR0530P2T5G
1
D48
3.9 V 5W Zener
Thru Hole
ON Semiconductor
1N5335BRLG
6
J1,J5,J6,J8,J27,J30
3 Pin Header
Header_3X1
Molex
22-28-4364
4
J3,J4,J29,J31,
J32
2 Pin Header
Header_2X1
Molex
22-28-4364
2
J7,J9
3 Pin Connector
Header_3X1
Molex
22272031
2
J10,J11
6 Pin Connector
Header_6X1
Molex
22272061
2
J14,J15
25 Pin D-SUB PLUG R/A
Thru Hole
TE Connectivity
5747842-3
1
J16
Mini USB RCPT RA
Type B
SMD
TE Connectivity
1734035-2
5
J12,J13,J19,J23,J25
2 Pin Terminal Block
Thru Hole
Phoenix Contact
1727010
2
J20,J24
4 Pin Terminal Block
Thru Hole
Phoenix Contact
1727036
1
J28
Power Jack 2.1 mm X 5.5 mm
High Cur.
Thru Hole
CUI Inc
PJ-102AH
11
J1,J3,J4,J5,J6,J8,
J27,J29,J30,J31,J32
Shorting Jumper
N/A
3M
929957-08
Q1
MOSFET P-CH 30 V
385 mA
SOT-23
Vishay Siliconix
TP0202K-T1-E3
Jumpers
Transistors
1
2
Q2,Q3
MOSFET P-CH 20 V 3.7 A
SOT-23
IR
IRLML6402TRPBF
2
Q4,Q6
PNP
SOT-23
Fairchild
MMBT3906
8
Q5,Q7,Q8,Q36,Q37,
Q40,Q41,Q42
NPN
SOT-23
Fairchild
MMBT3904
6
Q10,Q11,Q12,Q13,
Q14,Q43
MOSFET N-CH 60 V 4 A
SOT-23
Fairchild
NDT3055L
4
Q48,Q49,Q54,Q55
MOSFET N-CH 25 V
220 mA
SOT-23
Fairchild
FDV301N
20
R122,R123,R124,
R125,R126,R127,
R172,R173,R174,
R175,R176,R177,
R178,R179,R199,
R200,R201,R217,
R248,R261
Zero Ohm jumper
SM_R_0603
Panasonic
ERJ-3GEY0R00V
2
R54,R57
0.02 Ohm 1/4 W 1%
SM_R_1206
Yageo
PF1206FRF070R02L
1
R216
1.0 Ohm 1/10 W 1%
SM_R_0603
Panasonic
ERJ-3RQF1R0V
3
R182,R239,R250
2.0 Ohm 1/10 W 1%
SM_R_0603
Panasonic
ERJ-3RQF2R0V
1
R203
2.7 Ohm 1 W 5%
Thru Hole
Panasonic
ERX-1SJ2R7A
1
R129
10 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ100V
10
R20,R21,R232,R233, 22 Ohm 1/10 W 5%
R255,R256,R257,
R258,R259,R260
SM_R_0603
Panasonic
ERJ-3GEYJ220V
4
R251,R252,R253,
R254,
SM_R_0603
Panasonic
ERJ-3GEYJ500V
Resistors
50 Ohm 1/10 W 5%
52
Platform Manager 2 Evaluation Board
Reference
Designator
Quantity
Description
Package
Manufacturer
Part Number
19
R10,R11,R12,R13,
R14,R29,30,R31,
R59,R120,R128,
R245,R246,R247,
R249
100 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ101V
4
R180,R181,R240,
R241
150 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ151V
1
R226
220 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ221V
12
R1,R2,R3,R4,R6,
270 Ohm 1/10 W 5%
R7,R8,R23,R24,R25,
R26,R28
SM_R_0603
Panasonic
ERJ-3GEYJ271V
2
R89,R117
330 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ331V
13
R55,R60,R82,R110,
R121,R185,R186,
R189,R190,R212,
R214,R228,R264
470 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ471V
1
R9
680 Ohm 0.5 W 1%
SM_R_1206
Vishay Dale
CRCW1206680RFKEAHP
12
R34,R36,R39,R41,
R42,R56,R61,R68,
R96,R159,R244,
R262
1 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ102V
1
R44
1 kOhm 1/4 W 5%
SM_R_0603
Rohm
ESR03EZPJ102
4
R33,R35,R38,R40
1 kOhm Slide Pot
Thru Hole
Taiwan Alpha Elect.
RA2043F-20-10EB1-B1K
2
R15,R16
2 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ202V
4
R27,R34,R119,R230
2.2 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ222V
9
RN3,RN4,RN5,RN6, 2.2 kOhm Array
RN7,RN8,RN9,RN10,
RN11
SM_ 2512
CTS
745C101222JP
10
R17,R18,R158,R160, 4.7 kOhm 1/10 W 5%
R161,R193,R194,
R197,R198,R263
SM_R_0603
Panasonic
ERJ-3GEYJ472V
2
R77,R105
6.34 kOhm 1/8 W 1%
SM_R_0805
Panasonic
ERJ-6ENF6341V
22
R5,R19,R22,R37,
R43,R45,R46,R47,
R48,R49,R50,R51,
R164,R165,R168,
R169,R171,R202,
R236,R237,R242,
R243
10 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ103V
1
RN1
10 kOhm Array
SM_ 2512
CTS
745C101103JP
4
R78,R79,R106,R107
11.0 kOhm 1/8 W 1%
SM_R_0805
Panasonic
ERJ-6ENF1102V
1
R231
12 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ123V
4
R85,R86,R113,R114
19.6 kOhm 1/8 W 1%
SM_R_0805
Panasonic
ERJ-6ENF1962V
2
R84,R112
20.0 kOhm 1/8 W 1%
SM_R_0805
Panasonic
ERJ-6ENF2002V
2
R235,R265
100 kOhm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ104V
1
R118
1M Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ105V
DCDC3,DCDC4,
DCDC7,DCDC8
5V In, 0.6 V-5.5 V Out 2 A
Thru Hole
GE Critical Power
NQR002A0X4Z
F1
FAST ACT 125 V 0.25 A
Thru Hole
Littelfuse Inc.
F5533CT
DC-DC Converters
4
Fuse
1
Inductors
1
L1
270 uH 0.4 A 10%
SM 10 mm x 10 mm
Bourns Inc.
PM105SB-271K-RC
2
L2,L3
Ferrite Bead 600 Ohm
SM_FB_0603
TDK Corp.
MPZ1608S601A
5
SW1,SW2,SW3,
SW4,SW5
Tactile SPST-NO 0.02 A 15 V
SMT_SW
Panasonic
EVQ-Q2K03W
1
SW6
8 Pos Dip Sw
Thru Hole
CTS
195-8MST
X1
12 MHz
SM_XTAL
TXC
7M-12.000MAAJ-T
Switches
Crystal
1
53
Platform Manager 2 Evaluation Board
Appendix B: Bill of Materials (Not installed)
Table 21. Bill of Materials – Not Populated on Evaluation Board
Quantity
Reference
Designator
Description
Package
Manufacturer
Part Number
Capacitors
4
C76,C79,C88,C91
10 nF 50 V 10% X7R
SM_C_0603
Kemet
C0603C103K5RACTU
8
C77,C78,C80,C81,
C89,C90,C92,C93
100 nF 16 V 10% X7R
SM_C_0603
Murata
GRM188R71C104KA01D
4
C31,C33,C39,C41
22 uF 16 V 20% Tantalum
SM_C_2413
Kemet
T491C226M016ZT
4
C32,C34,C40,C42
22 uF 10 V 20% Aluminum
SM_C_1206
Kemet
T491A226M010AT
D49,D50,D53,D54
Green LED Clear
SM_LED_0603
Lite-On
LTST-C190GKT
1
J33
2 Pin Header
Header_2X1
Molex
22-28-4364
2
J2,J26
8 Pin Header
Header_8X1
Molex
22-28-4364
1
J35
10 Pin Header
Header_5X2
Molex
22-28-4364
4
Q34,Q35,Q38,Q39
NPN
SOT-23
Fairchild
MMBT3904
9
Q15,Q16,Q17,Q18,
Q19,Q45,Q47,Q51,
Q53
MOSFET N-CH 25 V 220 mA
SOT-23
Fairchild
FDV301N
8
Q20,Q21,Q22,Q23,
Q24,Q25,Q26,Q27
Prototype1
SOT-23
2
Q32,Q33
Prototype1
SOT-223
4
Q28,Q29,Q30,Q31
Prototype1
SOIC-8
2
R170,R238
Zero Ohm jumper
SM_R_0603
Panasonic
ERJ-3GEY0R00V
4
R183,R184,R187,
R188
470 Ohm 1/10 W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ471V
2
R75,R103
680 Ohm 1/10 W 1%
SM_R_0603
Panasonic
ERJ-3GEYJ681V
24
R132,R133,R134,
R135,R136,R137,
R138,R139,R140,
R141,R142,R143,
R144,R145,R146,
R147,R150,R151,
R152,R153,R154,
R155,R156,R157
Prototype1
SM_R_0805
4
R130,R131,R148,
R149
Prototype1
SM_R_2512
4
R191,R192,R195,
R196
4.7 kOhm 1/10W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ472V
8
R162,R163,R166,
R167,R213,R215,
R227,R229
20 kOhm 1/10W 5%
SM_R_0603
Panasonic
ERJ-3GEYJ203V
24
R62,R66,R67,R69,
R73,R74,R76,R80,
R81,R83,R87,R88,
R90,R94,R95,R97,
R101,R102,R104,
R108,R109,R111,
R115,R116
Open2
SM_R_0805
2
R63,R91
2.74 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF2741V
2
R70,R98
4.42 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF4421V
4
R64,R65,R92,R93
5.60 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF5601V
4
R71,R72,R99,R100
8.02 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF8061V
2
R205,R219
23.7 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF2372V
2
R207,R221
36.5 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF3652V
2
R209,R223
54.9 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF5492V
2
R211,R225
84.5 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF8452V
4
R204,R206,R208,
R210
130 kOhm 1/8 W 1%2
SM_R_0805
Panasonic
ERJ-6ENF1303V
Diodes
4
Jumpers
Transistors
Resistors
54
Platform Manager 2 Evaluation Board
4
R218,R220,R222,
R224
200 kOhm 1/8 W 1% 2
SM_R_0805
12 V In – User selected
5 Pin SIP
Panasonic
ERJ-6ENF2003V
DC-DC Converters
4
DCDC1,DCDC2,
DCDC5,DCDC6
1. Prototype mounting pads for “blue wire” connections to user defined transistors, resistors, inductors, capacitors, and diodes.
2. Values subject to user selected DC-DC type and output; use Platform Designer to calculate values based on output voltage.
55
Platform Manager 2 Evaluation Board
Appendix C: Predefined Preference File Listing
// These names are generated by the software and can be copied into the
// preference file
// ASC0 Connections
LOCATE COMP "ASC0_RSTN" SITE "M8" ;
// ASC1 Connections
LOCATE COMP "ASC1_RSTN_I" SITE "C8" ;
LOCATE COMP "rdat_1" SITE "B7" ;
LOCATE COMP "wdat_1" SITE "C7" ;
LOCATE COMP "wrclk_1" SITE "A7" ;
// ASC2 Connections
LOCATE COMP "ASC2_RSTN_I" SITE "C5" ;
LOCATE COMP "rdat_2" SITE "B6" ;
LOCATE COMP "wdat_2" SITE "B5" ;
LOCATE COMP "wrclk_2" SITE "A4" ;
// ASC3 Connections
LOCATE COMP "ASC3_RSTN_I" SITE "N5" ;
LOCATE COMP "rdat_3" SITE "T2" ;
LOCATE COMP "wdat_3" SITE "P3" ;
LOCATE COMP "wrclk_3" SITE "R4" ;
56
Platform Manager 2 Evaluation Board
Appendix D: User Defined Preference File Listing
// These names follow the Platform Manager 2 Evaluation Board schematic but,
// they may be defined by the user. Thus, they can be copied into the preference
// file and edited to match a different naming convention if needed.
// LED
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
Connections
COMP "LED1"
COMP "LED2"
COMP "LED3"
COMP "LED4"
COMP "LED5"
COMP "LED6"
COMP "LED7"
COMP "LED8"
COMP "LED9"
COMP "LED10"
COMP "LED11"
COMP "LED12"
COMP "LED13"
COMP "LED14"
COMP "LED15"
// LCD
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
Connections
COMP "LCD_COM"
COMP "LCD_1E"
COMP "LCD_1D"
COMP "LCD_1C"
COMP "LCD_DP1"
COMP "LCD_2E"
COMP "LCD_2D"
COMP "LCD_2C"
COMP "LCD_DP2"
COMP "LCD_3E"
COMP "LCD_3D"
COMP "LCD_3C"
COMP "LCD_3B"
COMP "LCD_3A"
COMP "LCD_3F"
COMP "LCD_3G"
COMP "LCD_2B"
COMP "LCD_2A"
COMP "LCD_2F"
COMP "LCD_2G"
COMP "LCD_1B"
COMP "LCD_1A"
COMP "LCD_1F"
COMP "LCD_1G"
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
"D3"
"B2"
"C2"
"C1"
"P4"
"R5"
"P5"
"T4"
"M7"
"P7"
"P8"
"N8"
"E8"
"D8"
"R7"
"T7"
"P6"
"N6"
"R6"
"N7"
"B1"
"E4"
"R1"
"P1"
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
// VID
LOCATE
LOCATE
LOCATE
LOCATE
Connections
COMP "VIDA_1"
COMP "VIDA_2"
COMP "VIDA_3"
COMP "VIDA_4"
SITE
SITE
SITE
SITE
"K2"
"K3"
"J3"
"J2"
;
;
;
;
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
"B10"
"N9"
"E9"
"E10"
"D11"
"C11"
"C10"
"D10"
"M2"
"N2"
"N1"
"M1"
"L2"
"L3"
"L1"
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
57
Platform Manager 2 Evaluation Board
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
COMP
COMP
COMP
COMP
COMP
"VIDA_5"
"VIDA_6"
"VIDA_7"
"VIDA_8"
"VIDA_SW"
SITE
SITE
SITE
SITE
SITE
// FAN
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
LOCATE
Connections
COMP "FAN1_TACH"
COMP "FAN1_PWM"
COMP "FAN2_TACH"
COMP "FAN2_PWM"
COMP "FAN3_TACH"
COMP "FAN3_PWM"
COMP "FAN4_TACH"
COMP "FAN4_PWM"
// DCDC Connections
LOCATE COMP "DCDC1_SYNC”
LOCATE COMP "DCDC2_SYNC”
LOCATE COMP "DCDC3_SYNC”
LOCATE COMP "DCDC4_SYNC”
LOCATE COMP "DCDC5_SYNC”
LOCATE COMP "DCDC6_SYNC”
LOCATE COMP "DCDC7_SYNC”
LOCATE COMP "DCDC8_SYNC”
"H2"
"H3"
"G3"
"G2"
"K1"
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
SITE
;
;
;
;
;
"E2"
"D2"
"D1"
"E1"
"F2"
"F3"
"F1"
"G1"
;
;
;
;
;
;
;
;
“N10” ;
“P10” ;
“P9” ;
“R10” ;
“L10” ;
“T10” ;
“M9” ;
“M10” ;
// ASC2 Hot-Swap Connections
LOCATE COMP “ASC2_BOARD_SENSE” SITE “D5” ;
// Note: Overcurrent signals share the LED I/O.
LOCATE COMP “A2_5V_OVERCURRENT_SENSE”
SITE “C10”
LOCATE COMP “A2_5V_OVERCURRENT_SHUTDOWN” SITE “L3”
LOCATE COMP “A2_12V_OVERCURRENT_SENSE”
SITE “M1”
LOCATE COMP “A2_12V_OVERCURRENT_SHUTDOWN” SITE “L2”
;
;
;
;
//
//
//
//
LED_7
LED_14
LED_12
LED_13
// ASC3 Hot-Swap Connections
LOCATE COMP “ASC3_BOARD_SENSE” SITE “E6” ;
// Note: Overcurrent signals share the LED I/O.
LOCATE COMP “A3_5V_OVERCURRENT_SENSE”
SITE “N1”
LOCATE COMP “A3_5V_OVERCURRENT_SHUTDOWN” SITE “N2”
LOCATE COMP “A3_12V_OVERCURRENT_SENSE”
SITE “D10”
LOCATE COMP “A3_12V_OVERCURRENT_SHUTDOWN” SITE “M2”
;
;
;
;
//
//
//
//
LED_11
LED_10
LED_8
LED_9
// Misc Connections
LOCATE COMP "PIO3_PB_SW3" SITE "T9" ;
LOCATE COMP "MANUAL_RESTART_SW4" SITE "M6" ;
LOCATE COMP “I2C_WRITE_PROTECT” SITE “M5” ;
58
59
4
3
2
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
Title
System Block Diagram and Table of Contents
1
Sheet
C
C
Schematic Rev
Board Rev
1
of 16
A
A
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
B
B
5
Contents
1
C
2
C
3
D
4
D
5
Platform Manager 2 Evaluation Board
Appendix E: Schematics
Figure 26. System Block Diagram and Table of Contents
60
A
B
C
D
(6) TEMP_SENSE2N
(6) TEMP_SENSE1N
(6) TEMP_SENSE2P
(6) TEMP_SENSE1P
100
100
100
R10
R11
R12
5
(8,9,10,11,13,16) +12V
(5,10) ASC3_3V_SOFTS
(10) ASC2_3V_SOFTS
(9,15) +5V_USB_SW
C2
150pF
C1
150pF
270
270
680
R7
R8
R9
A0_GS_VMON3
A0_GS_VMON2
A0_GS_VMON1
270
R6
(9,10) +11.3V
(10) ASC2_IMONP
(10) ASC2_IMONN
(6) POT1
(6) POT2
(6,9,12) OUT_DCDC4
(9,12) A0_VMON4
(9) A0_GS_VMON4
(9,12) OUT_DCDC3
(9,11) OUT_DCDC2
(9,11) OUT_DCDC1
(3,4,5,10) I2C_SDA
(3,4,5,10) I2C_SCL
(3,5,10) I2C_WRITE_PROTECT
270
270
270
R3
R4
PWM
R226
220
A0_HVMON
A0_VMON9
A0_VMON6
A0_VMON5
270
R2
22
R233
0
R1
22
R232
R170
4
Q19
FDV301N
R129
10
R128
100
A0_LED1
4
Q1
A11
D13
P16
R16
L15
M15
K16
L16
H16
J16
G15
E15
E16
C16
B16
T13
T14
R14
P14
T15
R15
P15
N15
P11
B11
F11
G11
BANK_ANALOG
C8
1uF
RESETb
TRIM1
TRIM2
TRIM3
TRIM4
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
HVOUT1
HVOUT2
HVOUT3
HVOUT4
L1
270uH
3
C6
47uF
R250
2
R216
1
F13
B15
A15
F14
G14
A14
F12
E13
G12
B13
C12
B12
R11
M11
N11
D12
C13
K11
L11
C7
100nF
Connect with thick traces
(30 mils minimum)
Close to each other
On top side of the board.
LPTM21-FTG237
HDRV
VDC
VMON1
VMON1GS
VMON2
VMON2GS
VMON3
VMON3GS
VMON4
VMON4GS
VMON5
VMON6
VMON7
VMON8
VMON9
HIMONP
HIMONN_HVMON
IMON1P
IMON1N
TMON1P
TMON1N
TMON2P
TMON2N
ASCCLK
NC_FT1
NC_FT2
NC_FT3
SCL
SDA
U1A
D2
MSS1P3L-M3/89A
+11.3V
TP0202K-T1-E3
C5
33uF
25V
PWM
A0_VMON9
A0_HIMON
A0_HVMON
A0_VMON1
A0_GS_VMON1
A0_VMON2
A0_GS_VMON2
A0_VMON3
A0_GS_VMON3
A0_VMON4
A0_GS_VMON4
A0_VMON5
A0_VMON6
ASC0_CLK
ASC0_WDAT
ASC0_RDAT
ASC0_WRCLK
P12
N12
3
R5
10k
J1
HEADER 3
+3.3V
A0_LED1
A0_LED2
A0_LED3
A0_LED4
A0_LED5
A0_LED6
A0_LED7
A0_LED8
A0_LED9
A0_LED10
A0_HVOUT1
2
(11)
(11)
(12)
(12)
2
D48
3.9V
1N5335BRLG
+3.3V_USB_SW (15)
LPTM2_RESETb (3,5,10)
TRIM_DCDC1
TRIM_DCDC2
TRIM_DCDC3
TRIM_DCDC4
A0_LED[1:10] (6,7,11,12)
ENABLE_ASC2_3.3V (10)
ENABLE_ASC3_3.3V (10)
A0_HVOUT4 (6)
R121
470
D44
Green
SM_LED_0603
F1
F5533CT
250 mA
3
2
1
5
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
Title
LPTM21 Analog Connections
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
C
C
Schematic Rev
Board Rev
2
of 16
A0_GPIO1
A0_GPIO2
A0_GPIO3
A0_GPIO4
A0_GPIO5
A0_GPIO6
A0_GPIO7
A0_GPIO8
A0_GPIO9
A0_GPIO10
A0_LED1
A0_LED2
A0_LED3
A0_LED4
A0_LED5
A0_LED6
A0_LED7
A0_LED8
A0_LED9
A0_LED10
+3.3V (3,4,5,6,7,8,9,10,11,12,13,14,16)
A0_HVOUT1
A0_HVOUT2
A0_HVOUT3
A0_HVOUT4
A0_TRIM1
A0_TRIM2
A0_TRIM3
A0_TRIM4
A0_TMON1P
A0_TMON1N
A0_TMON2P
A0_TMON2N
A0_HIMONP
A0_HIMONN_HVMON
A0_IMON1P
A0_IMON1N
A0_VMON1
A0_VMON1_GS
A0_VMON2
A0_VMON2_GS
A0_VMON3
A0_VMON3_GS
A0_VMON4
A0_VMON4_GS
A0_VMON5
A0_VMON6
A0_VMON7
A0_VMON8
A0_VMON9
A0_WDAT
A0_RDAT
A0_WRCLK
A0_RESET
A0_CLK
LDRV
PWM
A0_HVOUT1
ENABLE_ASC2_3.3V
ENABLE_ASC3_3.3V
A0_HVOUT4
TRIM_DCDC1
TRIM_DCDC2
TRIM_DCDC3
TRIM_DCDC4
TEMP_SENSE1P
TEMP_SENSE1N
TEMP_SENSE2P
TEMP_SENSE2N
A0_HIMON
A0_HVMON
ASC2_IMONP
ASC2_IMONN
A0_VMON1
A0_GS_VMON1
A0_VMON2
A0_GS_VMON2
A0_VMON3
A0_GS_VMON3
A0_VMON4
A0_GS_VMON4
A0_VMON5
A0_VMON6
POT1
POT2
A0_VMON9
ASC0_WDAT
ASC0_RDAT
ASC0_WRCLK
LPTM2_RESETb
ASC0_CLK
LDRV
PWM
1
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 27. LPTM21 Analog Connections
61
A
B
C
D
+3.3V
(15) USB_TCK
(15) USB_TMS
(15) USB_TDO
(15) USB_TDI
5
R18
4.7k
R17
4.7k
+3.3V
1
2
3
4
5
6
7
8
J2
JTAG
(6) MANUAL_RESTART
(2,5,10) I2C_WRITE_PROTECT
(10) ASC3_WDAT
(10) ASC3_RDAT
(10) ASC3_WRCLK
(10) ASC3_RESET
(10) ASC2_WDAT
(10) ASC2_RDAT
(10) ASC2_WRCLK
(10) ASC2_RESET
(5) ASC1_WDAT
(5) ASC1_RDAT
(5) ASC1_WRCLK
(5) ASC1_RESET
(2,5,10) LPTM2_RESETb
(6) PB_SW3
(10) ASC2_BOARD_SENSE
(10) ASC3_BOARD_SENSE
(2,4,5,10) I2C_SCL
(2,4,5,10) I2C_SDA
(2,4,5,6,7,8,9,10,11,12,13,14,16)
R15
2k
+3.3V
J33
Enable_I2C
DNI
C73
150pF
150
150
(15) USB_I2C_EN
R181
R180
R16
2k
4
2
1
50
50
R161
4.7k
R202
10k
+3.3V
R262
1k
(15) FTDI_SCL
C72
120pF
R254
R253
4
+3.3V
R160
4.7k
6
4
5
B0_NC
2
1
3
LCD_2A
LCD_2B
LCD_2C
LCD_2D
LCD_2E
LCD_2F
LCD_2G
LCD_DP2
LCD_DP1
FSA4157_Analog_Sw
GND
B1_NO
S_CTRL
A_IN
VCC
U10
C103
10nF
ASC3_WRCLK
ASC3_RESET
ASC3_WDAT
ASC3_RDAT
SPI_CLK
SPI_OUT
LCD_1F
LCD_1G
LCD_1B
LCD_1C
LCD_1D
LCD_1E
LCD_COM
LCD_1A
SPI_CS0
USB_TDO
USB_TDI
USB_TCK
USB_TMS
Proto_PROGRAMN
ASC2_WRCLK
ASC2_RESET
ASC2_WDAT
ASC2_RDAT
B5
B6
D7
E7
A4
C5
D6
C6
D5
E6
C4
B4
D3
E4
B3
A3
B1
C1
C2
B2
I2C_SCL
LPTM21-FTG237
3
BANK_2
D8
E8
C9
D9
A7
B7
C7
C8
LPTM21-FTG237
+3.3V
6
4
5
B0_NC
3
2
1
FSA4157_Analog_Sw
GND
B1_NO
S_CTRL
A_IN
VCC
U11
C104
10nF
2
2
I2C_SDA
N8
M8
T9
R9
P8
P7
R7
T7
LCD_3A
LCD_3B
Proto_INITN
Proto_DONE
ASC1_WRCLK
ASC1_RDAT
ASC1_WDAT
ASC1_RESET
PB4A
PB4B
PB20A
PB4C || CSSPIN
PB20B
PB4D
PB20C || SN
PB6A
PB20D || SI/SIPI
PB6B
PB18D
PB6C || MCLK/CCLK
PB18C
PB6D || SO/SPISO
PB18B
PB9A || PCLKT2_0
PB18A
PB9B || PCLKC2_0
PB9C
PB9D
PB11A || PCLKT2_1
PB11B || PCLKC2_1
PB11C
PB11D
PB15A
PB15B
PB15C
PB15D
PRI Function || SEC Function(s)
U1B
PT17A
PT17B
PT17C || INITN
PT17D || DONE
PT16A
PT16B
PT16C
PT16D
PRI Function || SEC Function(s)
BANK_0
PT15A
PT15B
PT15C || JTAGENB
PT15D || PROGRAMN
PT12A || PCLKT0_1
PT12B || PCLKC0_1
PT12C || SCL/PCLKT0_0
PT12D || SDA/PCLKC0_0
PT11A
PT11B
PT11C || TCK
PT11D || TMS
PT10A
PT10B
PT10C || TDO
PT10D || TDI
PT9A
PT9B
PT9C
PT9D
U1D
(15) FTDI_SDA
R1
P1
P2
M5
P3
T2
R3
T3
P4
R4
N5
M6
N6
P6
T4
P5
R5
R6
N7
M7
R158
4.7k
3
I2C_SCL
I2C_SDA
SPI_IN
SPI_OUT
SPI_CS0
SPI_CLK
1
6
5
2
+3.3V
1
2
3
4
5
6
7
8
LCD_COM (7)
LCD_1A (7)
LCD_1B (7)
LCD_1C (7)
LCD_1D (7)
LCD_1E (7)
LCD_1F (7)
LCD_1G (7)
LCD_DP1 (7)
LCD_2A (7)
LCD_2B (7)
LCD_2C (7)
LCD_2D (7)
LCD_2E (7)
LCD_2F (7)
LCD_2G (7)
LCD_DP2 (7)
LCD_3A (7)
LCD_3B (7)
LCD_3C (7)
LCD_3D (7)
LCD_3E (7)
LCD_3F (7)
LCD_3G (7)
100
22
22
100
100
Proto_INITN
Proto_DONE
Proto_PROGRAMN
R19
10k
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
1
+3.3V
Sheet
C
C
Schematic Rev
Board Rev
3
of 16
I2C_SPI
J26
INITN
DONE
PROGRAMN
SPI_CS0
SPI_CLK
SPI_IN
SPI_OUT
R159
1k
AT25DF041A-MH
S
C
D
Q
+3.3V
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R247
R255
R256
R245
R246
C102
10uF
U3
Vcc
Reset
W
Vss
R265
100k
+3.3V
8
7
3
4
Dual Boot &
Fault Log Mem
1
Title
LPTM21 Top & Bottom Bank Digital Connections and SPI Memory
LCD_3C
LPTM2_RESETb
PB_SW3
SPI_IN
LCD_3D
LCD_3E
LCD_3F
LCD_3G
R171
10k
+3.3V
C9
100nF
+3.3V
EPAD
9
5
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 28. LPTM21 Top and Bottom Bank Digital Connections and SPI Memory
62
A
B
C
D
5
(2,3,5,10) I2C_SDA
(2,3,5,10) I2C_SCL
(6) VIDA_SW
(6) VIDA_[1:8]
5
C10
100nF
R241
R240
C11
100nF
C101
150pF
150
150
(11) DCDC1_SYNC
(11) DCDC2_SYNC
(12) DCDC3_SYNC
(12) DCDC4_SYNC
(13) DCDC5_SYNC
(13) DCDC6_SYNC
(14) DCDC7_SYNC
(14) DCDC8_SYNC
C12
100nF
C100
120pF
R252
R251
(8) FAN1_TACH
(8) FAN1_PWM
(8) FAN2_TACH
(8) FAN2_PWM
(8) FAN3_TACH
(8) FAN3_PWM
(8) FAN4_TACH
(8) FAN4_PWM
50
50
4
BANK_3
PL10D
PL10C
PL10B
PL10A
PL9B || PCLKC3_0
PL9A || PCLKT3_0
C16
100nF
LPTM21-FTG237
C15
100nF
BANK_1
PR2D
PR2C
PR2B
PR2A
PR3B
PR3A
M2
N2
N1
M1
L2
L3
C17
100nF
PRI Function || SEC Function(s)
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8D
PR5D
PR4B
PR4A
Decoupling Caps
N10
P10
P9
R10
L10
T10
M9
M10
N9
B10
F10
E11
U1C
LPTM21-FTG237
PRI Function || SEC Function(s)
PL2A || L_GPLLT_FB
PL2B || L_GPLLC_FB
PL2C || L_GPLLT_IN
PL2D || L_GPLLC_IN
PL3A || PCLKT3_2
PL3B || PCLKC3_2
PL3C
PL3D
PL4A
PL4B
PL4C
PL4D
PL5A || PCLKT3_1
PL5B || PCLKC3_1
PL8A
PL8B
PL8C
PL8D
U1E
C14
100nF
LED_2
LED_1
USER_I2C_SCL
USER_I2C_SDA
C13
100nF
LED_15
VIDA_8
VIDA_7
VIDA_6
VIDA_5
VIDA_4
VIDA_3
VIDA_2
VIDA_1
E2
D2
D1
E1
F2
F3
F1
G1
G2
G3
H3
H2
J2
J3
K3
K2
K1
L1
4
3
C18
100nF
D11
C11
C10
D10
E9
E10
C19
100nF
LED_5
LED_6
LED_7
LED_8
LED_3
LED_4
TP_VCCIO3
TP_VCCIO1
TP_VCCIO0
C20
100nF
C21
100nF
+3.3V_ASC0
R199
0
R201
0
+3.3V_ASC0
+3.3V
LED_1
LED_2
LED_3
LED_4
LED_5
LED_6
LED_7
LED_8
LED_9
LED_10
LED_11
LED_12
LED_13
LED_14
LED_15
(2,3,5,6,7,8,9,10,11,12,13,14,16)
LED_9
LED_10
LED_11
LED_12
LED_13
LED_14
3
2
LED_[1:15] (7,10)
R200
0
1
2
2
K4
J4
T5
L8
L7
L5
L4
K8
J8
H8
G8
F8
F7
F5
F4
A5
G5
G6
G7
K5
K6
K7
G16
H12
J12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
H14
J14
T16
A13
H11
J11
T12
A1
A6
E3
F6
H5
H6
H7
J1
J5
J6
J7
L6
M3
T1
T6
BANK_NC
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
1
Sheet
C
C
Schematic Rev
H1
G4
H4
A12
Board Rev
4
of 16
NC_40
NC_41
NC_42
NC_43
LPTM21-FTG237
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
A2
A8
A9
A10
B8
B9
B14
C3
C14
C15
D4
D14
D15
D16
E5
E12
E14
F15
F16
H15
J15
K12
K14
K15
L12
L14
M4
M12
M14
M16
N3
N4
N14
N16
R2
R8
R12
T8
T11
U1G
Title
LPTM21 Left & Right Bank Digital and Power Connections
LPTM21-FTG237
VCCIO3
VCCIO3
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCC
VCC
VCC
VCC
VCC
VCC
U1F
BANK_POWER
VCCA
VCCA
VCCA
HEADER 2
J3
1
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 29. LPTM21 Left and Right Bank Digital and Power Connections
63
A
B
C
D
C23
100nF
(6) TEMP_SENSE4N
(6) TEMP_SENSE4P
(6) TEMP_SENSE3N
(6) TEMP_SENSE3P
5
270
270
R25
R26
(10) ASC3_IMONP
(10) ASC3_IMONN
(2,3,10) LPTM2_RESETb
(3) ASC1_RESET
22
22
ASCCLK
R27
2.2K
A1_VMON9
A1_HIMON
A1_HVMON
A1_VMON1
A1_GS_VMON1
A1_VMON2
A1_GS_VMON2
A1_VMON3
A1_GS_VMON3
A1_VMON4
A1_GS_VMON4
A1_VMON5
A1_VMON6
100
100
100
R29
R30
R31
270
1
2
3
J5
4
HEADER 3
A1_GS_VMON3
A1_GS_VMON2
A1_GS_VMON1
A1_VMON9
I2C LSB bits set to 001
R28
R21
R20
A1_LED1
4
VMON1
VMON1GS
VMON2
VMON2GS
VMON3
VMON3GS
VMON4
VMON4GS
VMON5
VMON6
VMON7
VMON8
VMON9
HIMONP
HIMONN_HVMON
IMON1P
IMON1N
TMON1P
TMON1N
TMON2P
TMON2N
WDAT
RDAT
WRCLK
ASCCLK
SDA
SCL
I2C_ADDR
ASC10-SG48
26
25
28
27
30
29
32
31
34
35
36
37
38
17
18
19
20
21
22
23
24
4
5
6
7
14
15
16
U4
+3.3V
Mandatory ASC Jumper 2 to 3
Optional ASC Jumper 1 to 2
(2,3,4,6,7,8,9,10,11,12,13,14,16)
ASC1_RESETb
270
R24
(6) POT3
(6) POT4
270
R23
(3) ASC1_WDAT
(3) ASC1_RDAT
(3) ASC1_WRCLK
(2,3,4,10) I2C_SCL
(2,3,4,10) I2C_SDA
(2,10) ASC3_3V_SOFTS
C25
150pF
C24
150pF
(9,14) OUT_DCDC8
(9,14) A1_VMON4
(9) A1_GS_VMON4
(9,14) OUT_DCDC7
(9,13) OUT_DCDC6
(9,13) OUT_DCDC5
C22
100nF
+3.3V_ASC1
(2,3,10) I2C_WRITE_PROTECT
0
33
8
VCC
VCC
R238
GND
49
5
1
2
RESETb
TRIM1
TRIM2
TRIM3
TRIM4
GPIO8
GPIO9
GPIO10
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HEADER 2
J4
43
39
40
41
42
3
ASC1_RESETb
A1_LED8
A1_LED9
A1_LED10
A1_LED1
A1_LED2
A1_LED3
A1_LED4
A1_LED5
A1_LED6
44
45
46
47
48
1
11
12
13
A1_HVOUT4
2
3
9
10
A1_HVOUT1
A1_HVOUT2
R22
10k
+3.3V_ASC1
3
TRIM_DCDC5
TRIM_DCDC6
TRIM_DCDC7
TRIM_DCDC8
(13)
(13)
(14)
(14)
2
A1_LED[8:10] (6,7,14)
A1_LED[1:6] (7,13)
HOTSWAP_ASC3_3.3V (10)
2
Date:
May 13, 2014
Project
Platform Manager 2 Evaluation Board
Title
L-ASC10 Connections and Test Points
Size
B
A1_GPIO6
A1_GPIO8
A1_GPIO9
A1_GPIO10
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
A1_LED6
A1_LED8
A1_LED9
A1_LED10
A1_GPIO1
A1_GPIO2
A1_GPIO3
A1_GPIO4
A1_GPIO5
A1_HVOUT1
A1_HVOUT2
A1_HVOUT3
A1_HVOUT4
A1_HVOUT1
A1_HVOUT2
HOTSWAP_ASC3_3.3V
A1_HVOUT4
A1_LED1
A1_LED2
A1_LED3
A1_LED4
A1_LED5
A1_TRIM1
A1_TRIM2
A1_TRIM3
A1_TRIM4
A1_TMON1P
A1_TMON1N
A1_TMON2P
A1_TMON2N
C
C
Schematic Rev
Board Rev
5
of 16
A1_HIMONP
A1_HIMONN_HVMON
A1_IMON1P
A1_IMON1N
A1_VMON1
A1_VMON1_GS
A1_VMON2
A1_VMON2_GS
A1_VMON3
A1_VMON3_GS
A1_VMON4
A1_VMON4_GS
A1_VMON5
A1_VMON6
A1_VMON7
A1_VMON8
A1_VMON9
A1_WDAT
A1_RDAT
A1_WRCLK
A1_RESET
A1_ASCCLK
TRIM_DCDC5
TRIM_DCDC6
TRIM_DCDC7
TRIM_DCDC8
TEMP_SENSE3P
TEMP_SENSE3N
TEMP_SENSE4P
TEMP_SENSE4N
A1_HIMON
A1_HVMON
ASC3_IMONP
ASC3_IMONN
A1_VMON1
A1_GS_VMON1
A1_VMON2
A1_GS_VMON2
A1_VMON3
A1_GS_VMON3
A1_VMON4
A1_GS_VMON4
A1_VMON5
A1_VMON6
POT3
POT4
A1_VMON9
ASC1_WDAT
ASC1_RDAT
ASC1_WRCLK
ASC1_RESETb
ASCCLK
ASC1 TEST POINTS
1
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 30. L-ASC10 Connections and Test Points
64
A
B
C
D
R35
1k
3
1
5
+3.3V
2
POT1
R33
1k
R36
1k
3
1
2
3
2
+3.3V
4
1
TEMP_SENSE1N (2)
TEMP_SENSE2P (2)
POT2(2)
VMON8
VMON7
POT1(2)
A0_LED10 (2,7)
TEMP_SENSE2N (2)
SW1
A0_GPIO_10
R34
1k
NDT3055LCT
Q43
TEMP_SENSE1P (2)
Temperature Sensor 1
R249
100
Q5
2N3904
Temperature Sensor 2
TEMP_DEMO
(2) A0_HVOUT4
2N3906
Q4
POT2
R203
2.7
1W
ASC0
(2,9,12) OUT_DCDC4
5
4
4
SW6H
SW6G
SW6F
SW6E
SW6D
SW6C
SW6B
SW6A
8
7
6
5
4
3
2
1
2
1
2
1
(2,3,4,5,7,8,9,10,11,12,13,14,16)
3
4
3
4
SW3
PB_SW3
SW2
VID_A
2
1
9
10
11
12
13
14
15
16
3
VIDA_8
VIDA_7
VIDA_6
VIDA_5
VIDA_4
VIDA_3
VIDA_2
VIDA_1
VID A
Restart
SW4
3
4
R242
10k
+3.3V
Manual Restart
+3.3V
3
9
10k
8
10k
7
10k
6
10k
4
10k
3
10k
2
10k
1
10k
R243
10k
+3.3V
RN1H
RN1G
RN1F
5
RN1E
RN1D
RN1C
RN1B
VIDA_[1:8] (4)
+3.3V
PB_SW3
VIDA_SW (4)
MANUAL_RESTART (3)
10
RN1A
R244
1k
C26
10nF
DI
R37
10k
DI
+3.3V
2
PB_SW3 (3)
2
3
1
R41
1k
3
1
2
VMON8
POT4(5)
R39
1k
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
1
Sheet
C
C
Schematic Rev
Board Rev
6
of 16
VMON7
POT3(5)
A1_LED10 (5,7)
SW5
A1_GPIO10
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
2
R38
1k
+3.3V
3
4
TEMP_SENSE4N (5)
TEMP_SENSE4P (5)
Title
Inputs: Temperature Sensors, Slide Pots, and Switches
R40
1k
POT4
2
1
TEMP_SENSE3N (5)
TEMP_SENSE3P (5)
Temperature Sensor 3
Q7
2N3904
Temperature Sensor 4
POT3
+3.3V
2N3906
Q6
ASC1
1
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 31. Inputs: Temperature Sensors, Slide Pots, and Switches
65
A
B
C
D
+3.3V
5
(3) LCD_3C
(3) LCD_3D
(3) LCD_3E
(3) LCD_DP2
(3) LCD_2C
(3) LCD_2D
(3) LCD_2E
(3) LCD_DP1
(3) LCD_1C
(3) LCD_1D
(3) LCD_1E
(3) LCD_COM
(4,10) LED_[1:15]
(5,6,14) A1_LED[8:10]
(5,13) A1_LED[1:6]
(2,6,11,12) A0_LED[1:10]
(2,3,4,5,6,8,9,10,11,12,13,14,16)
5
LED_1
3
Red
D14
RN10D
2.2k
RN10C
2.2k
12
11
10
9
8
7
6
5
4
3
2
1
C3
D3
E3
DP2
C2
D2
E2
DP1
C1
D1
E1
COM
LED_2
Red
D23
RN3D
2.2k
RN3C
2.2k
A1_LED2
3
4
PCB Footprint = LCD_301
Red
D22
1 RN3B
2.2k
RN3A
2.2k
10
A1_LED1
Red
D13
1 RN10B
2.2k
RN10A
2.2k
10
A0_LED2
2
RN7D
2.2k
D4
A0_LED1
2
Red
2
RN7B
2.2k
D3
3
RN7C
2.2k
Red
1
RN7A
2.2k
10
4
4
RN10E
2.2k
RN3E
2.2k
A1_LED3
Red
D15
6 RN10F
2.2k
5
D
4
C
E
LED_3
Red
D24
6 RN3F
2.2k
5
Red
D5
U5
G
7
RN7F
2.2k
RN7E
2.2k
A0_LED3
6
5
4
7
7
B
F
Red
Red
D16
RN10H
2.2k
RN10G
2.2k
Red
D25
RN3H
2.2k
RN3G
2.2k
A
9
9
9
Red
B3
A3
F3
G3
B2
A2
F2
G2
B1
A1
F1
G1
13
14
15
16
17
18
19
20
21
22
23
24
LED_5
Red
D26
1 RN4B
2.2k
RN4A
2.2k
10
A1_LED5
Red
D17
1 RN11B
2.2k
RN11A
2.2k
10
2
RN8B
2.2k
D7
A0_LED5
1
RN8A
2.2k
10
LUMEX-LCD2
3
2
1
A1_LED4
8
LED_4
8
RN7H
2.2k
D6
A0_LED4
8
RN7G
2.2k
2
2
Red
Red
D18
RN11D
2.2k
RN11C
2.2k
Red
D27
RN4D
2.2k
RN4C
2.2k
4
4
4
RN11E
2.2k
RN4E
2.2k
LED_7
Red
D28
LCD_3B (3)
LCD_3A (3)
LCD_3F (3)
LCD_3G (3)
LCD_2B (3)
LCD_2A (3)
LCD_2F (3)
LCD_2G (3)
LCD_1B (3)
LCD_1A (3)
LCD_1F (3)
3
A1_LED8
Red
D19
6 RN11F
2.2k
5
6 RN4F
2.2k
5
Red
D9
7
RN8F
2.2k
RN8E
2.2k
A0_LED7
6
5
LCD_1G (3)
A1_LED6
3
LED_6
3
RN8D
2.2k
D8
A0_LED6
3
RN8C
2.2k
3
7
7
Red
Red
D20
RN11H
2.2k
RN11G
2.2k
Red
D29
RN4H
2.2k
RN4G
2.2k
A1_LED9
8
LED_8
8
9
RN8H
2.2k
D10
A0_LED8
8
RN8G
2.2k
9
9
RN9B
2.2k
Red
D11
Red
D21
RN6H
2.2k
RN6G
2.2k
LED_9
Red
D30
1 RN5B
2.2k
RN5A
2.2k
10
2
A1_LED10
8
A0_LED9
1
RN9A
2.2k
10
9
2
Red
Red
D31
RN5D
2.2k
RN5C
2.2k
+3.3V
LED_10
3
RN9D
2.2k
D12
4
A0_LED10
3
RN9C
2.2k
4
RN5E
2.2k
LED_11
Red
D32
7
RN9F
2.2k
RN9E
2.2k
6 RN5F
2.2k
5
6
5
2
7
2
Red
D33
RN5H
2.2k
RN5G
2.2k
9
RN9H
2.2k
RN9G
2.2k
LED_12
8
8
9
LED_13
Red
D34
1 RN6B
2.2k
RN6A
2.2k
10
2
Red
D35
RN6D
2.2k
RN6C
2.2k
LED_14
3
Date:
Size
B
4
RN6E
2.2k
LED_15
Red
D36
6 RN6F
2.2k
5
Project
Platform Manager 2 Evaluation Board
May 13, 2014
7
+3.3V
1
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
Title
Outputs: LCD and LEDs
+3.3V
C
C
Schematic Rev
Board Rev
7
of 16
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 32. Outputs: LCD and LEDs
66
A
B
C
D
+3.3V
R43
10k
5
(4) FAN1_TACH
(2,3,4,5,6,7,9,10,11,12,13,14,16)
(4) FAN1_PWM
R42
1k
+12V
R44
1k
0.25W
C74
2uF
FAN 1 Voltage Select
C69
0.22uF
Q3
IRLML6402
3
2
1
J6
4
4
FAN 1 - 3 WIRE HIGH SIDE DRIVE
C75
10uF
J27
Fan1_Capacitor
R45
10k
Q8
2N3904
+5V
1
2
3
5
J7
3
2
1
FAN 1
+5V
R212
470
R46
10k
+3.3V
3
3
2
1
Fan 2
J9
FAN 2 Voltage Select
J8
Q10
NDT3055LCT
3
2
1
FAN 2 - 3 WIRE LOW SIDE DRIVE
R47
10k
(4) FAN2_PWM
(4) FAN2_TACH
+12V
3
2
(4) FAN4_PWM
(4) FAN4_TACH
R50
10k
R48
10k
Date:
Size
B
May 13, 2014
+12V
1
6
5
4
3
2
1
FAN 3
J10
+12V
6
5
4
3
2
1
FAN 4
J11
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
FAN 4 - 4 WIRE or
3 WIRE LOW SIDE DRIVE
Q12
NDT3055LCT
+5V
C
C
Schematic Rev
Board Rev
8
of 16
FAN 3 - 4 WIRE or
3 WIRE LOW SIDE DRIVE
Q11
NDT3055LCT
+5V
Project
Platform Manager 2 Evaluation Board
R228
470
+3.3V
R214
470
+3.3V
Title
Fan Connectors
R51
10k
(9,10,12,14,16) +5V
R49
10k
(4) FAN3_PWM
(4) FAN3_TACH
(2,9,10,11,13,16) +12V
2
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 33. Fan Connectors
67
A
B
C
D
A
B
A
B
A
B
5
2 Position Terminal Block
J13
2 Position Terminal Block
J12
(2,15) +5V_USB_SW
2 Position Terminal Block
J25
J28
1
2
3
D47
D45
SMBJ22CA
NSR0530P2T5G
PWR JACK
+12V
+3.3V
+5V
5V_USB_PWR
J29
2
1
5
4
NSR0530P2T5G
D46
NSR0530P2T5G
D37
+12V (2,8,10,11,13,16)
4
C28
220uF
25V
D38
NSR0530P2T5G
+11.3V (2,10)
+3.3V (2,3,4,5,6,7,8,10,11,12,13,14,16)
+5V (8,10,12,14,16)
C27
47uF
25V
R52
100
+11.3V
3
3
(5,14) OUT_DCDC7
(5,13) OUT_DCDC6
(5,13) OUT_DCDC5
(2,12) OUT_DCDC3
(2,11) OUT_DCDC2
(2,11) OUT_DCDC1
B
A
B
A
B
A
A
B
A
B
A
B
J23
2
DCDC7
J22
DCDC6
J21
DCDC5
DCDC3
J19
DCDC2
J18
DCDC1
J17
2
Date:
May 13, 2014
Project
Platform Manager 2 Evaluation Board
Title
Board Power Connections
Size
B
R32
100
R59
100
D
C
B
A
A
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
(5) A1_GS_VMON4
(5,14) OUT_DCDC8
(5,14) A1_VMON4
(5,14) DCDC8_SENSE
(2) A0_GS_VMON4
C
B
D
(2,12) A0_VMON4
R13
100
R14
100
(2,6,12) OUT_DCDC4
(2,12) DCDC4_SENSE
1
C
C
Schematic Rev
Board Rev
9
of 16
J24
DCDC8
DCDC4
J20
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 34. Board Power Connections
68
A
B
C
D
5
J30
Mosfet Drive Select
(2,5) ASC3_3V_SOFTS
ASC0
(2) ENABLE_ASC3_3.3V
ASC1
(5) HOTSWAP_ASC3_3.3V
(5) ASC3_IMONN
R261
J32
Program J15
J31
Program J14
(5) ASC3_IMONP
+3.3V
(2) ASC2_3V_SOFTS
(2) ASC2_IMONN
(2) ASC2_IMONP
(2) ENABLE_ASC2_3.3V
1
2
3
R58
100
0
1
2
2
1
R53
100
+3.3V
R57
0.020
(4,7) LED_13
(4,7) LED_12
(3) ASC2_RESET
(2,3,4,5) I2C_SCL
(2,3,4,5) I2C_SDA
(4,7) LED_14
4
(4,7) LED_9
(4,7) LED_8
(3) ASC3_RESET
I2C_SCL
I2C_SDA
(4,7) LED_10
(4,7) LED_11
R179
0
22
R260
R178
22
0
R177
R259
0
R176
A3_12V_OVERCURRENT_SENSE
15
16
17
18
19
20
A3_5V_OVERCURRENT_SHUTDOWN
22
23
21
+12V
24
25
A3_5V_OVERCURRENT_SENSE
+5V
3
J14
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
8MHz
+12V
+5V
ASC3_+3.3V
2
ASC3_WDAT (3)
ASC3_RDAT (3)
2
ASC2_WDAT (3)
ASC2_RDAT (3)
ASC2_WRCLK (3)
LPTM2_RESETb (2,3,5)
SM_LED_0603
D40
Green
C30
330uF
10V
TP8
R55
470
R61
1k
R56
1k
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R60
470
ASC3_+3.3V
SM_LED_0603
D39
Green
C29
330uF
10V
TP9
ASC2_+3.3V
1
Date:
Size
B
May 13, 2014
Project
Platform Manager 2 Evaluation Board
1
Sheet
Title
L-ASC10 #2 & #3 Interface Connectors and 3.3 V Soft Start
I2C_WRITE_PROTECT (2,3,5)
+11.3V (2,9)
ASC2_+3.3V
ASC3_WRCLK (3)
LPTM2_RESETb
I2C_WRITE_PROTECT
8MHz
ASC3_+3.3V
+11.3V
+12V
+5V
CONN DSUB 25-R
14
15
16
17
18
19
20
21
22
23
24
25
CONN DSUB 25-R
J15
0 A2_12V_OVERCURRENT_SHUTDOWN
0 A3_12V_OVERCURRENT_SHUTDOWN 14
R175
A2_5V_OVERCURRENT_SHUTDOWN
A2_5V_OVERCURRENT_SENSE
3
0 A2_12V_OVERCURRENT_SENSE
22
R258
R174
0
22
R257
0
R173
R172
(3) ASC2_BOARD_SENSE
(2,8,9,11,13,16) +12V
(8,9,12,14,16) +5V
(4,7) LED_7
(3) ASC3_BOARD_SENSE
NDT3055LCT
Q14
0.020
R54
NDT3055LCT
Q13
4
1
(2,3,4,5,6,7,8,9,11,12,13,14,16)
+3.3V
1
5
C
C
Schematic Rev
Board Rev
10 of 16
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 35. L-ASC10 #2 and #3 Expansion Connectors and 3.3 V Soft Start
69
A
B
C
D
1
3
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
R204
130k
12
16
17
5
4
R63
1.36k
2.74k
R64
2.8k
5.6k
Resistor number
13
4
5
6
Trim
Vout
R65
2.8K
5.6k
R205
23.7k
4
R66
open
open
R63
2.74k
RpdnS
R64
5.6k
Rs2
R62
open
RpupS
R6 7
open
open
C76
10nF
R67
open
RpdnD
R65
5.6k
Rs1
R66
open
RpupD
C78
100nF
(2,3,4,5,6,7,8,9,10,12,13,14,16)
R183
470
C32
22uF
10V
R191
4.7k
R68
1K
D49
Green
SM_LED_0603
+3.3V
C80
100nF
C33
22uF
16V
+12V
(2,7) A0_LED6
(2) TRIM_DCDC2
ASC0 TRIM2
Q16
FDV301N
(4) DCDC2_SYNC
(12,13,14) SMB_ALERT
(12,13,14) PMBUS_SDA
ASC0 GPIO6
1
2
14
15
8
9
10
11
2
1
3
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
7
5
4
3
R69
open
open
R206
130k
12
16
17
6
4
5
Trim
Vout
2
R70
2.22k
4.42k
R207
36.5k
5
4
Date:
Size
B
Project
Platform Manager 2 Evaluation Board
May 13, 2014
R192
4.7k
C34
22uF
10V
R184
470
R75
680
1
Sheet
C
C
Schematic Rev
Board Rev
11 of 16
ASC0 VMON2
OUT_DCDC2 (2,9)
Q35
2N3904
+3.3V
D50
Green
SM_LED_0603
1
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R7 4
open
open
C79
10nF
R74
open
RpdnD
R72
8.02k
Rs1
R73
open
RpupD
C81
100nF
Title
LPTM21 Trims: DCDC1 and DCDC2
R73
open
open
R70
4.42k
RpdnS
R71
8.02k
Rs2
R69
open
RpupS
R71
R72
4.12k 4.12k
8.02k 8.02k
Resistor number
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
3.3V @ 3A
3
GND
SIP
3.3V @ 2A
On-Off Control
Vin
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
PDT003A0X3
DCDC2
2
DCDC2_A
NQR002A0X4Z
Q47
FDV301N
R215
20K
3.3V DCDC installed
R163
20K
TP11_SYNC
(12,13,14) PMBUS_SCL
ASC0 VMON1
OUT_DCDC1 (2,9)
Q34
2N3904
3
The NQR002A0X4Z supply is Positive ON logic and requires this circuit. The APXS002A0X and PDT003A0X3 supplies are Negative ON logic so they do not need it.
R62
open
open
7
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
5V @ 3A
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
5V DCDC installed
14
15
8
9
10
11
2
1
PDT003A0X3
DCDC1
3
GND
SIP
5V @ 2A
On-Off Control
Vin
DCDC1_A
NQR002A0X4Z
Q45
FDV301N
R213
20K
2
The Safe-state of GPIO5 and GPIO6 is Low.
The two MOSFET circuits are used to prevent
turning ON a DCDCx_A supply, which uses
Positive ON logic, during Safe-state.
Q15 is used to interface from the ASC
to the +12V supply. However
Q15 inverts the output from the GPIO
so Q45 is used to invert it back again.
ASC0 TRIM1
(2) TRIM_DCDC1
ASC0 GPIO5
Q15
FDV301N
SMB_ALERT
PMBUS_SDA
(4) DCDC1_SYNC
(2,7) A0_LED5
R162
20K
TP10_SYNC
PMBUS_SCL
C77
100nF
C31
22uF
16V
(2,8,9,10,13,16) +12V
5
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 36. LPTM21 Trims: DCDC1 and DCDC2
70
A
B
C
D
TP12_SYNC
PMBUS_SCL
(2,7) A0_LED3
On-Off Control
2
1
14
15
3
7
R209
54.9k
R80
open
open
C82
10nF
R8 1
open
open
R81
open
RpdnD
R79
11.0k
Rs1
C36
22uF
10V
R82
470
(2,7) A0_LED4
SMB_ALERT
PMBUS_SDA
ASC0 GPIO4
5
The Safe-state of GPIO3 and GPIO4 is Low.
Therefore this GPIO can be directly used for turning
ON a DC-DC supply which uses Positive ON logic
such as the NQR002A0X4Z supply.
Q48 is used to invert the signal for turning ON
a DC-DC supply which uses Negative ON logic
such as the APXS002A0X and PDT003A0X3
supplies.
This prevents the DC-DC supply from being
turned ON during Safe-state of the GPIO output.
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
R77
3.16k
6.34k
4
R78
R79
5.6k 5.6k
11.0k 11.0k
3
2
4
6
8
10
J35
HEADER_2X5
1
3
5
7
9
Q49
FDV301N
(11,13,14) SMB_ALERT
(11,13,14) PMBUS_SDA
(4) DCDC4_SYNC
TP13_SYNC
(11,13,14) PMBUS_SCL
(2) TRIM_DCDC4
R77
6.34k
RpdnS
R78
11.0k
Rs2
ASC0 TRIM4
Resistor number
R208
130k
12
16
17
6
4
5
ASC0 VMON3
OUT_DCDC3 (2,9)
C37
22uF
10V
(2) TRIM_DCDC3
R76
open
open
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
2.5V @ 3A
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
R80
open
RpupD
R193
4.7k
Q36
2N3904
C86
100nF
R165
10K
+5V
1
2
SIP
1.2V @ 2A
3
PMBUS_SCL
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
7
2
Trim
Vout
2
R83
open
open
R210
130k
12
16
17
6
4
5
5
4
R84
10.0k
20.0k
R8 8
open
open
Date:
Size
B
Project
Platform Manager 2 Evaluation Board
May 13, 2014
R194
4.7k
C38
22uF
10V
R186
470
R89
330
1
Sheet
C
C
Schematic Rev
Board Rev
12 of 16
ASC0 VMON4
OUT_DCDC4 (2,6,9)
Q37
2N3904
+3.3V
D52
Green
SM_LED_0603
1
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R87
open
open
C85
10nF
R88
open
RpdnD
R86
19.6k
Rs1
Title
LPTM21 Trims: DCDC3 and DCDC4
R85
11.0k
19.6k
R84
20.0k
RpdnS
R85
19.6k
Rs2
R87
open
RpupD
A0_GS_VMON4 (2,9)
DCDC4_SENSE (2,9)
C87
100nF
R83
open
RpupS
R86
11.0k
19.6k
R211
84.5k
Resistor number
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
1.2V @ 3A
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
1.2V DCDC installed
14
15
8
9
10
11
2
1
PDT003A0X3
DCDC4
On-Off Control
Vin
DCDC4_A
NQR002A0X4Z
3
R76
open
RpupS
C84
100nF
D51
Green
SM_LED_0603
R185
470
3
5
4
+3.3V
GND
Trim
Vout
(2,3,4,5,6,7,8,9,10,11,13,14,16)
3
GND
SIP
2.5V @ 2A
PDT003A0X3
DCDC3
8
9
10
11
1
Vin
2.5V DCDC installed
R164
10K
2
DCDC3_A
NQR002A0X4Z
4
ASC0 TRIM3
ASC0 GPIO3
Q48
FDV301N
SMB_ALERT
PMBUS_SDA
(4) DCDC3_SYNC
C35
22uF
10V
C83
100nF
(8,9,10,14,16) +5V
5
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 37. LPTM21 Trims: DCDC3 and DCDC4
71
A
B
C
D
1
3
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
7
R90
open
open
4
5
R218
200k
12
16
17
6
Trim
Vout
5
4
R92
2.8k
5.6k
R93
2.8K
5.6k
R94
open
open
R91
2.74k
RpdnS
R92
5.6k
Rs2
R90
open
RpupS
R9 5
open
open
C88
10nF
R95
open
RpdnD
R93
5.6k
Rs1
R94
open
RpupD
C90
100nF
(2,3,4,5,6,7,8,9,10,11,12,14,16)
R187
470
C40
22uF
10V
R195
4.7k
R96
1K
D53
Green
SM_LED_0603
+3.3V
C92
100nF
C41
22uF
16V
+12V
(5,7) A1_LED6
(5) TRIM_DCDC6
ASC1 TRIM2
Q18
FDV301N
(4) DCDC6_SYNC
(11,12,14) SMB_ALERT
(11,12,14) PMBUS_SDA
ASC1 GPIO6
1
2
1
14
15
3
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
7
R97
open
open
5
4
3
R220
200k
12
16
17
6
4
5
Trim
Vout
5
4
2
R98
2.22k
4.42k
R221
36.5k
Date:
Size
B
Project
Platform Manager 2 Evaluation Board
May 13, 2014
R196
4.7k
C42
22uF
10V
R188
470
R103
680
1
Sheet
C
C
Schematic Rev
Board Rev
13 of 16
ASC1 VMON2
OUT_DCDC6 (5,9)
Q39
2N3904
+3.3V
D54
Green
SM_LED_0603
1
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R102
open
open
C91
10nF
R102
open
RpdnD
R100
8.02k
Rs1
R101
open
RpupD
C93
100nF
Title
L-ASC10 #1 Trims: DCDC5 and DCDC6
R101
open
open
R98
4.42k
RpdnS
R99
8.02k
Rs2
R97
open
RpupS
R99
R100
4.12k 4.12k
8.02k 8.02k
Resistor number
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
3.3V @ 3A
3
GND
SIP
3.3V @ 2A
On-Off Control
Vin
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
PDT003A0X3
DCDC6
8
9
10
11
2
DCDC6_A
NQR002A0X4Z
Q53
FDV301N
R229
20K
2
3.3V DCDC installed
R167
20K
TP15_SYNC
(11,12,14) PMBUS_SCL
ASC1 VMON1
OUT_DCDC5 (5,9)
Q38
2N3904
3
The NQR002A0X4Z supply is Positive ON logic and requires this circuit. The APXS002A0X and PDT003A0X3 supplies are Negative ON logic so they do not need it.
R91
1.36k
2.74k
4
R219
23.7k
Resistor number
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
5V @ 3A
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
5V DCDC installed
14
15
8
9
10
11
2
1
PDT003A0X3
DCDC5
3
GND
SIP
5V @ 2A
On-Off Control
Vin
Q51
FDV301N
R227
20K
2
DCDC5_A
NQR002A0X4Z
The Safe-state of GPIO5 and GPIO6 is Low.
The two MOSFET circuits are used to prevent
turning ON DCDCx_A supply, which uses
Positive ON logic, during Safe-state.
Q17 is used to interface the ASC to the +12V
supply. However Q17 inverts the output from the GPIO
so Q51 is used to invert it back again.
ASC1 TRIM1
(5) TRIM_DCDC5
ASC1 GPIO5
Q17
FDV301N
SMB_ALERT
PMBUS_SDA
(4) DCDC5_SYNC
(5,7) A1_LED5
R166
20K
TP14_SYNC
PMBUS_SCL
C89
100nF
C39
22uF
16V
(2,8,9,10,11,16) +12V
5
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 38. L-ASC10 #1 Trims: DCDC5 and DCDC6
72
A
B
C
D
On-Off Control
2
1
14
15
3
7
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
Trim
Vout
R222
200k
12
16
17
6
4
5
5
4
5
R223
54.9k
R105
3.16k
6.34k
4
R106 R107
5.6k 5.6k
11.0k 11.0k
R105
6.34k
RpdnS
R106
11.0k
Rs2
R104
open
RpupS
C94
10nF
+3.3V
R109
open
open
R109
open
RpdnD
R107
11.0k
Rs1
R108
open
RpupD
R108
open
open
C96
100nF
(2,3,4,5,6,7,8,9,10,11,12,13,16)
4
Resistor number
R104
open
open
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
2.5V @ 3A
3
GND
SIP
2.5V @ 2A
PDT003A0X3
DCDC7
8
9
10
11
1
Vin
2.5V DCDC installed
10K
R168
2
DCDC7_A
NQR002A0X4Z
The Safe-state of GPIO8 and GPIO9 is HiZ.
Therefore this GPIO can be directly used for turning
ON a DC-DC supply which uses Negative ON logic
such as the APXS002A0X and PDT003A0X3
supplies.
Q54 is used to invert the signal for turning ON
a DC-DC supply which uses Positive ON logic
such as the NQR002A0X4Z supply.
This prevents the DC-DC supply from being
turned ON during Safe-state of the GPIO output.
ASC1 TRIM3
(5) TRIM_DCDC7
SMB_ALERT
PMBUS_SDA
(4) DCDC7_SYNC
TP16_SYNC
PMBUS_SCL
Q54
FDV301N
C95
100nF
ASC1 GPIO8
(5,7) A1_LED8
10V
C43
22uF
(8,9,10,12,16) +5V
5
C44
22uF
10V
R197
4.7k
R110
470
+5V
10V
C45
22uF
OUT_DCDC7 (5,9)
ASC1 GPIO9
(5,7) A1_LED9
Q40
2N3904
Q55
FDV301N
C98
100nF
3
ASC1 TRIM4
(5) TRIM_DCDC8
(11,12,13) SMB_ALERT
(11,12,13) PMBUS_SDA
(4) DCDC8_SYNC
TP17_SYNC
(11,12,13) PMBUS_SCL
ASC1 VMON3
D55
Green
SM_LED_0603
R189
470
3
2
1
14
15
3
APXS002A0X
NQR002A0X4Z
or PDT003A0X3
7
SMBALERT
DATA
GND GND
CLK
SEQ
PGOOD
SYNC
VIN
ON_OFF
Trim
Vout
R224
200k
12
16
17
6
4
5
5
4
2
R111 R112
open 10.0k
open 20.0k
R116
open
open
Date:
Size
B
Project
Platform Manager 2 Evaluation Board
May 13, 2014
R198
4.7k
C46
22uF
10V
R190
470
R117
330
1
Sheet
C
C
Schematic Rev
Board Rev
14 of 16
ASC1 VMON4
OUT_DCDC8 (5,9)
Q41
2N3904
+3.3V
D56
Green
SM_LED_0603
1
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
R115
open
open
C97
10nF
R116
open
RpdnD
R114
19.6k
Rs1
Title
L-ASC10 #1 Trims: DCDC7 and DCDC8
R113
11.0k
19.6k
R112
20.0k
RpdnS
R113
19.6k
Rs2
R115
open
RpupD
A1_GS_VMON4 (2,9)
DCDC8_SENSE (5,9)
C99
100nF
R111
open
RpupS
R114
11.0k
19.6k
R225
84.5k
Resistor number
13
SIG_GND
VS-
ADDR0
ADDR1
TRIM
VOUT
VS+
DOSA
1.2V @ 3A
3
GND
SIP
1.2V @ 2A
On-Off Control
Vin
PDT003A0X3
DCDC8
8
9
10
11
1
2
1.2V DCDC installed
10K
R169
DCDC8_A
NQR002A0X4Z
2
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 39. L-ASC10 #1 Trims: DCDC7 and DCDC8
A
B
C
D
C57
100nF
8
7
6
5
10
11
6
7
8
9
4
5
2
3
1
CS
SK
DIN
DOUT
1
2
3
4
5
PWR_ENABLEb
SOIC-8
C71
1uF
3
100k
C47
10nF
R237
C58
0.33uF
2
10k
NC
Vout
4
D42
Blue
4
D41
NSR0530P2T5G
R119
2.2k
C70
1uF
R120
100
+3.3V_USB
2
1
4
3
C59
47uF
16V
D43
NSR0530P2T5G
12MHZ
X1
R231
R230
C60
10uF
10V
3
C55
18pF
C51
3.3uF
Ferrite_bead
L3
+3.3V_USB
VCC18FT
+5V_USB_SW (2,9)
C56
18pF
4
5
+5V_USB_SW
Q2
IRLML6402
2.2k
2
GND
EECS
EESK
EEDATA
LD6836
EN
Vin
R118
1M
+5V_USB
R234
1
R236
10k
+3.3V_USB
R235
L2
Ferrite_bead
R217
0
SHLD
M93C46-WMN6TP
VCC
NC
ORG
GND
U7
MH1
MH2
CASE
CASE
CASE
CASE
NC
GND
DD+
VCC
USB_MINI_B
+3.3V_USB
TYPE_B
J16
USB Connection
C48
10nF
1
U9
IN
U8
12k
1
C50
100nF
2
4
13
3
2
63
62
61
6
14
7
8
49
50
3
FT2232H
C61
6.8uF
16V
C53
100nF
+3.3V_USB
FTDI High-Speed USB
TEST
OSCO
OSCI
EECS
EECLK
EEDATA
REF
RESET#
DM
DP
VREGOUT
VREGIN
U6
FT2232HL
NCP1117
OUT
TAB
GND
2.2k
C52
100nF
C49
4.7uF
3
AGND
10
+5V_USB
4
9
VPHY
VPLL
12
37
64
VCORE
VCORE
VCORE
20
31
42
56
SUSPEND#
PWREN#
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
GND
GND
73
+3.3V_USB_SW
1
5
11
15
25
35
47
51
5
PWR_ENABLEb
+3.3V_USB_SW (2)
36
60
48
52
53
54
55
57
58
59
38
39
40
41
43
44
45
46
26
27
28
29
30
32
33
34
16
17
18
19
21
22
23
24
C54
100nF
2
2
R126
R127
R248
R122
R123
R124
R125
0
0
0
0
0
0
0
Date:
Size
B
1
R264
470
Sheet
C
C
Schematic Rev
Board Rev
15 of 16
Q42
2N3904
+3.3V
D57
Red
SM_LED_0603
C65
100nF
R263
4.7k
1
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
FTDI_SDA (3)
FTDI_SCL (3)
USB_I2C_EN (3)
Project
Platform Manager 2 Evaluation Board
May 13, 2014
C68
100nF
C64
100nF
USB_TCK (3)
USB_TDI (3)
USB_TDO (3)
USB_TMS (3)
C67
100nF
C63
100nF
Title
USB Programming Interface
C66
100nF
VCC18FT
C62
100nF
+3.3V_USB
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 40. USB Programming Interface
A
B
C
D
Q21
FDV301N
DNI
Q20
FDV301N
DNI
Q22
FDV301N
DNI
Q26
FDV301N
DNI
R141
1k
DNI
R140
1k
DNI
5
R133
1k
DNI
R132
1k
DNI
R142
1k
DNI
R134
1k
DNI
(2,3,4,5,6,7,8,9,10,11,12,13,14)
Q23
FDV301N
DNI
Q27
FDV301N
DNI
AK11
AK13
AK14
AK12
AK16
AK19
AK17
AK15
AK18
AK20
AK21
AK22
AJ19
AJ18
AJ17
AJ20
AJ13
AJ12
AJ15
AJ11
AJ16
AJ14
AJ21
AJ22
R143
1k
DNI
R135
1k
DNI
R144
1k
DNI
R136
1k
DNI
R145
1k
DNI
R137
1k
DNI
R146
1k
DNI
R138
1k
DNI
Q32
FDV301N
DNI
Q33
FDV301N
DNI
SMD SOT-223 Prototype Area
AH16
AH19
AH18
AH20
AH12
AH13
AH14
AH11
AH17
AH15
AH21
AH22
4
R147
1k
DNI
R139
1k
DNI
R151
1k
DNI
R150
1k
DNI
AG17
AG19
AG18
AG20
AG12
AG13
AG14
AG11
AG15
AG16
AG21
AG22
R153
1k
DNI
R152
1k
DNI
AF15
AF17
AF19
AF20
AF13
AF12
AF14
AF11
AF16
AF18
AF21
AF22
R155
1k
DNI
R154
1k
DNI
AE14
AE13
AE15
AE16
AE19
AE17
AE20
AE18
AE11
AE12
AE21
AE22
R157
1k
DNI
R156
1k
DNI
AD11
AD12
AD13
AD14
AD15
AD17
AD18
AD16
AD19
AD20
AD21
AD22
Through Hole Prototype Area
SMD 0805 Cs, Ds, or Rs Prototype Area
+3.3V
(8,9,10,12,14) +5V
(2,8,9,10,11,13) +12V
Q25
FDV301N
DNI
Q24
FDV301N
DNI
SOT-23 Package Prototype Area
AC11
AC12
AC13
AC14
AC15
AC18
AC17
AC16
AC19
AC20
AC21
AC22
3
AB11
AB12
AB13
AB14
AB18
AB15
AB17
AB16
AB20
AB19
AB21
AB22
3
AA11
AA12
AA14
AA15
AA13
AA16
AA17
AA18
AA19
AA20
AA21
AA22
1
2
3
4
FDV301N
DNI
D4
D3
D2
D1
8
7
6
5
1
1
R148
1k
DNI
2
R149
1k
DNI
8
7
6
5
Q31
D4
D3
D2
D1
FDV301N
DNI
S1
S2
S3
G
Date:
Size
B
Project
Platform Manager 2 Evaluation Board
May 13, 2014
8
7
6
5
1
1
Sheet
Lattice Semiconductor Applications
www.latticesemi.com/techsupport
Board Stack-Up
1
2
3
4
Title
Prototype, Mechanical, and Mounting Holes
G3
E-Friendly
R131
1k
DNI
D4
D3
D2
D1
FDV301N
DNI
M_HOLE1
DI
IW_MNT0
1
MH11
Q30
S1
S2
S3
G
G2
WEEE
Board Logos
M_HOLE1
DI
IW_MNT0
1
1
M_HOLE1
DI
IW_MNT0
1
MH9
MH12
1
2
3
4
G1
Lattice Logo
M_HOLE1
DI
IW_MNT0
1
MH10
1
Q29
S1
S2
S3
G
Board Mounting Holes
1
2
3
4
SMD 2512 Resistor
Package Prototype Area
8
7
6
5
R130
1k
DNI
FDV301N
DNI
S1
S2
S3
G
D4
D3
D2
D1
SOIC-8 Package Prototype Area
Q28
2
1
4
1
74
1
5
C
C
Schematic Rev
Board Rev
16 of 16
A
B
C
D
Platform Manager 2 Evaluation Board
Figure 41. Prototype, Mechanical, and Mounting Holes
Platform Manager 2 Evaluation Board
Appendix F. Known Issues
R264 is not connected to the +3.3 V plane on the board. A blue wire jumper is added to the bottom of the board to
make the required connection for LED D57 to operate as shown in Figure 42.
Figure 42. Connecting R264 to the +3.3 V Plane
For the +12 V DC Buck Converter the package for Q1 was changed from the SOT-223 to the SOT23. The device is
soldered down to pins 2 and 3 of the SOT-223 footprint and jumper wires are attached to the SOT-23 source and
gate pins as shown in Figure 43.
Figure 43. Q1 Package Change and Connections
75