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IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.133
133
IEIE Transactions on Smart Processing and Computing
Power-Efficient Wireless Neural Stimulating System
Design for Implantable Medical Devices
Hyung-Min Lee1,2 and Maysam Ghovanloo1
1
School of Electrical and Computer Engineering, Georgia Institute of Technology / Atlanta, GA 30308, USA
mgh@gatech.edu
2
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology / Cambridge, MA
02139, USA hyungmin@mit.edu
* Corresponding Author: Maysam Ghovanloo
Received May 13, 2015; Accepted June 15, 2015; Published June 30, 2015
* Regular Paper
Abstract: Neural stimulating implantable medical devices (IMDs) have been widely used to treat
neurological diseases or interface with sensory feedback for amputees or patients suffering from
severe paralysis. More recent IMDs, such as retinal implants or brain–computer interfaces, demand
higher performance to enable sophisticated therapies, while consuming power at higher orders of
magnitude to handle more functions on a larger scale at higher rates, which limits the ability to
supply the IMDs with primary batteries. Inductive power transmission across the skin is a viable
solution to power up an IMD, while it demands high power efficiencies at every power delivery
stage for safe and effective stimulation without increasing the surrounding tissue’s temperature.
This paper reviews various wireless neural stimulating systems and their power management
techniques to maximize IMD power efficiency. We also explore both wireless electrical and optical
stimulation mechanisms and their power requirements in implantable neural interface applications.
Keywords: Neural stimulation, Wireless power transfer, Implantable medical devices, Optogenetics
1. Introduction
Implantable medical devices (IMDs) with stimulating
functions have proven to be effective therapies to alleviate
neurological diseases or substitute sensory modalities lost
due to disease or injury [1, 2]. These implantable
stimulators are capable of injecting a designated amount of
charge into the surrounding tissue by providing a precise
amount of output current or output voltage between two or
more electrodes for a predefined period. Deep brain
stimulation (DBS) is one of the most effective examples of
such therapies to treat several diseases, such as Parkinson’s
disease, tremor, and dystonia [3, 4]. However, today’s
DBS devices suffer from having large primary batteries
implanted in the chest, where there is more space available,
instead of the brain. Therefore, they need subcutaneous
interconnects to pass across the neck to reach the
electrodes implanted deep in the brain. This increases the
complexity of implantation surgery and the risks of
mechanical interconnect failure due to head motion [5].
Moreover, batteries need to be replaced every two to five
years through additional surgery. As a promising solution,
a head-mounted DBS can reduce the risk and hardship
imposed by a chest-implanted primary battery and long
interconnects across the neck, replacing them with a pair
of coils and transcutaneous inductive power transfer from
a behind-the-ear (BTE) rechargeable energy source,
similar to cochlear implants or hearing aids [6-8].
Fig. 1 shows a conceptual configuration of a headmounted inductively powered DBS system as an
alternative to the conventional chest-implanted batterypowered DBS [9]. An external processing unit, which
includes a rechargeable battery, provides transcutaneous
power and data through a pair of loosely-coupled coils.
The induced AC input across the implanted coil supplies
the rest of the DBS implant through an efficient powermanagement unit. The DBS system generates stimulus
pulses, which are delivered to the stimulation sites through
individual leads that are significantly shorter than those
from the chest area. Therefore, the head-mounted
inductively-powered system is less invasive and
potentially more suitable for high-density DBS [10]. Like
Lee et al.: Power-Efficient Wireless Neural Stimulating System Design for Implantable Medical Devices
134
DBS burr hole
Implanted wireless
DBS system
Electrode array
(DBS lead)
Implanted coil
Transcutaneous
power and data
transmission
Example of
multi-electrode
stimulation paths
External coil
External
DBS battery
& Processor
Fig. 3. Block diagram of a conventional inductively
powered current-controlled stimulation (CCS) system
with emphasis on key blocks for power transfer.
Electrodes
Fig. 1. Conceptual configuration of a head-mounted
inductively powered DBS system in which power and
data are transferred through an inductive link [9].
additional power losses, further decreasing the overall
stimulation efficiency.
In this paper, we review various inductively powered
neural stimulating systems and their circuit techniques to
increase IMD power efficiency while ensuring safe
stimulation. We also explore the recently introduced
optogenetic stimulation, the optical stimulation of neural
circuits [15], and discuss the power limitations and
potential solutions for implantable wireless optogenetic
stimulators.
2. Inductively Powered Stimulating IMDs
(a)
(b)
Fig. 2. (a) A current-controlled stimulation (CCS)
system stimulating a simplified electrode and tissue
model, (b) the resulting stimulation current and voltage
waveforms.
other wirelessly powered IMDs, high power efficiency is
paramount in reducing the risk of tissue damage from
overheating as well as extending the range of a wireless
power transmission link and external battery life [11, 12].
The next step is adopting efficient stimulating schemes
and power management techniques to further improve
DBS efficiency. Voltage-controlled stimulation (VCS)
enables power-efficient stimulation. However, balancing
the stimulation charge is quite complicated in VCS
because the electrode impedance can vary over time and
position [4, 13]. On the other hand, current-controlled
stimulation (CCS) has been widely used because of its
precise charge control and safe operation by using current
sources [14]. Fig. 2 shows the biphasic (cathodic-anodic)
stimulation current and voltage waveforms when the CCS
system drives a simplified pair of electrodes and tissue
model, a series RS and CDL, which represent tissue
spreading resistance and double-layer capacitance,
respectively. The CCS system is capable of injecting
charge-balanced biphasic stimuli (Q = I × T) by adjusting
stimulation current level, IS, and duration, TS. However, the
CCS system suffers from low power efficiency because of
the dropout voltage across its current sources, particularly
when the stimulation voltage, VSTIM, is much smaller than
the CCS supply voltage. Moreover, inductively powered
stimulating systems with any stimulation mechanism need
a rectifier and a regulator to convert the radio frequency
(RF) input to the DC supply voltage, which results in
Fig. 3 shows a block diagram of a conventional
inductively powered CCS system with emphasis on key
blocks for power transfer to the stimulator outputs. The
wireless transcutaneous power is commonly delivered
from an RF power transmitter (Tx) to an IMD (Rx)
through an inductive link and power management units.
The power Tx, which is supplied by an external energy
source, drives a primary coil, L1, at the power carrier
frequency, fp. An AC signal is induced across a secondary
coil, L2, because of the coils’ electromagnetic flux
coupling. The Rx inductive-capacitive resonance circuit,
L2C2-tank, which is tuned at fp, boosts the AC voltages,
VINP and VINN, across the L2C2-tank. Then, the IMD utilizes
a rectifier to convert the AC input to a DC output, VREC,
followed by a low-dropout (LDO) regulator to generate a
fixed supply voltage, VDD, for the rest of the system.
However, this simple structure wastes a large portion of
the input power across the rectifier, LDO, and current
sources in the CCS method. The LDO loss increases when
VREC, which depends on the AC input amplitude, increases.
The CCS loss also increases as the peak VSTIM, i.e. the
maximum voltage across the electrodes and tissue model
(see Fig. 2), becomes smaller.
Recently, several circuit techniques have been
proposed to improve overall power efficiency in wireless
neural stimulating IMDs. Fig. 4 compares various
inductively powered stimulating structures, while all
structures were assumed to provide bipolar and biphasic
stimulation pulses through a similar pair of electrodes. We
have also assumed that the inductive link can maintain its
peak efficiency against reflected impedance variations as
the stimulator loading changes using a multi-coil inductive
link or adaptive resonant load transformation [16-18]. Here,
we focus on power efficiency of the stimulating IMD,
which can be defined as the ratio of the RF input power
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
135
(a)
Fig. 5. Conceptual block diagram of the inductively
powered wireless stimulating system with adaptive
supply control [9].
(b)
considered as a factor on the biological side to further
improve the stimulus efficacy in addition to the stimulator
efficiency on the IMD side [24, 25].
3. Wireless Stimulating System with
Adaptive Supply Control
(c)
Fig. 4. Various inductively powered stimulating IMD
structures with (a) a fixed output rectifier [19][19], (b) a
dynamic DC-DC converter [20], (c) an external closedloop supply control [21, 22].
from the secondary coil to the stimulator output power
delivered to the tissue.
In Fig. 4(a), a fixed output rectifier was proposed to
generate a predefined constant VREC without an LDO [19].
Eliminating the LDO reduced the loss, but the CCS loss
was still dominant during stimulation, especially when
VSTIM << VREC. It also needs an auxiliary rectifier to supply
the fixed output rectifier. A stimulator from Arfin and
Sarpeshkar [20] utilized a dynamic supply voltage, VIN,
from a DC-DC converter, as shown in Fig. 4(b). It
achieved high efficiency from VCS as well as coarse
current controllability. However, it still required constant
DC input, VREC, from the rectifier, leading to a loss added
to that of the DC-DC converter (ηDCDC = 55 ~ 94%).
In Fig. 4(c), the inductive power delivered to the
stimulator was adjusted through an external closed loop,
changing VREC to be near the peak voltage of VSTIM, leading
to small power loss across the current sources in CCS [21,
22]. However, the external control loop via load-shiftkeying (LSK), which adjusts the inductive coupling by
shorting the L2C2-tank for a short time (< 1 µs), is prone to
interference and can be interrupted in loosely coupled
inductive links, while increasing the system design
complexity. The passive rectifier also induces a larger ACDC loss than the active rectifier, which further decreases
the overall power efficiency [23]. It should be pointed out
that the methods used in these inductively powered
stimulating structures may be used together to improve
overall power efficiency.
Further improving the stimulation power efficiency of
the inductively powered stimulators under limited received
power through the inductive link is highly desired.
Moreover, the shape of the stimulus waveform can also be
In order to achieve both safe and power-efficient
stimulation, a wireless neural stimulating system with
adaptive supply control was proposed [9]. In this system,
the stimulator supply voltage is automatically adjusted
near the required peak stimulation voltage by detecting the
site potential and forming a closed control loop through an
efficient adaptive regulated rectifier. This mechanism
minimizes power losses across current sources in the CCS
as well as the adaptive regulated rectifier, resulting in
higher IMD power efficiency for neural stimulation. The
stimulation system also adopts active charge balancing by
sharing the closed-loop path of the adaptive supply control
to inject small current pulses in the tissue to keep the
residual charges within a safe limit [4, 26].
Fig. 5 shows a conceptual block diagram of the
inductively powered wireless stimulating system with
adaptive supply control. The adaptive regulated rectifier
with active switching is capable of generating a multilevel
DC voltage, VREC, directly from the AC input voltage
across L2 through an internal closed-loop supply control
mechanism. Therefore, VREC, which directly supplies the
CCS without an LDO, is adaptively adjusted close to the
peak of VSTIM, resulting in minimum loss while benefiting
from the safety feature of the CCS. Moreover, the adaptive
regulated rectifier achieves high AC-DC power conversion
efficiency (PCE) by adopting phase control feedback and
active synchronous rectification to improve the overall
power efficiency of the inductively powered stimulator.
In order for the adaptive regulated rectifier to generate
the desired multilevel VREC without using the regulator, the
rectifier turn-on time needs to be adjusted to limit the
forward current, while achieving high PCE. Fig. 6 shows
the simplified voltage waveforms of the rectifier
depending on the turn-on time. Conventional rectifiers aim
to generate the maximum VREC from VIN(AC) at high PCE.
Therefore, they turn on as long as VIN(AC) > VREC, as shown
in Fig. 6(a). Consequently, VREC becomes dependent on the
VIN(AC) amplitude, and it is not internally adjustable. To
internally adjust VREC, the adaptive regulated rectifier
controls the turn-on phase, as shown in Fig. 6(b). In this
method, the rectifier turns on when VIN(AC) > VREC, similar
to the conventional rectifiers. However, its turn-off timing
Lee et al.: Power-Efficient Wireless Neural Stimulating System Design for Implantable Medical Devices
136
(a)
(b)
Fig. 6. Simplified voltage waveforms of (a) the
conventional rectifier, (b) the adaptive regulated
rectifier with turn-on phase control.
Fig. 8. Overall power efficiencies of stimulating IMDs
with adaptive supply control and fixed supply [9].
4.6 V. The adaptive supply control leads to higher overall
power efficiency (41 ~ 58%), which includes efficiencies
of the adaptive regulated rectifier and the current
stimulator, compared with using the fixed supply (27 ~
55%).
Fig. 7. Schematic diagram of the current-controlled
stimulator with low dropout 5-bit current sources and
active charge balancing [9].
is controlled to limit the forward current. Therefore, VREC
is adjustable depending on the rectifier turn-on phase,
while the small dropout voltage between VIN(AC) and VREC
during the on period provides high PCE.
Fig. 7 shows a schematic diagram of a currentcontrolled stimulator [9]. The current stimulator is
equipped with a pair of low-dropout 5-bit current sources,
while being supplied from the adaptive VREC, as shown in
Fig. 5. Feedback loops using AMP2-5 set the drain-source
voltages of P14 ~ P18 and N15 ~ N19 at ~60 mV in the triode
region. Therefore, the voltage headroom of the output
stage, VHead, can drop down to VDS,sat + 60 mV, which is
smaller than 2VDS,sat of a typical cascode output stage. The
two current stimulators source and sink at the same time,
providing a bipolar stimulation compliance voltage of VREC
- 2VHead. The 5-bit current sources with binary-weighted
transistors are placed at the output stage directly to reduce
the stimulator power loss, compared to using current
mirrors after a 5-bit current DAC in [21]. In addition, the
active charge balancing circuits push or pull additional
small current pulses to the load after stimulation until the
residual site voltage settles within a ±50 mV safety
window [26]. This scheme is capable of estimating the
required charge-balancing period.
Fig. 8 compares the overall power efficiency vs. ISTIM
between using an adaptive supply, VREC, and a fixed supply,
VDD, when stimulating the series RC model with RS = 2 kΩ
and CDL = 500 nF for TS = 400 μs. The adaptive supply
control automatically adjusts VREC between 2.5 V and 4.6
V with 0.3 V increments, while the fixed supply sets VDD =
4. Wireless Switched-Capacitor
Stimulation (SCS) System
Switched-capacitor stimulation (SCS), proposed in [27],
takes advantage of both high efficiency of VCS and safety
of CCS by using capacitor banks to transfer quantized
amounts of charge to the tissue. Vidal and Ghovanloo [13]
only presented a discrete version of the SCS with no onchip integration. The stimulating system of Kelly and
Wyatt [28] also adopts the SCS mechanism to construct
pseudo-rectangular stimuli, using multiple decaying
exponential pulses, but it suffers from poor voltage-based
capacitor charging efficiency, which is always less than
50%.
Recently, an integrated wireless SCS system was
proposed [29], which has inductive capacitor charging and
charge-based stimulation capabilities for energy-efficient
stimulation. Fig. 9 shows the conceptual block diagram of
the inductive power flow from the external energy source
to the tissue in the SCS systems as well as the resulting
stimulus waveform. The streamlined inductively powered
SCS efficiently charges the storage capacitors directly
from the inductive link and delivers the quantized stored
charge to the electrode/tissue, modeled by a series RC,
improving stimulator efficiency. In addition, the SCS
system is capable of generating a decaying exponential
stimulus by dumping the capacitor charge in the tissue
without wasting additional power. This decaying
exponential stimulus can be equally, if not more, effective
in activating a larger target tissue area, compared to the
conventional rectangular stimuli, while consuming the
same amount of energy, thus improving both stimulus
efficacy and safety [24, 25].
Fig. 10 shows a simplified block diagram of the SCS
system that can efficiently charge a positive/negative
capacitor bank, CP and CN, directly from AC input voltage
137
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Fig. 9. Conceptual diagram of the wireless switchedcapacitor stimulating (SCS) system [29].
Fig. 10. Simplified block diagram of the SCS system
with a focus on wireless capacitor charging and charge
transfer to the tissue [29].
through a series capacitor, CS, and an inductive charger, to
improve capacitor charging efficiency. For efficient
stimulation, the capacitor bank stores the energy being
wirelessly delivered across the skin from the external
battery and then transfers quantized amounts of the stored
charge to the tissue. The charge stored in the capacitors is
delivered to the load (i.e. two electrodes and the tissue in
between) in a quantized fashion (Q = C × V) through lowresistance switches, which minimize the power losses,
while creating exponentially decaying pulses. This SCS
mechanism not only improves overall IMD power
efficiency to ensure highly efficient charge-based
stimulation, but also creates a buffer between the inductive
link and the highly variable load without using any
rectifiers and regulators.
For biphasic stimulation, the storage capacitor pairs are
alternately connected to the electrodes, injecting negative
and positive charges into the tissue to evoke neural activity.
A charge monitoring (CM) circuit measures the amount of
injected charge and dynamically changes the pulse width
of the subsequent stimulus to neutralize the residual charge
in the tissue. Discharged capacitor pairs are continuously
recharged to their target voltages, while a secondary
charge balancing (CB) circuit prevents residual charge
accumulation by shorting electrodes to ground for a
predefined period following stimulation.
Table 1 benchmarks the state-of-the-art wireless neural
stimulating systems with emphasis on their overall power
efficiencies. The inductively powered stimulating systems,
which utilize CCS or VCS, require the rectifier, regulator,
current driver, and even DC-DC converter to generate
rectangular stimuli, while power losses at each stage result
in poor overall stimulation efficiencies. On the other hand,
the SCS systems can generate decaying exponential pulses,
which can be more effective in activating neural tissue
than rectangular pulses while consuming the same amount
of stimulus energy. The overall SCS power efficiency
mainly depends on its capacitor charging efficiency, which
needs to be optimally designed. It should be noted that the
overall stimulation efficiency may also vary depending on
electrode/tissue impedance as well as stimulus pulse width
in various applications.
5. Wireless Optogenetic System
Optical stimulation of genetically modified neurons,
known as optogenetics, has become an effective way to
selectively generate neural activity using various lightdelivery schemes. Optogenetics enables fast, spatially
controlled, and minimally invasive modulation of target
cells compared to electrical stimulation [31]. In addition,
the optical stimulation is capable of eliminating electrical
artifacts, while enabling extended lifetime by hermetic
sealing of the light sources [32].
There are several light-delivery schemes for optical
stimulation, such as a laser-coupled optical fiber and a
single light-emitting diode (LED). However, they suffer
Table 1. Inductively powered stimulating system benchmarking.
*
Publication
2010 [30]
2012 [20]
2013 [9]
2011 [28]
2015 [29]
0.35 µm
Technology
0.18 µm HV
0.35 µm
0.5 µm
1.5 µm
Stimulator structure
CCS
VCS + CCS
Adaptive CCS
SCS
SCS
Supply voltage (V)
±12
3.3
2.5 ~ 4.6
±1.75 (Cap)
±2 (Cap)
Rect. + Reg.
Max.
DC-DC
stimulator
power
Current drv.
efficiency Charger+Sw
(%)
Total
85.6
80*
87
-
-
-
74**
-
-
-
41.6
-
68
-
-
-
-
-
40***
80.4
35.6
59**
59
40
80.4
Current stimulus shape
Rectangular
Rectangular
Rectangular
Decaying expo.
Decaying expo.
Injected ISTIM (mA)
0.5
0.45
1.45
0.4 (peak)
4 (peak)
Series RC model
10kΩ + 100nF
1kΩ + 0.93μF
2kΩ + 0.5μF
1.15kΩ + 1μF
0.5kΩ + 1μF
Assuming a rectifier is needed,
**
averaged,
***
including power consumption of the other blocks.
138
Lee et al.: Power-Efficient Wireless Neural Stimulating System Design for Implantable Medical Devices
(a)
Fig. 11. Conceptual diagram of the conventional
wireless optogenetic system with an LED driver [34].
from poor spatial resolution and tethering effects through
wires and optical fibers. Recently, a multichannel 3-D
optrode array, which integrates micro-LEDs with microneedle waveguides, was proposed to minimize light
scattering in the tissue and achieve high spatial resolution
for long-term implantable optogenetics [33].
However, LEDs typically require high instantaneous
power to emit sufficient light for optical neural stimulation,
which can be a significant limiting factor in conventional
IMDs [34]. Fig. 11 shows a conceptual diagram of the
conventional inductively powered optogenetic system,
which requires the rectifier and the regulator to convert AC
input voltage to DC output voltage for supplying the LED
driver. Power losses in these stages result in poor overall
power efficiency from L2 to the LEDs. In addition, the
high instantaneous power that flows to the LEDs leads to
large load variation, which affects impedance matching
with the inductive link. This can significantly increase the
required inductive power level and create a safety issue by
increasing the temperature while degrading the inductive
link’s power efficiency, due to impedance mismatch, and
the supply voltage for the rest of the IMD.
To address these limitations, the SCS mechanism is
utilized for power-efficient implantable optogenetics, as
shown in Fig. 12(a) [35]. The SCS-based optogenetic
system can efficiently charge an array of storage capacitors
directly from the inductive link and periodically discharge
them into the micro-LEDs, providing high instantaneous
current without burdening the inductive link and system
supply voltage. The efficient wireless capacitor charger
also improves the optical stimulation power efficiency.
After charging, a storage capacitor pair, CP and CN, can be
connected in series to provide higher pulse-based LED
driving voltage, VLED, as shown in Fig. 12(b).
6. Conclusion
Wireless neural stimulating systems require high
stimulation power efficiency to perform effective therapies
through multiple sites, without raising the surrounding
tissue temperature, and to operate with their limited
available transcutaneous power. Various circuit and
system-level techniques can be utilized in stimulating
IMDs to efficiently generate stimulus pulses from the RF
input power and precisely deliver them to the tissue.
Power-efficient wireless stimulating systems can activate
the target tissue with a minimum amount of energy from
the inductive link, providing multiple advantages, such as
extended-range wireless power transfer, less volume or
(b)
Fig. 12. (a) Conceptual diagram of the SCS-based
wireless optogenetic system, (b) its pulse-based
output voltage to drive LEDs [35].
longer lifetime of the external power Tx battery, a wide
range of stimulus energy levels, efficacious and safe
stimulation, and a lower risk of tissue damage from
overheating.
Acknowledgement
This work was supported in part by National Institute
of Biomedical Imaging and Bioengineering grant
1R21EB018561 and the National Science Foundation
under awards IIP-1439426, ECCS-1407880, and ECCS1408318.
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Hyung-Min Lee received a BSc in
electrical engineering (summa cum
laude) from Korea University, Seoul,
Korea, in 2006, an MSc in electrical
engineering from the Korea Advanced
Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2008,
and a PhD in electrical and computer
engineering from Georgia Institute of Technology, Atlanta,
GA, USA, in 2014. He is currently a postdoctoral associate
in the Department of Electrical Engineering and Computer
Science, Massachusetts Institute of Technology (MIT),
Cambridge, MA, USA. His research interests include
analog/mixed-signal/power-management integrated circuit
and system design for implantable biomedical applications.
Dr. Lee received Silver Prizes in the 16th and 18th
Human-Tech Thesis contest from Samsung Electronics,
Korea, in 2010 and 2012, respectively, and a
Commendation Award associated with the 4th Outstanding
Student Research Award from TSMC, Taiwan, in 2010.
He is a member of the IEEE.
Copyrights © 2015 The Institute of Electronics and Information Engineers
Maysam Ghovanloo received a BSc
in electrical engineering from the
University of Tehran, Tehran, Iran, in
1994, an MSc in biomedical engineering
from the Amirkabir University of
Technology, Tehran, Iran, in 1997, and
an MSc and a PhD in electrical
engineering from the University of
Michigan, Ann Arbor, MI, USA, in 2003 and 2004,
respectively. From 2004 to 2007, he was an Assistant
Professor in the Department of Electrical and Computer
Engineering, North Carolina State University, Raleigh, NC,
USA. He joined the faculty of the Georgia Institute of
Technology, Atlanta, GA, USA, in 2007, where he is
currently an Associate Professor and the Founding
Director of the Georgia Tech Bionics Lab in the School of
Electrical and Computer Engineering. He has authored or
coauthored more than 150 conference and journal
publications. Dr. Ghovanloo is an Associate Editor of
IEEE Transactions on Biomedical Circuits and Systems
and IEEE Transactions on Biomedical Engineering. He is
the general chair of the 2015 IEEE Biomedical Circuits
and Systems (BioCAS) Conference. He served on the
IEEE International Solid-State Circuits Conference
(ISSCC) subcommittee for imagers, MEMS, medical, and
displays from 2010-2014. He received awards in the 40th
and 41st DAC/ISSCC Student Design Contests. He
organized special sessions and was a member of technical
review committees for several major conferences, such as
ISSCC and ISCAS, in the areas of biomedical circuits,
sensors, and systems. He is a member of Tau Beta Pi,
Sigma Xi, the IEEE Solid-State Circuits Society, the IEEE
Circuits and Systems Society, and the IEEE Engineering in
Medicine and Biology Society. He is a senior member of
the IEEE.
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.141
141
IEIE Transactions on Smart Processing and Computing
A Stability-Secured Loop Bandwidth Controllable
Frequency Synthesizer for Multi-Band Mobile DTV Tuners
Kyeong-Woo Kim, Muhammad Abrar Akram, and In-Chul Hwang
Department of Electrical & Electronics Engineering, Kangwon National University / Chuncheon, 200-701, Korea
{kwkim1104, abrar, ihwang}@kangwon.ac.kr
* Corresponding Author: In-Chul Hwang
Received May 21, 2015; Accepted June 15, 2015; Published June 30, 2015
* Short Paper
Abstract: A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV
tuners is proposed, it’s loop bandwidth can be calibrated to optimize integrated phase noise
performance without the problem of phase noise peaking. For this purpose, we proposed a new
third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase
margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary
metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing
while the loop bandwidth increases by up to three times.
Keywords: Frequency synthesizer, Phase-lock loop (PLL), Loop filter (LF), Loop bandwidth (LBW), Chargepump circuit (CPC), Phase noise peaking
1. Introduction
Broadband radio frequency synthesizers for multi-band,
multi-standard mobile DTV tuners require stringent
integrated phase noise (IPN) or phase jitter specifications
to support complex baseband demodulation [1, 2]. Also, it
is more important that the uniform performance of IPN
must be retained against the voltage-to-frequency gain of
the voltage-controlled oscillator (VCO) and the phase-lock
loop (PLL) multiplication factor, as both experience a wide
range of variation over broadband.
Typically for this purpose, calibration of loop
bandwidth (LBW) is applied to each band to suppress
phase noise particularly close-in phase noise and spurs to
get the optimal IPN. In many cases, such calibration is
achieved by controlling charge-pump circuit (CPC) current,
since it affects only the LBW, unlike resistors in a loop
filter. However, calibrating LBW while confined within
poles and zero fixed by passive filters causes an issue of
excessive jitter peaking around the LBW, because openloop phase margin is degraded more as LBW approaches
to the poles or zero more closely.
The effect of jitter peaking, intense as marginal
stability is reached, is one of the main factors that degrade
IPN performance. So, the LBW should be controlled
within a range where stability must not be degraded.
To avoid the issue of stability, we propose a stabilitysecured LBW-controllable PLL with a pole-zero scalable
loop filter and a current-scalable CPC. When these two
circuits are combined with a common bias source, the
proposed PLL provides LBW calibration while keeping a
constant phase margin. In this paper, we present a secondorder scalable loop filter, including third-order filter
conversion and its application for the fractional-N
frequency synthesizer with a MASH 1-1-1 sigma-delta
modulator (SDM).
2. Circuit implementation
Fig. 1 shows a frequency synthesizer designed with a
fractional-N PLL to support the multi-band receiver
including Frequency Modulation (FM), Terrestrial Digital
Multimedia Broadcasting (T-DMB), Digital Video
Broadcasting-Handheld (DVB-H), and Integrated Services
Digital Broadcasting-terrestrial (ISDB-T), where VCO
needs to cover 2.4GHz to 3.6GHz if we use a Local
Oscillator (LO) planning based on the divider-by-2 circuit
only.
The designed frequency synthesizer is composed of a
Phase Frequency Detector (PFD), the second-order
scalable loop filter, a scalable CPC, a first-order passive
142
Kim et al.: A Stability-Secured Loop Bandwidth Controllable Frequency Synthesizer for Multi-Band Mobile DTV Tuners
Fig. 1. A block diagram of the proposed frequency synthesizer.
Fig. 2. The proposed second-order scalable loop filter and scalable CPC.
filter, a VCO, dividers, and a MASH 1-1-1 sigma-delta
modulator. The VCO is designed with a complementary gm
cell and a seven-bit binary-weighted capacitor bank to
minimize the variation in VCO gain. To avoid a gap
between frequency segments, the overlap between adjacent
center frequencies of a segment is designed to be 50% or
more. Switches S1 and S2 are used to connect the first RC
filter for third-order filter conversion, which is required to
reject the third-order SDM noise from the MASH 1-1-1.
Fig. 2 shows a circuit diagram of the proposed secondorder scalable loop filter and scalable CPC. The original
concept was presented by Hwang [3], but this design is
enhanced to include a differential CPC so that it solves the
problems of voltage headroom and glitch-induced spur by
charge sharing.
The proposed circuit is composed of a V-to-I converter,
loop filter core, and CPC. In the V-to-I converter, the input
voltage (VB) is converted to the basic current (IB) and MN2
is a replica transistor of MN4, so we can change gm as well
as ID of the MN4 through MN2 indirectly. The variables, a
and b, represent the size multiplication factor of the
corresponding branches in terms of the basic aspect ratios:
AP=Wp/Lp in a positive-channel metal oxide semiconductor
and AN=Wn/Ln in a negative metal oxide semiconductor.
The loop filter core provides the given second-order
characteristics as follows, where the output resistance seen
in MN5 and MP6 is assumed to be large enough for
simplicity of calculation.
vLF ( s )
iLF ( s )
(1)
(C1 + C2 ) / C1
1 + s / wz
1
=
×
×
1+ a
g m, M N 4 ( s / w z )(1 + s / w p )
Z LF ( s ) =
wz =
wp =
g m, M N 4
C1 + C2
(1 + a) g m, M N 4
C2
=
mn C ox AN (VB - VT )
=
mn C ox (1 + a ) AN (VB - VT )
C1 + C2
C2
(2)
(3)
where wz and wp are the zero and the non-zero poles in
radian frequency, respectively.
The whole transfer function (HT(s)) including CPC
current can be calculated as
H T ( s ) = I CPC × Z LF ( s )
é (C + C2 ) b (VB - VT ) ù
1 + s / wz
=ê 1
×
×
ú×
1+ a
2
ë C1
û ( s / w z )(1 + s / w p )
This equation results in the loop bandwidth (wB) in
radians as follows:
143
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
(a)
Fig. 4. Microphotograph of the fabricated chip.
(b)
Fig. 3. The effect of the scalable loop filter on phase
margin (a) conceptual diagram for LBW location within
pole and zero, (b) phase margin vs. LBW scaling.
ωB = (1 +
C2 K 0
b VB − VT
⋅
⋅
)⋅
C1 N div 1 + a
2
In passive filters having non-scalable poles and zero,
movement of ωB in any direction degrades phase margin,
because it approaches ωz or ωp1. But the scalable loop filter
blocks the degradation of phase margin because ωB is
moved, accompanied by ωz and ωp1, as shown in Fig. 3(a),
even though ωp2 is fixed in position.
To quantify the effect, Fig. 3(b) plots the variation of
phase margin caused by the LBW scaling. For comparison
purposes, the upper two curves represent the phase margin
with a second-order filter when ωp2 is assumed to be
infinity. As expected, the phase margin is kept constant at
the scalable filter, but drops at the passive filter. Also in
the third-order filter, we observe that the scalable loop
filter blocks the abrupt degradation of phase margin, and
even the worst phase margin is better than that of the
second-order non-scalable filter.
(4)
where VCO gain and the frequency multiplication factor
are KO and Ndiv, respectively.
With this set of equations, we can say that the
fractional ratios between ωz, ωp1, and ωB are kept constant,
independent of scaling ωB, and therefore, phase margin can
be constant. Also, the proposed circuit saves silicon area
because it reuses capacitor C2 with its value rescaled by
1/(1+a) for the pole composition, while the sum of C1 and
C2 builds up the zero.
As another remarkable advantage, the proposed
second-order scalable loop filter can be easily converted
into a third-order one by adding a series RC filter as shown
in Fig. 1, which provides an additional fixed pole at ωp2
(~1/R2C2).
We can analyze the effect of the second-order scalable
filter on phase margin in the third-order filter by a
comparison with a passive filter having fixed poles and
zero.
Fig. 3(a) shows a conceptual diagram that represents
locations of poles and zero in the open-loop transfer
function of the PLL with the third-order loop filter having
two poles at DC(0 Hz) frequency , one zero at ωz, and two
non-zero poles at ωp1 and ωp2. For this analysis, we assume
that the LBW (ωB) is placed equally four times apart from
the boundary set by ωz and ωp1, respectively, as a rule of
thumb.
3. Measurement results
Fig. 4 shows a microphotograph of the proposed
fractional-N PLL, fabricated with a TSMC 180nm
complementary metal-oxide semiconductor (CMOS)
process.
Fig. 5(a) shows the transient response monitored via
VTUNE with a test mode (the second-order filter) where the
RC filter is bypassed and the SDM is turned off while the
PLL is in transition mode under three different conditions
of VB. Voltage VB is provided by an on-chip programmable
four-level voltage divider controlled by Vsel[3:0], which
can have the values of “1000”, “0100”, “0010”, and
“0001”, measured to provide 750mV, 665mV, 582mV, and
507mV, respectively. With VT≈500mV, therefore, the three
conditions of “0010”, “0100”, and “1000” can provide 1x,
2x, and 3x the loop bandwidth, respectively. This variation
of the LBW causes the corresponding difference in lock
time in Fig. 5(a).
Phase margin (ΦM) is difficult to measure directly,
because it is an open-loop small-signal parameter. But, we
can calculate it using the damping ratio (ζ) that can be
measured at the transient response of the PLL, as given in
Eq. (5).
Φ M = tan −1
2ζ
−2ζ 2 + 1 + 4ζ 2
(5)
144
Kim et al.: A Stability-Secured Loop Bandwidth Controllable Frequency Synthesizer for Multi-Band Mobile DTV Tuners
(a)
Fig. 6. Plot of SSB phase noise with the third-order
scalable filter and MASH 1-1-1.
4. Conclusion
(b)
Fig. 5. PLL acquisition with a second-order scalable
filter over three different conditions of the LBW (a)
Measured oscilloscope waveform, (b) Waveforms
normalized with respect to natural frequency(fn).
For this purpose, Fig. 5(b) plots the transient response
using the time axis normalized with a damped natural
frequency (fn), where we can show that the three curves
have the same damping ratio (z), thus the same phase
margin when it is estimated with the first peak (A1) and
the second peak (A2).
z =
ln( A1 / A2)
2
p + [ln( A1 / A2)]2
(6)
Fig. 6 shows a plot of the single sideband phase noise
from the designed frequency synthesizer, with the normal
mode where the third-order filter is connected and the
SDM is turned on. With the same conditions on VB as
given above, the phase noise is measured when the LBW is
1x, 2x, and 3x. In this figure, we can see that phase noise
peaking is blocked within a tolerable range. The overall
performance of phase noise meets the requirement for
multi-band, multi-standard mobile DTV tuners when
divided into the required bands.
Copyrights © 2015 The Institute of Electronics and Information Engineers
The proposed scalable filter and scalable CPC enables
the design of a stability-secured LBW-controllable PLL,
which prevents the degradation of phase margin and thus
phase noise peaking while its loop bandwidth is tuned
targeting the best IPN in each band.
The fractional-N PLL for multi-band and multistandard mobile DTV tuners, fabricated with a TSMC
180nm CMOS process, has shown that the third-order
filter, based on a second-order scalable filter, with the
property of constant damping effectively rejects the SDM
noise from the MASH 1-1-1, adds little noise to close-in
phase noise, and prevents phase noise peaking from
growing while its LBW increases by up to three times.
Acknowledgement
This research was supported in part by the UniversityIndustry Cooperation Foundation of Kangwon National
University, Chuncheon, Korea, and in part by the Ministry
of Science, ICT & Future Planning (MSIP), Korea, under
the Convergence Information Technology Research Center
(C-ITRC) support program (NIPA-2013-H0401-13-1002)
supervised by the National IT Industry Promotion Agency
(NIPA).
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(2010) 92. Article (CrossRef Link)
[3] I. Hwang: IEEE Microwave & Wireless Components
Letter 22 (2012) 324. Article (CrossRef Link)
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.145
145
IEIE Transactions on Smart Processing and Computing
A Multi-bit VCO-based Linear Quantizer with Frequencyto-current Feedback using a Switched-capacitor Structure
Sangyong Park, Hyuk Ryu, Eun-Taek Sung, and Donghyun Baek
School of Electrical Engineering, Chung-Ang University / Seoul, Republic of Korea
* Corresponding Author: Donghyun Baek
Received May 28, 2015; Accepted June 10, 2015; Published June 30, 2015
* Short Paper
Abstract: In this letter, we present a new linearization method for a voltage controlled oscillator
(VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO
generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of
the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to
effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by
more than 53 dB. And a VCO-based quantizer employing the proposed linearization method
achieves a high SNDR of 74.1 dB.
Keywords: VCO, Quantizer, Low harmonic distortion, Frequency-to-current feedback
1. Introduction
Recently, there are difficulties in voltage-domain
circuit design with decreases in supply voltage with
complementary metal-oxide semiconductor (CMOS)
technology scaling down. But time resolution has
improved to under tens of picoseconds in the 90nm CMOS
process because the effect of the parasitic component is
decreased [1]. Therefore, design of time-based circuits (for
example, the frequency-to-digital converter (FDC) or the
time-to-digital converter (TDC) using a sub-micron CMOS
process, is of great interest.
The VCO-based quantizer is usually composed of a
VCO and a phase counter, as shown in Fig. 1(a). A VCO
generates the phase proportionally by input voltage. The
output frequency is quantized by counting edges using a
phase counter, such as a FDC. The quantization noise of
the previous sample affects that of the current sample,
because the VCO generates continuous phase output. So, a
VCO-based quantizer can achieve inherent first-order
quantization noise shaping [2].
The main design difficulty of a VCO-based quantizer is
attributed to the nonlinearity of the VCO gain, as depicted
in Fig. 1(b), which generates harmonic spurs as illustrated
in Fig. 1(c), and consequently, reduces the SNDR and
effective number of bits (ENOB) of a quantizer. Several
techniques have been proposed to compensate for this
nonlinearity. Kim et al. [2] used a digital reverse-mapping
circuit of the nonlinear VCO gain using an external FPGA
at the end of the quantizer. Hamilton et al. [3] and Yoon et
al. [4] employed two identical VCO-based quantizers to
remove odd harmonic spurs. However, even harmonics
still remain. Iwata et al. [5] and Straayer and Perrott [6]
employed analog feedback using a digital-to-analog
converter (DAC), which needs many complex analog
components.
In this paper, we present a simple and effective
linearization technique for reducing harmonic distortion of
a VCO-based quantizer using frequency-to-current
feedback, which can be easily integrated in a small chip
area and can suppress all the harmonic spurs.
2. Linearized Multi-bit VCO-based
Quantizer Design
Fig. 2(a) shows a block diagram of the proposed VCObased quantizer. The frequency-to-current feedback
structure for improving the linearity of the VCO is applied.
First of all, the phase counter changes the VCO output
phase to a digital code at every clock edge. At the same
time, the output frequency of the VCO is sampled and is
converted to current in the frequency-to-current (FC)
converter. The converted current is compared with input
current Vin/R. The error current is integrated into the loop
146
Park et al.: A Multi-bit VCO-based Linear Quantizer with Frequency-to-current Feedback using a Switched-capacitor Structure
(a)
Fig. 3. The nonlinear model of the proposed VCObased quantizer.
(b)
(c)
Fig. 1. A conventional VCO-based quantizer (a) Block
diagram, (b) Nonlinear VCO gain, (c) Output spectrum.
steady state with the FC converter current and the
reference current Vref/RB. Assuming the operation amplifier
is ideal, the node equation can be obtained by applying
Kirchhoff’s current law with the input current [7].
vin − Vint Vref − Vint
+
= f vco ⋅ C1 Vref − Vint
RA
RB
(
)
(1)
The reference voltage Vref is usually set to VDD. And if
all the circuits are realized differentially, Vint can be set to
zero. Then, rearranging the above equation, the VCO
output frequency becomes
f vco =
(a)
v
1
1
+ in
= f c + Δf ⋅ vin
RB C1 VREF RAC1
(2)
where fc is the center frequency, and ∆f is the tunable
frequency range. The center frequency and the tunable
range can be adjusted independently by RA, RB, and C1.
3. Nonlinearity Reduction
(b)
Fig. 2. The proposed VCO-based quantizer (a) Block
diagram, (b) Detailed circuit.
filter. And finally, output voltage of the loop filter controls
the VCO.
The detailed circuit is shown in Fig. 2(b). The VCO
makes 31 phases in the proposed structure. The phase
counter consists of the 31 arrays, and each one is
composed of two D flip-flops and a subtractor as the XOR
gate. Counting the VCO edge’s previous and current clock
makes the thermometer 31-bit output data from the
difference of the previous and current counting data [2, 6].
Consequently, we achieve the binary five-bit output value
from the thermometer 31-bit data using the thermo-tobinary decoder. The switched capacitor circuit, which is
driven by one of the 31-phase VCO outputs through the
non-overlapping phase generator (NOPG), is employed for
frequency-to-current conversion. The switched capacitor
acts as a resistor, inversely proportional to the clock
frequency, with a value of 1/(C1·fvco). The net current
through the integrating capacitor C2 should be zero in the
The relationship between the frequency and the control
voltage of a VCO can be simplified in the phase domain,
as shown in Fig. 3. The nonlinear relation between the
frequency of the VCO and the control voltage can be
expressed as:
f vco = K vco ⋅ vc + a2 ⋅ vc2 + ⋅⋅⋅ = K vco ⋅ vc + f nl
(3)
The first term (Kvco·vc) represents the linear part; the
second and third terms (fnl) designate the nonlinear parts.
The nonlinear part generates the harmonic spurs in the
output. In the proposed architecture, these harmonic spurs
originating from the VCO nonlinearity can be considerably
reduced through negative feedback, and the amount of
reduction can be estimated by the transfer function
between ϕvco and ϕnl:
⎛
⎜
φvco
= 20 ⋅ log ⎜
φnl
⎜
⎝
f f , harm
(
f f2, harm + Vref ⋅ C2 ⋅ K vco C1
)
2
⎞
⎟
⎟
⎟
⎠
(4)
where ff,harm is the harmonic frequency of the input signal,
fvco=dϕvco/dt, and fnl=dϕnl/dt. Since the transfer charac-
147
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Table 1. Summary of the recently reported VCO-based
quantizers.
Name
Configuration
Kim et al.
Digital
[2]
Compensator
Yoon et al.
Harmonic
[4]
Cancellation
Straayer,
and Perrott DAC Feedback
[6]
This Work FCC Feedback
Fig. 4. Simulated output frequencies of the conventional VCO and the one with the FCC feedback vs.
control voltage.
(a)
(b)
Fig. 5. Simulation result of the proposed VCO-based
quantizer using Verilog-A (a) fin = 100 kHz, (b) fin = 1
MHz.
teristic is expressed as a high-pass filter, the lower is the
applied input frequency of the quantizer, and the higher
harmonic reduction is achieved.
4. Simulation Results
The proposed VCO-based quantizer is simulated using
Verilog-A, where Vref = 1 V, fclk = 1 GHz, RA= RB = 20 kΩ,
C1= 100 fF, and C2 = 500 fF. A center frequency of fc is
determined by 1/RB·C1 = 500 MHz with Eq. (2). A 31phase ring-type VCO is used with a control voltage range
of 0.1 – 0.9 V. Fig. 4 shows the simulated nonlinear VCO
gain with a tuning range of 0.1 - 0.9 GHz and also the
linearized VCO gain after the FCC feedback is applied.
The frequency of the linearized VCO is measured at the
output of the VCO in front of the phase count. A
significant linearity improvement is achieved without
changing the original gain.
The output spectrums of the proposed quantizer and
conventional quantizer are shown in Fig. 5; 20 dB noise
slopes are attributed to the first-order noise shaping
characteristics of the phase counter using D flip-flops. As
expected, high second and third harmonic spurs appear in
the conventional VCO-based quantizer, as shown in Fig.
1(a). However, the harmonic spurs dwindle substantially
fclk
BW
(MHz) (MHz)
SNR
(dB)
SNDR
(dB)
500
1
68.4
62
100
5
58.2
56.5
950
10
86
72
1000
5
76.52
74.1
with the proposed FCC feedback applied. Second
harmonic spurs decrease by about 53 dB and 33 dB, or
more, with input frequencies of 100 kHz and 1 MHz,
respectively, and third harmonic spurs suppress roughly
more than 49 dB and 29 dB in both frequencies,
respectively. The amount of the harmonic reduction is well
matched with the expected value from Eq. (4).
Table 1 presents the comparisons of the recently
reported VCO-based quantizers. The proposed quantizer
shows comparable or superior performance due to the
novel switched capacitor linearization technique, despite
the simple linearization scheme.
5. Conclusion
A new linearization method for a VCO-based quantizer
with low harmonic distortion is proposed. The nonlinearity
of the VCO is effectively suppressed with a frequency-tocurrent feedback (FCC) configuration. Both even and odd
harmonic spurs are simultaneously reduced in the proposed
VCO-based quantizer. Second harmonic spurs decrease
approximately 53 dB and 33 dB more with input
frequencies of 100 kHz and 1 MHz, respectively, and third
harmonic spurs decrease about 49 dB and 29 dB more in
both frequencies. The proposed VCO-based quantizer
achieves a high SNDR of 74.1 dB.
Acknowledgement
This research was partly supported by the Industrial
Core Technology Development Program (No.10049138)
funded by the Ministry of Trade, Industry & Energy and
by the Basic Science Research Program through the
National Research Foundation of Korea (NRF) funded by
the Ministry of Education (No.2013R1A1A2060885).
References
[1] Minjae Lee and Asad A. Abidi, “A 9b, 1.25 ps
resolution coarse-fine time-to-digital converter in 90
nm CMOS that amplifies a time residue”, IEEE J.
Solid-State Circuits, vol. 43, no. 4, pp. 769-777, Apr.
2008. Article (CrossRefLink)
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Park et al.: A Multi-bit VCO-based Linear Quantizer with Frequency-to-current Feedback using a Switched-capacitor Structure
[2] J. Kim, T. Jang, T. Yoon, and S. Cho,
design of voltage-controlled oscillator
to-digital converter,” IEEE Circuits
Regular Papers, vol. 57, no. 1, pp.
“Analysis and
based analogand Syst. I.
18-30, 2010.
Article (CrossRefLink)
[3] J. Hamilton, S. Yan, and T.R. Viswanathan, “A
discrete-time input ∆∑ quantizer Architecture using a
dual-VCO-based integrator,” IEEE Trans. Circuits
and Syst. II. Express Briefs, vol. 57, no. 11, pp. 848852, 2010. Article (CrossRefLink)
[4] Y. G. Yoon, M. C. Cho, and S. Cho, “A linearization
technique for voltage controlled oscillator-based
quantizer,’ in Proc. International SoC Design
Conference (ISOCC), 2009, pp. 317-320. Article
(CrossRefLink)
[5] A. Iwata, N. Sakimura, M. Nagata, and T. Morie,
“The architecture of delta sigma analog-to-digital
converters using a voltage-controlled oscillator as a
multibit quantizer,” IEEE Trans. Circuits and Syst. II,
Analog and Digital Signal Processing, vol. 46, no.7,
pp. 941-945, 1999. Article (CrossRefLink)
[6] M. Z. Straayer, and M. H. Perrott, “A 12-Bit, 10MHz bandwidth, continuous-time delta-sigma
quantizer with a 5-bit, 950-MS/s VCO-based
quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4,
pp. 805-814, 2008. Article (CrossRefLink)
[7] N. Sasidhar, R. Inti, and P. Hanumolu, “Low-noise
self-referenced CMOS oscillator,” Electronics letters,
vol. 45, no. 18, pp. 920-9212, 2009. Article
(CrossRefLink)
Copyrights © 2015 The Institute of Electronics and Information Engineers
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.149
149
IEIE Transactions on Smart Processing and Computing
A Capacitively Coupled Multi-Stage LC Oscillator
Cheonwi Park1, Junyoung Park2, and Byung-Geun Lee1,*
1
2
School of Mechatronics, Gwangju Institute of Science and Technology / Gwangju, South Korea bglee@gist.ac.kr
Samsung Electronics / Suwon, South Korea
* Corresponding Author: Byung-Geun Lee
Received May 30, 2015; Accepted June 15, 2015; Published June 30, 2015
* Short Paper
Abstract: Coupling with a ring of capacitors introduces in-phase coupling current in multi-stage LC
oscillators, increasing coupling strength and phase spacing accuracy. Capacitive coupling is
effective at high-frequency applications because it increases coupling strength with the operating
frequency. However, capacitive loading from the ring lowers operating frequency and reduces the
tuning range. Mathematical expressions of phase noise and phase spacing accuracy with capacitive
coupling are examined here, and transistor-level simulations confirm the effectiveness of the
capacitive coupling.
Keywords: LC oscillator, Multi-stage, Phase noise, Capacitive coupling
1. Introduction
A single-stage LC oscillator operates at a frequency
that satisfies its oscillation conditions. Under these
conditions, both the current and the voltage of the LC tank
are in phase. However, for a multi-stage coupled LC
oscillator, out-of-phase coupling current is introduced in
each stage from the adjacent stage, which changes the
operating frequency and degrades the quality factor of an
LC tank [1]. While phase noise in a multi-stage oscillator
typically depends on the quality factor of the LC tank,
phase spacing accuracy is related to the strength of the
coupling signal [2]. Unlike conventional coupling with
coupling transistors, capacitive coupling introduces a large
in-phase coupling current from the adjacent stages without
degrading the quality factor of an LC tank. Therefore,
capacitive coupling can achieve both low-phase noise and
accurate phase spacing.
2. Capacitive Coupling
Capacitive coupling can be accomplished using a ring
of capacitors, as seen in Fig. 1(a) [3-5]. The three-stage
coupled oscillator with the basic oscillator stage seen in
Fig. 1(b) accompanies both conventional coupling with
transistors (solid lines) and capacitive coupling (dashed
lines). Even though capacitive coupling alone can provide
multi-phases, coupling with coupling transistors is also
used to accurately define oscillation direction and phase
sequences. Based on the fact that Vi+ in the basic cell
ideally leads π/3 degrees to Vo+, Fig. 1(a) shows the phases
on output, and the capacitors connect the oscillator output
nodes in the order of the phases, forming a ring.
A phasor diagram of a three-stage coupled LC
oscillator with capacitive coupling is shown in Fig. 2. Each
oscillator output node contains three current components.
For example, node Vo1+ contains a regeneration current,
Iosc1, with two coupling currents: one is a coupling current
produced by coupling transistors, Ic_tr3-, and the other is a
coupling current introduced by the coupling capacitors,
Ic_cap1.
With the assumption that the voltage at Vo1+, Vo2-, and
Vo3- are Vo·cos(ωrest), Vo·cos(ωrest-φ), and Vo·cos(ωrest+φ),
respectively, the current contributed to the Vo1+ node
through the coupling capacitors, Ic_cap1, is the sum of the
two current components, Ic_cap13b and Ic_cap2b1, in Eq. (1),
and the phase of Ic_cap1 is the same as the phase of Vo1+.
ic _ cap1 = 2CcVoωres sin φ cos(ωres t )
(1)
With this large in-phase coupling current at gigahertz
operations, the total coupling current in Eq. (2), becomes a
vector sum with the coupling current through coupling
transistors, Ic_tr3-, resulting in much greater coupling
current magnitude in Fig. 2.
150
Park et al.: A Capacitively Coupled Multi-Stage LC Oscillator
(a)
Fig. 2. Phasor diagram of a three-stage LC oscillator
ring with capacitive coupling, and comparison of the
coupling current magnitude and phase differences
between one without capacitive coupling and one with
capacitive coupling.
(b)
Fig. 1. Three-stage LC oscillator with a ring of
capacitors (Fig. 1(a)), and a basic oscillator stage (Fig.
1(b)).
in Eq. (4) increases the effective quality factor of the LC
tank, resulting in lower phase noise [6].
Phase spacing error in multi-stage coupled LC
oscillators can be expressed as standard deviation, σφ, of
the phase spaces in Eq. (5), where m is the ratio of the
coupling current to the regeneration current (Ic/Iosc), and φ
is the phase difference introduced to an LC tank [2].
σω
N − 1 (1 + m cos φ )
⋅ 2Q ⋅
⋅
ωres
N
m ( m + cos φ )
2
ic1 =
(
2
ic _ tr 3− + ic _ cap12
+ 2 ic _ tr 3− ic _ cap1 cos φ
σφ =
)
1/2
(2)
An additional benefit with the large in-phase coupling
current is that the phase difference between the total
coupling current and the regeneration current becomes
smaller in Fig. 2 from the phase difference without
capacitive coupling, φcon, in Eq. (3) [2, 6] compared to that
with capacitive coupling, φcap, in Eq. (4), because the
denominator in the parentheses grows faster with the
capacitive coupling current.
⎛
−1 ⎜
φcon = cos ⎜
iosc1 + ic _ tr 3− cos φ
(
⎜ iosc12 + ic _ tr 3− 2 + 2 iosc1 ic _ tr 3− cos φ
⎝
)
1/2
⎞
⎟
⎟
⎟
⎠
⎛
⎜
iosc1 + ic _ cap1 + ic _ tr 3− cos φ
−1 ⎜
= cos
1/2
⎜⎛
2
2
⎞
⎜ ⎜ iosc1 + ic _ cap1 + ic _ tr 3− + 2 iosc1 + ic _ cap1 ic _ tr 3− cos φ ⎟
⎠
⎝⎝
(
)
As m increases with capacitive coupling in Eq. (2),
phase spacing error in terms of σφ becomes smaller
because the denominator in the last term in Eq. (5) grows
faster than the numerator, resulting in accurate phase
spacing. However, the phase difference in the voltages
across the coupling capacitors causes capacitive loading,
lowering the operating frequency and reducing the tuning
range [4].
3. Simulation
(3)
φcap
(5)
⎞
⎟
⎟
⎟
⎟
⎠
(4)
The smaller phase difference with capacitive coupling
Two three-stage coupled oscillators are designed to
operate at 4.5GHz with Taiwan Semiconductor
Manufacturing Corporation (TSMC) 0.18μm technology,
but only one oscillator has a ring of 1pF metal-insulatormetal (MIM) capacitors taking advantage of in-phase
capacitive coupling current, and the other one has
equivalent capacitive loading. The LC tank is comprised of
an 858pH spiral inductor with a quality factor of
approximately 8 at 4.5GHz and a series of varactors. With
the basic oscillator stage in Fig. 1(b), the amount of
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
151
References
(a)
(b)
Fig. 3. Comparison of phase noise with/without
capacitive coupling (Fig. 3(a)) and phase spacing error
(Fig. 3(b)).
coupling current through coupling transistors can be
controlled. With a deliberate mismatch (i.e., 50 fF extra
capacitance in one of the six output nodes), the phase noise
and the phase spacing error for different transistor
coupling current settings (expressed as a percentage of Itot
(6mA)) are plotted in Figs. 3(a) and (b), respectively. Even
though the two oscillators operate at the same frequency,
in the presence of the same mismatch, the oscillator with
capacitive coupling performs at 0.3dB less phase noise
with 20% of the total current for the coupling transistors
and substantially less phase spacing error: a 0.07 unit
interval phase spacing error improvement at the same
operating point.
4. Conclusion
Capacitive coupling in multi-stage coupled LC
oscillators introduces in-phase coupling current, improving
phase noise performance and phase spacing accuracy.
Mathematical derivation and simulation shows the
effectiveness of capacitive coupling. Capacitive coupling
can be easily extended to any number of stages and
provides an accurate and finely spaced clock system for
clock-and-data recovery and other applications.
Copyrights © 2015 The Institute of Electronics and Information Engineers
[1] B. Razavi, “RF microelectronics”, Prentice Hall,
1998.
[2] L. Romano, et al., “Multiphase LC oscillators”,
Circuits and Systems I: Regular Papers, IEEE
Transactions on, Volume: 53, Issue: 7, pp. 1579–
1588, Jul. 2006. Article (CrossRef Link)
[3] J. Park, et al., “Capacitively averaged multi-phase LC
oscillator”, Circuits and Systems, IEEE International
Symposium on, Vol. 3, pp 2651–2654, 2005. Article
(CrossRef Link)
[4] J. Park, et al., “A Low Jitter Multi-Phase PLL with
Capacitive Coupling”, Custom Integrated Circuits
Conference, IEEE, pp 753–756, 2006. Article
(CrossRef Link)
[5] L. Oliveira, et al., “Synchronization of two LCoscillators using capacitive coupling”, Circuits and
Systems, IEEE International Symposium on, pp
2322–2325, 2008. Article (CrossRef Link)
[6] J. Tang, et al., “Analysis and design of an optimally
coupled 5-GHz quadrature LC oscillator”, Solid-State
Circuits, IEEE Journal of , Volume: 37, Issue: 5, pp
657–661, 2002. Article (CrossRef Link)
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.152
152
IEIE Transactions on Smart Processing and Computing
A Capacitor-less Low Dropout Regulator for Enhanced
Power Supply Rejection
Seong Jin Yun1, Jeong Seok Kim1, Taikyeong Ted. Jeong2, and Yong Sin Kim1
1
2
School of Electrical Engineering, Korea University / Seoul, Korea {flamental, hanshin06, shonkim}@korea.ac.kr
College of Computer Science and Engineering, Seoul Women’s University / Seoul, Korea ttjeong@swu.ac.kr
* Corresponding Author: Yong Sin Kim
Received June 6, 2015; Revised June 23, 2015; Accepted June 28, 2015; Published June 30, 2015
* Regular Paper
Abstract: Various power supply noise sources in a system integrated circuit degrade the
performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator
for enhanced power supply rejection is proposed to provide good power supply rejection (PSR)
performance. The proposed scheme is implemented by an additional capacitor at a gate node of a
pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator
depends on the capacitance value at the gate node of the pass transistor, that it can be maximized,
and that it outperforms a conventional LDO regulator.
Keywords: Low dropout, Regulator, Power supply rejection, Capacitor-less
1. Introduction
Low dropout (LDO) regulators are essential for analog
circuits in mobile devices that require a clean power
supply. The power supply of a system integrated circuit
(IC) is usually stepped down by using buck converters in a
switched mode power supply (SMPS). Then, an LDO
regulator cascaded with the SMPS provides clean power to
analog circuits. With the growing trend of external
capacitor-less design of an LDO regulator, it is essential to
have a regulator integrated into a single system IC and to
maintain low cost by minimizing the chip size as well.
However, a system IC is affected by several power supply
noise sources. The output voltage ripple of the SMPS
directly affects the performance of the LDO regulator. In
addition, the transition of logic levels in high-speed digital
circuits causes supply voltage bouncing. These power
supply noises appear from a few hundred kilohertz to a
few megahertz [1].
To minimize power supply noise from these sources,
an LDO regulator needs superior power supply rejection
(PSR) performance for frequencies up to a few megahertz.
There are several techniques to achieve high PSR
performance without using an off-chip capacitor. A supply
noise shielding technique using a negative metal oxide
semiconductor (NMOS) cascode transistor was used [2].
Since the NMOS cascode transistor with its gate biased
separately acts like a source follower, it shields the entire
regulator from fluctuations in the power supply. But this
technique is not suitable for most applications because of
high dropout voltage and bad transient response. A feedforward supply-noise cancellation (FFNC) technique was
used [3]. However, as a widely used solution, this
technique is no longer available, because it is very
sensitive to input voltage and load current variation.
Moreover, supply noise is partially cancelled according to
the control voltage that determines the gain of the feedforward amplifier. Ho and Mok [4] proposed an LDO
regulator composed of a band-pass filter and summing
amplifier to enhance power supply rejection. But, its ripple
rejection accuracy is limited due to passive elements of the
filter. Moreover, the PSR enhancement in high frequency
regions was trivial. The feed-forward current injection
technique was introduced [5], which achieves significant
PSR enhancement in the 0.4-4 MHz range at the expense
of an additional complex circuit block to minimize
mismatch between the scaled transistor and the current
amplifier ratio for direct dependency of PSR performance
to the ratio.
We analyzed a new PSR enhancing scheme that
consists of an additional capacitor at the gate node of a
pass transistor. Since the additional capacitor is related to
parasitic capacitance at the gate node of the pass transistor,
frequency response of the gate-source voltage of the pass
153
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
VREF
Vgate
VIN
Mp
M5a
VOUT
M5b
Vgate
R1
VFB
M4a
CL
M4b
M1a
VREF
R2
M1b
VFB
RCM RCM
M3a
(a)
M2a
M2b
M3b
(a)
VREF
Vgate
Mp
VIN
Cvar
VOUT
M9
M11
M12
M13
R1
VFB
RC2
CD1
CL
CC2
Vgate
VOUT
R2
CC1
(b)
M6b
RC1
M8b
M7b
M6a
M7a
M8a
CD2
M10
Cvar
VREF
Vgate
Mp
(b)
Frequency
Compensator
VOUT
R1
VFB
Fig. 2. Circuit implementation of (a) error amplifier, (b)
frequency compensator [5, 6].
CL
R2
(c)
Fig. 1. Fundamental blocks of (a) the conventional LDO
regulator, (b) an LDO regulator with an additional
capacitor, (c) the proposed LDO regulator.
transistor is changed. Therefore, the PSR performance of
the LDO is changed by its additional capacitance value.
This paper is organized as follows. The design
considerations for fundamental circuit blocks are reviewed
in Section 2, and the proposed PSR enhancing scheme is
reviewed in Section 3. Simulation results and discussion of
the effect of the proposed scheme are presented in Section
4. Finally, comparisons of the proposed LDO regulator
with others follow with our conclusion in Section 5.
proposed LDO regulator includes a frequency compensator
to enhance the frequency response, as shown in Fig. 1(c).
A circuit implementation of the error amplifier is
depicted in Fig. 2(a). Differential gain of the single-ended
two-stage error amplifier with a fully differential input
stage is tuned by the common-mode resistor RCM. Highfrequency PSR affected by the error amplifier is
minimized by using a symmetrical structure. To improve
the matching between M3a and M3b and to increase the
output impedance, cascade transistors M4a and M4b are
added to the second stage of the error amplifier. The
conventional structure of a frequency compensator as
shown in Fig. 2(b) is adapted to the proposed LDO
regulator for a phase margin higher than 60°, which
compensates loop stability with a differentiator and a gain
stage that generate a frequency compensating zero [5, 6].
3. The Proposed Scheme
2. Design Considerations
Fig. 1(a) shows fundamental blocks of a conventional
LDO regulator composed of an error amplifier, a pass
transistor, and passive elements. Fig. 1(b) shows an
additional capacitor added at the gate node of the pass
transistor in order to enhance PSR performance. But the
stability of this circuit can be degraded. Therefore, the
3.1 Conventional PSR Enhancing
Scheme
Fig. 3 shows a small signal model of the conventional
LDO regulator [5]. The main factor for PSR limitation at
high frequencies of the conventional LDO regulator is the
supply voltage coupled through the gate-source and the
gate-ground parasitic capacitances of the pass transistor.
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Yun et al.: A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection
Vdd
Cgs
Vgate
RG
=rdsn||rdsp
sCgdVdd
Vdd
Mp
Cp
Vgate
(1/rdsp+sCdb)Vdd
RG
=rdsn||rdsp
Cgd
Cvar
Cp
Cgs
Mp
VOUT
sCgdVgate
RLT
VOUT
CLT=CL+Cgd+Cdb
Fig. 3. Small-signal equivalent circuit of the conventional LDO regulator [5].
The coupled gate-source voltage from the supply is
converted into current through the pass transistor. Then,
the output voltage of the LDO regulator is affected by the
supply noise, resulting in degradation of PSR performance
at high frequencies. The gate voltage as a function of
supply voltage Vdd can be approximated as
Vgate =
s (C gs + C gd )
1
+ s (C p + C gs + C gd )
RG
Vdd ≅
C gs + Cgd
C p + C gs + gd
≅ Vdd (1)
where Cp, Cgs, and Cgd represent the parasitic capacitances
of the error amplifier, of the gate-source, and the gatedrain, respectively. RG indicates output resistance of the
error amplifier. 1/RG and Cp can be ignored since RG is
large enough, and the sum of Cgs and Cgd are much bigger
than Cp. Note that the gate-source voltage Vgs(= Vdd - Vgate)
is small enough to be neglected. Thus, the fluctuation of
the supply voltage does not affect the output node. But
complex circuits are needed to implement the voltage
controlled current source, sCgdVdd, and a mismatch
problem also exists.
3.2 Proposed PSR Enhancing Scheme
The proposed PSR enhancing scheme is described as
follows. The aforementioned noise modulation of the gate
voltage can easily be removed by an additional capacitor at
the gate node of the pass transistor. Fig. 4 shows the smallsignal equivalent circuit with additional capacitor Cvar
connected between the gate node of the pass transistor and
the ground. The gate-source voltage of the pass transistor
can be neglected by choosing the optimum value of Cvar,
which leads to enhanced PSR at high frequencies.
The gate voltage as a function of supply voltage Vdd of
the proposed LDO regulator can be approximated as
Vgate =
≅
sC gs
1
+ s (C p + Cgs + Cgd ) + sCvar
RG
sCgs
s (C p + Cgs + Cgd + Cvar )
Vdd
Vdd = Vdd
(1/rdsp+sCdb)Vdd
Cgd
(2)
sCgdVgate
RLT
CLT=CL+Cgd+Cdb
Fig. 4. Small-signal equivalent circuit of the proposed
LDO regulator.
If the capacitance value of Cvar is adjusted to –(Cp+Cgd),
Cp and Cgd in the denominator cancel out.
4. Simulation Result
The proposed LDO regulator is simulated with 0.18 μm
complementary metal-oxide semiconductor (CMOS)
technology. Regulated output voltage of the LDO regulator
is 1.6 V for an input voltage ranging from 1.8 V to 2.6 V,
and its minimum dropout voltage is 200 mV. The
capacitance of the load is 20 pF, and maximum load
current is 50 mA. Four 1.3 pF on-chip capacitors are used
for both frequency compensation and fast slew. The sum
of on-chip capacitor values is 25.2 pF, which includes the
20 pF load capacitor. Fig. 5(a) depicts the simulated PSR
with different values of Cvar at a load current of 50 mA.
The PSR performance of the proposed LDO regulator with
fine values of Cvar is shown in Fig. 5(b), which indicates
the best performance of PSR at a Cvar of -7 pF. As a result,
in Fig. 5(c), the proposed LDO regulator achieves higher
PSR than the LDO regulator without Cvar by over 20 dB in
a 0.9 MHz to 6 MHz range. In particular, it is 25 dB higher
at a 2 MHz to 5 MHz range. There is remarkable PSR
improvement in the tens of megahertz region that equals
the switching frequency of the DC-DC converter and
digital circuits. Fig. 6 shows the simulated load step
transient response from 0 to 50 mA regulated under 100 ns
for the rising and the falling time. The maximum
overshoot and undershoot are 88 mV and 164 mV,
respectively. The settling time is obtained in less than 1.5
μs. The simulated load regulation is 0.14 mV/mA. The
simulated line regulation for an input variation from 1.8 V
to 2.6 V is regulated under 500 ns for rising and falling
times, as shown in Fig. 7. The maximum variation of
output voltage is 3 mV for a load current of 50 mA, and
the simulated line regulation is 1.45 mV/V.
Performance comparisons between the proposed LDO
regulator and other capacitor-less LDO regulators is listed
in Table 1. Park et al. [5] achieved the best PSR
performance. However, a large total on-chip capacitor, 128
pF, is needed, which occupies 45% of its active area. The
proposed LDO regulator exhibits the second-best PSR
performance among the others. Since the least total
capacitance, 32.2 pF, is used, a smaller area can be
achieved, compared to the Park et al. scheme [5].
155
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
ILOAD=50mA
100ns
Current(A)
100ns
ILOAD=0mA
88mV
Voltage(V)
VOUT
(a)
164mV
Time(s)
Fig. 6. Simulated load transient response for a load
current step of 50Ma.
VDD
500ns
500ns
Voltage(V)
(b)
VOUT
3mV
Time(s)
Fig. 7. Simulated line transient response for an input
variation of 1.8 to 2.6V.
(c)
Fig. 5. Simulated PSR (a) with coarse values of Cvar, (b)
with fine values of Cvar, (c) with and without Cvar.
Table 1. Performance Comparison.
[2], 2007
[3], 2011
[4], 2012
[5], 2014
[6], 2007
this work
Technology (μm)
CMOS 0.6
CMOS 0.18
CMOS 0.13
CMOS 0.18
CMOS 0.35
CMOS 0.18
Max. load (mA)
5
25
50
50
50
50
VOUT (V)
1.2
1.5
1
1.6
2.8
1.6
VDROP (mV)
600
300
200
200
200
200
80
IQ (μA)
80
300
37.32
80
65
Load capacitor (pF)
10
25
20
100
100
20
Total on-chip capacitor (pF)
58
125
41
128
123
32.2
@1MHz
-40
-40
-40
-70
-36
-52
@10MHz
-30
-22
-15
-36
-5
-29
PSR
(dB)
ΔVOUT (mV)
192
N/A
56
75
90
103
FOM* (ns)
0.006144
N/A
0.000017
0.000264
0.000234
0.000066
*FOM=(COUT x ΔVOUT x IQ)/(IMAX.LOAD)2
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Yun et al.: A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection
5. Conclusion
A capacitor-less LDO regulator for enhanced PSR is
proposed at the expense of an additional capacitor at the
gate node of a pass transistor. The proposed LDO regulator
is simulated with 0.18 μm CMOS technology, and
simulation results show the optimum value of the capacitor
gives a PSR better than -40 dB up to 5 MHz with a 50 mA
load current. Compared to a conventional LDO regulator,
regulator is 25.2 pF, including the load capacitor of 20 pF.
the proposed LDO regulator improves PSR by more
than 20 dB in a frequency range of 0.9 MHz to 6 MHz.
The total on-chip capacitor required for the proposed LDO
Because of both the high PSR performance at higher
frequencies and the smaller on-chip capacitor, the
proposed LDO regulator can be widely used for low-cost
applications requiring high power supply rejection.
Seong Jin Yun received his BSc and
MSc in Electrical Engineering from
Kangwon National University (KNU),
Korea, in 2010 and 2012, respectively.
Currently, he is working toward a PhD
at Korea University, Seoul, Korea.
From December 2011 to August 2013,
he worked as a Research Engineer at
Dongbu Hitek Inc., Seoul, Korea, designing digital circuits
and systems for a large display driver IC (LDDI). His
research interests include low-power energy harvesters,
low dropout (LDO) voltage regulators for system-on-chip
(SoC) applications, and power management IC design. He
was a recipient of the 2010 KEC Analog Circuit Design
Contest. He also won the IP Design Contest of Dongbu
Hitek Inc. in 2011.
Acknowledgement
This work was supported by a Human Resources
Development program grant (No. 20124030200120) of the
Korea Institute of Energy Technology Evaluation and
Planning (KETEP) funded by the Korea government’s
Ministry of Trade, Industry and Energy. This work is also
supported by the Korea Sanhak Foundation.
References
[1] M. D. Mulligan, B. Broach, and T. H. Lee, “A 3MHz
low-voltage buck converter with improved light load
efficiency,” in IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, pp. 528-529, Feb. 2007.
[2] V. Gupta and G. A. Rincon-Mora, “A 5mA 0.6μm
CMOS Miller-compensated LDO regulator with 27dB worst-case power-supply rejection using 60pF
of on-chip capacitance,” in IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, pp. 520–521, Feb.
2007.
[3] B. Yang, B. Drost, S. Rao, and P. K. Hanumolu, “A
high-PSR LDO using a feedforward supply-noise
cancellation technique,” in Proc. IEEE Custom
Integrated Circuits Conf. pp. 1-4, Sep. 2011.
[4] E. N. Y. Ho and P. K. T. Mok, “Wide-loading-range
fully integrated LDR with a power-supply ripple
injection filte,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, Vol. 59, No. 6, pp. 356–360, Jun. 2012.
[5] C. J. Park, M. Onabajo, and Silva-Martinez,
“External capacitor-less low drop-out regulator with
25dB superior power supply rejection in the 0.4-4
MHz range,” IEEE J. Solid-State Circuits, Vol. 49,
No. 2, pp. 486–501, Feb. 2014.
[6] R. J. Milliken, J. Silva-Martinez, and E. Sanchezsinencio, “Full on-chip CMOS low-dropout voltage
regulator,” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 51, no. 6, pp. 1879–1890, Sep. 2007.
Jeong Seok Kim received his BSc in
Electrical Engineering from Korea
University, Korea, in 2010. He is
currently working toward a PhD in
Electrical Engineering at Korea University, Seoul, Korea. His research interests
include gesture recognition sensors
(GRSs), ambient light sensors (ALSs),
and proximity sensors (PSs) for mobile devices, digital
speaker drivers for audio applications, and high-speed
intra-panel interfaces.
Taikyeong Ted. Jeong received a PhD
from the Department of Electrical and
Computer Engineering at the University of Texas at Austin in 2004, and
was a recipient of research grants from
NASA, working on high-performance
systems for next-generation systems,
and energy-harvesting mobile systems.
He is currently working as an Assistant Professor in the
Department of Computer Science and Engineering at Seoul
Women’s University, Korea. His research interests include
IoT, mobile systems and power management design.
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Yong Sin Kim received a BSc and
MSc in electronics engineering from
Korea University in 1999 and 2003,
respectively, and a PhD in electrical
engineering from the University of
California at Santa Cruz, USA, in 2008.
From 2008 to 2012, he worked at the
University of California Advanced
Solar Technologies Institute (UC Solar), in Merced, where
he researched maximizing power harvesting in distributed
photovoltaic systems. From 2012 to 2014, he was with the
School of Electrical and Electronics Engineering, ChungAng University, Korea, where he was involved in
developing sensors for a human–machine interface. In
2014, he joined the faculty of the School of Electrical
Engineering, Korea University, Korea. His research
interests are integration of circuits and systems for energy
harvesting, human–machine interfaces, sensor applications,
power management ICs, and wireless sensor nodes.
Copyrights © 2015 The Institute of Electronics and Information Engineers
157
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.158
158
IEIE Transactions on Smart Processing and Computing
Low Phase Noise CMOS VCO with Hybrid Inductor
Seonghan Ryu
Department of Information and Communication Engineering, Hannam University / Daejeon, South Korea ilikeit@hnu.kr
Received May 31, 2015; Accepted June 19, 2015; Published June 30, 2015
* Regular Paper
Abstract: A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multistandard RF Transceivers is presented. For both wide tunability and low phase noise characteristics,
Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is
proposed. This approach reduces inductance variation and presents high quality factor without
custom-designed single-turn inductor occupying large area, which improves phase noise and tuning
range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS
technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at
400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider.
The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from
1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.
Keywords: Low phase noise, CMOS VCO, Hybrid inductor, Wide tuning range
1. Introduction
Recently, miniaturized and cost-effective RF
transceivers are highly demanded by the worldwide
wireless communication market for global mobility and
wide coverage of the proposed communication service .
Therefore, designing an integrated VCO for multistandard/multi-band system-on chip(SOC) has attracted
considerable interest. 3G/4G communication service
requires miniaturized and cost-effective device solution,
which can cover different frequency bands. CMOS has
become the most favored technology meeting demands
such as high data rates, global mobility and wide
communication service coverage, because structural
complexity and operating speed of silicon integrated
circuits are continuously increased by scaling down of
CMOS technology. Among the efforts for highly
integrated
wireless
CMOS
transceivers,
the
implementation of building blocks with both wide
frequency operability and signal purity is crucial. And
single low phase noise multi-band/multi-mode CMOS
VCO design is still remain as challenging work [1, 2]. The
multiband VCO with wide frequency tunability needs large
capacitor banks and varactor diodes, large capacitor banks
result in area occupation issue and high VCO gain of
varactor results in phase noise degradation issue. Though
these problems can be solved by allowing higher power
consumption, this is not desirable for total performance of
the SOC. In addition, the larger the value of capacitance,
the lower the inductance value, which normally results in
low quality factor inductor. Though the custom-designed
single turn inductor could have higher quality factor, it
should have wide metal strip and occupies larger area than
a conventional inductor which is provided by the process
design kit(PDK). The silicon area issue has become
severer these days since MIMO is basically required for
much better uplink/downlink capability. For the MIMO
communication system, multi RF transceiver architecture
should be integrated in one SOC. Therefore, the size of
wideband and low phase noise VCO is the most crucial
issue for feasible wireless communication SOC. The
bondwire inductor occupies far less area than customdesigned inductor and could be a proper alternative for
good quality factor, however it suffers from inductance
variation issues which is generated during bonding process
and package fabrication.
This paper describes the design of a low phase noise
CMOS VCO with wide tunability using hybrid inductor
which is composed of bondwire inductor and planar spiral
inductor in the same area and is less vulnerable to variation.
With a 1.3V power supply, this VCO consumes a 7.5 mA
bias current at VCO core and shows frequency tunability
from 3.15 to 4.18GHz with low phase noise characteristics.
GSM/EDGE and WCDMA bands can be covered by the
proposed VCO.
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IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Fig. 2. Hybrid Inductor Structure.
Fig. 1. Two types of CMOS VCO Structures.
2. Hybrid Inductor Structure
A complementary type and an NMOS-only type are
mostly favored structure for differential CMOS VCO. Two
types of VCO structures are depicted in Fig. 1.
The well-known phase noise model for an oscillator is
Leeson’s proportionality [3].
(1)
where the phase noise is given by kT/C noise that is shaped
in frequency domain by LC tank and normalized to the
power in the tank. This expression reveals the dependency
of the phase noise upon the signal amplitude Vo. For the
complementary type VCO, as the bias current increases,
signal amplitude is limited by VDD in the voltage limited
regime, while the NMOS-only type VCO enables higher
voltage swing above VDD limit. Therefore, the phase noise
of the complementary type at each offset frequency may
become worse than that of the NMOS-only type as the bias
current increases [4]. The complementary type could
maintain better phase noise performance for relatively
small bias current, but this bias current is not enough to
satisfy the requirements for multi-band/multi-standard
operation. In addition, considering various lossy
components of the real Si circuits, enough phase noise
margin is necessary. Accordingly, the NMOS-only type is
adopted. This topology has just two MOSFETs for active
gm-switching cell, which minimizes parasitics and is really
helpful for maximizing frequency tuning range. After
selecting optimum FET size considering power
consumption and phase noise, the LC tank which is
composed of a switched capacitor bank and inductor
decide the performance of the multi-band VCO. On the
whole, the inductor has lower quality factor than the
capacitor bank.
Therefore, a high Q factor inductor is cardinal for low
phase noise CMOS VCO design. However, the planar
spiral inductor model which is provided by PDK has low
Q factor value of around 10. Though thick metal option
could help for enhancement of Q factor, it is not enough
and is normally not provided for the wireless
communication SOCs due to the cost issues. A customdesigned planar spiral inductor which has higher Q factor
than PDK model is another alternative. A relatively large
size single-turn inductor shows Q of around 15 ~ 20.
However, very wide metal strip width and out-diameter of
around 400 ~ 500 µm is required for high Q inductor. The
inductor occupies large area, which is not desirable from
the point of view of high density integration.
The bondwire inductor occupies far less area than
custom-designed inductor and has a quite good quality
factor of above 25, therefore it could be a proper
alternative. However it suffers from inductance value
variation which is generated during bonding process and
package fabrication.
To address these issues, Hybrid inductor which is
composed of both bondwire inductor and planar spiral
inductor is proposed for both wide tunability and low
phase noise characteristics. Two types of inductors are
designed to be placed in the same area and are connected
in parallel as depicted in Fig. 2. This approach reduces
inductance variation and presents high quality factor
without custom-designed single-turn inductor occupying
large area, which improves phase noise and tuning range
characteristics without additional area loss.
Considering the tuning range and Q factor, inductance
value of about 1nH is often selected for 2 ~ 6GHz
operation. In this research, 1nH Hybrid inductor is
composed of a 2nH bondwire inductor and a 2nH
conventional spiral inductor. The quality factor of each
2nH inductor is depicted in Fig. 3. The bondwire inductor
shows good quality factor above 30 in the frequency range
of interest, however conventional spiral inductor which is
provided in PDK has low Q of around 12 at 4GHz.
The spiral inductor has peak Q at high frequency above
7GHz and peak Q of the bondwire inductor is at around
3GHz. With parallel connection of these two types of
inductors, the hybrid inductor has Q factor value of around
20 and inductance value of about 1nH at 4GHz as shown
in Fig. 4. The shunted bondwire inductor and conventional
planar spiral inductor are simulated using EM simulator.
The inductance of bondwire is linearly increased with
the bondwire length and can be modified with changing
the distance between two bondpads and bondwire height.
In general, bondwire inductor has 3-D structure and other
Ryu: Low Phase Noise CMOS VCO with Hybrid Inductor
160
WBand9Tx (X2)
WBand8Tx (X4)
WBand6Tx (X4)
WBand5Tx (X4)
WBand4Tx (X2)
WBand3Tx (X2)
WBand2Tx (X2)
WBand1Tx (X2)
PCS 1900Rx (X2)
DCS 1800Rx (X2)
GSM 900Rx (X4)
GSM 850 Rx (X4)
PCS 1900Tx (X2)
DCS 1800Tx (X2)
GSM 900Tx (X4)
GSM 850Tx (X4)
3200
3300
3400
3500
3600
3700
3800
3900
4000
Carrier Frequency (MHz)
Fig. 3. Quality factor of each inductor structure.
Fig. 5. Frequency planning for the carrier generation of
quad-band GSM/EDGE and WCDMA standards.
Fig. 4. Quality factor and Inductance for Hybrid Inductor.
Fig. 6. Proposed VCO structure.
circuit blocks such as dividers, buffers and bias blocks
could be placed under bondwire inductor. In this research,
a conventional planar spiral inductor and periphery
circuitry are placed under bondwire inductor.
In the simple prescaler only LO chain, even though
carrier frequency doubling is needed to generate
quadrature I/Q signal, side effects of other structures such
as self-mixing, DC-offset and frequency pushing/pulling
can be minimized. Fig. 5 depicts a frequency planning for
the carrier generation of quad-band GSM/EDGE and
WCDMA standards. WCDMA Rx band is excluded in this
frequency planning since WCDMA Tx and Rx are
simultaneously active for operation. The VCO with a
frequency tuning range of 684MHz, which is from
3296MHz (GSM850Tx × 4) to 3980MHz (PCS1900Rx ×
2), is needed for prescaler-only scheme.
In the design of a VCO for wide frequency range
standard, it is very difficult to satisfy both wide tunability
and phase noise requirement with same LC tank. Proper
design of a switched capacitor bank and varactor is
required to avoid phase noise degradation and to acquire
reasonable KVCO, the vco gain, for stable PLL operation.
The proposed VCO structure is shown in Fig. 6.
Accumulation-type MOS varactor is used for fine tuning.
A binary-weighted 8-bit switched capacitor bank with
enough frequency margin is used for coarse tuning to
overcome frequency shift due to PVT variations.
3. The VCO Circuit Design
The mobile integrated system for quad-band GSM/
EDGE and WCDMA requires the VCO having a very wide
tuning range and very low phase noise at both close in
offset and higher offset from the carrier frequency. Since
complex carrier generation structures using a harmonic
mixer have various non-ideal effects including harmonics
coupling, a simple frequency planning based on only
divide-by-two prescaler is favored these days. This simple
LO chain structure is the optimum solution to minimize the
cost in terms of system complexity, power consumption
and area in comparison with other solutions such as
quadrature VCO (QVCO) and a polyphase filter. QVCO
requires doubling both area and power consumption. The
polyphase filter has similar defects to lose dependency on
the process variation and mismatches [5].
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IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Table 1. VCO performance summary and comparison.
VCO
Tech.
Freq.
[GHz]
Power
[mW]
P/N
[dBc/Hz]
[6]
0.35um
Bi-CMOS
1.91
10
[7]
0.35um
Bi-CMOS
5.6
13.5
-117
@1MHz
-180.7
[8]
0.13um
CMOS
3.0-5.6
2
-114.5
@1MHz
-186.5
[9]
0.35um
CMOS
2.19
12.6
-139
@3 MHz
-185.3
This
Work
0.13um
CMOS
3.15-4.18
9.75
-142
@3 MHz
-181.7
FOM
-121
-181.1
@600KHz
Fig. 7. Complete layout of the proposed CMOS VCO.
carrier, respectively. The measured frequency tuning range
and phase noise performances satisfy Quad-band GSM/
EDGE and WCDMA standard requirements. Table 1.
shows the summary of the measurement results compared
to those of other low phase noise VCOs.
A normalized figure of merit (FOM) has been defined
[10] to compare the VCO performance with other VCOs as
(2)
Fig. 8. Measured phase noise of the proposed VCO at
900MHz carrier frequency.
As for the size issue, this VCO structure can save large
silicon area by placing two inductors and periphery
circuitry in the same position. In the layout of LC VCOs,
inductor commonly occupies almost total silicon area. And
for minimizing power consumption, the VCO bias current
is varied between each frequency band by controlling the
3-bit binary weighted bias resistors. This programmability
allows the trade-off between power consumption and
phase noise, which is necessary for multi-band/multistandard VCOs.
4. Measurement Results
Considering these multi-band low phase noise VCO
design issues, the VCO is designed with the proposed
hybrid inductor in 0.13 um CMOS technology, Fig. 7
shows the complete layout of the VCO. The chip size is
0.7 × 0.6 mm2.
The VCO is tunable between 3.15GHz and 4.18GHz.
The resulting range is 28% of the mid frequency. The
VCO operates from 1.3V supply and biases at 7.5 mA. Fig.
8 plots the measured phase noise for the test VCO with the
carrier frequency of 900MHz after 1/4 divider.
The VCO achieves -121dBc/Hz and -142dBc/Hz at
400KHz and 3MHz offset frequencies from the 900MHz
where L(Δω) is the total single-sideband phase-noise
spectral density at an offset frequency Δω, PDC is total
VCO power consumption, and ω0 is the frequency of
oscillation. The calculated FOM of this VCO is about 181.7 dBc/Hz at 3MHz offset. Considering the wide tuning
range of 28%, this FOM is quite comparable to the
previously published results.
5. Conclusion
In this paper, a low phase noise CMOS VCO with
Hybrid inductor for multi-band/multi-standard RF
Transceivers is presented. The proposed VCO has wide
frequency tunability through hybrid inductor structure,
which is composed of bondwire inductor and spiral
inductor. These two inductors are placed in the same
position, which saves large silicon area. This approach
reduces total inductance variation and presents high quality
factor without custom-designed single-turn inductor
occupying large area.
The design has been achieved with 0.13um CMOS
process. An NMOS-only structure, high Q bond wire
inductor and conventional planar spiral inductor are
adopted for enough frequency tining range, good phase
noise characteristics, and chip area efficiency. In addition,
programmable 3-bit bias resistors are used for a trade-off
between phase noise and power consumption. Proposed
hybrid inductor structure enables wide frequency tunability
and low phase noise characteristics. The measured results
show the tuning range of about 28%(3.15 to 4.18GHz) and
the phase noise of -121dBc/Hz at 400KHz offset and -
162
142dBc/Hz at 3MHz offset from a 900MHz carrier after
1/4 divider. The VCO consumes 7.5mA from 1.3V supply
and meets the requirements for GSM/EDGE and WCDMA
standard. These values confirm that a good tradeoff among
phase noise, wide tunability and silicon area efficiency is
achieved by the proposed CMOS VCO with hybrid
inductor.
Ryu: Low Phase Noise CMOS VCO with Hybrid Inductor
Proc. IEEE Custom Integrated Circuit Conf., San
Diego, CA, pp. 197–200, May. 2001. Article
(CrossRef Link)
[10] A. Wagemans, “A 3.5 mW 2.5 GHz diversity
receiver and a 1.2 mW 3.6 GHz VCO in silicon-onanything,” IEEE Int. Solid-State Circuits Conf. Tech.
Dig., pp. 250-251, Feb. 1998. Article (CrossRef
Link)
Acknowledgement
This research was supported by Basic Science
Research Program through the National Research
Foundation of Korea(NRF) funded by the Ministry of
Education, Science and Technology(No. 2011-0014304).
This work was supported by IC Design Education
Center(IDEC).
References
[1] S. Ryu, Y. Chung, H. Kim, J. Choi, and B. Kim,
“Phase noise optimization of CMOS VCO through
harmonic tuning”, in IEEE Radio Freq. Integr.
Circuits Symp., Long Beach, CA. pp. 403–406, Jun.
2005. Article (CrossRef Link)
[2] K. Lee, H. Yu, H. Ahn, H. Oh, S. Ryu, D. Keum and
B. Park, “A0.13-um CMOS Σ-Δ Frequency
Synthesizer with an Area Optimizing LPF, Fast AFC
Time, and a Wideband VCO for WCDMA/GSM/
GPRS/ EDGE Applications”, in IEEE Radio Freq.
Integr. Circuits Symp., Atlanta, GA. pp. 299–302, Jun.
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[3] D. B. Leeson, “A Simple Model of Feedback
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[4] S. Ryu, “Multi-standard carrier generator with CMOS
logic divider,” in IEEE Int. Midwest Symp on Circuit
and Systems., Cancun. pp. 1059–1062, Aug. 2009.
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[5] A. Koukab, Y. Lei, M. J. Declercq, “A GSMGPRS/UMTS FDD-TDD/WLAN 802.11a-b-g MultiStandard Carrier Generation System”, IEEE J. SolidState Circuits, vol. 41, pp. 1513-1521, July. 2006.
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[6] D. Ham and A. Hajimiri, “Concepts and methods in
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[7] G. De Astis, D. Cordeu, J. Paillot, and L. Dascalescu,
“A 5-GHz fully integrated full pMOS Low-phasenoise LC VCO”, IEEE J. Solid-State Circuits, vol. 40,
pp. 2087–2091, Oct. 2005. Article (CrossRef Link)
[8] N. Fong, “Design of wideband CMOS VCO for
multiband wireless LAN applications”, IEEE J.
Solid-State Circuits, vol. 38, pp. 1333–1342, Aug.
2003. Article (CrossRef Link)
[9] P. Adreanj and H. Sjoland, “A 2.2 GHz CMOS VCO
with inductive degeneration noise suppression”, in
Copyrights © 2015 The Institute of Electronics and Information Engineers
Seonghan Ryu received the B.S.
degree in electronics engineering from
Kyungpook National University, Daegu,
Korea, in 1998, and the M.S. and Ph.D.
degree in electronic and electrical
engineering from Pohang University of
Science and Technology(POSTECH),
Pohang, Korea, in 2000 and 2005,
respectively. In 2002, he was a visiting researcher of
electrical engineering Dept. with the California Institute of
Technology(CALTECH), Pasadena, U.S. And from 2005
to 2007, he was with Samsung Electronics, Yongin, Korea.
From 2007 to 2008, he was with Defense Agency for
Technology and Quality(DTaQ), Seoul, Korea. Since 2008,
he has been with the Department of Information and
Communication Engineering, Hannam University,
Daejeon, Korea, where he is now an associate professor.
From 2013 to 2014, he was a visiting scholar of electrical
and computer engineering Dept. with the Georgia Institute
of Technology(GeorgiaTech), Atlanta, U.S. His research
interests include multi-mode/multi-standard RF CMOS
transceiver design for wireless communication, RF system
architectures, millimeter-wave circuits and Bio-inspired
microsystems with CMOS technologies.
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.163
163
IEIE Transactions on Smart Processing and Computing
On Reducing False Positives of a Bloom Filter in
Trie-Based Algorithms
Ju Hyoung Mun and Hyesook Lim
Dept. of Electronics Engineering, Ewha Womans University / Seoul, Korea {jhmun@ewhain.net, hlim@ewha.ac.kr}
* Corresponding Author: Hyesook Lim
Received March 26, 2015; Accepted April 17, 2015; Published June 30, 2015
* Regular Paper
* Extended from a Conference: The abstract version of this paper were presented at the ACM ANCS in October 2014. This
present paper has been accepted by the editorial board through the regular reviewing process that confirms the original
contribution.
Abstract: Many IP address lookup approaches employ Bloom filters to obtain a high-speed search
performance. Especially, it has been recently studied that the search performance of trie-based
algorithms can be significantly improved by adding Bloom filters. In such algorithms, the number
of trie accesses can be greatly reduced because Bloom filters can determine whether a node exists
in a trie without actually accessing the trie. Bloom filters do not have false negatives but have false
positives. False positives can lead to unnecessary trie accesses. The false positive rate must thus be
reduced to enhance the performance of lookup algorithms applying Bloom filters. One important
characteristic of trie-based algorithms is that all the ancestors of a node are also stored. The
proposed algorithm utilizes this characteristic in reducing the false positive rate of a Bloom filter
without increasing the size of the memory for the Bloom filter. When a Bloom filter produces a
positive result for a node of a trie, we propose to check whether the ancestors of the node are also
positives. Because Bloom filters have no false negatives, the negatives of any of the ancestors mean
that the positive of the node is false. In other words, we propose to use more Bloom filter queries to
reduce the false positive rate of a Bloom filter in trie-based algorithms. Simulation results show that
querying one ancestor of a node can reduce the false positive rate by up to 67% with exactly the
same architecture and the same memory requirement. The proposed approach can be applied to
other trie-based algorithms employing Bloom filters.
Keywords: IP lookup, Bloom filter, Binary search on levels
1. Introduction
Classless inter-domain routing (CIDR) architecture
makes Internet protocol (IP) address lookup algorithms
perform a task of finding the longest prefix matching for a
given input IP address. Finding the longest matching prefix
is much more complex than finding an exact match, and
this should be performed at line-speed for every incoming
packet [1]. As the Internet grows, the size of routing tables
is also growing rapidly. It is an important challenge in
designing Internet routers to develop efficient IP address
lookup algorithms to work on large routing tables.
Bloom filters have been actively employed in various
applications due to their compactness and simplicity [3].
Many IP address lookup algorithms employ Bloom filters
[4, 5]. Especially adding Bloom filters to trie-based
architectures has been recently proposed [5]. Reducing the
false positive rate of Bloom filters is a good challenge to
enhance the performance of these approaches.
We focus that every node in a trie is stored in triebased algorithms [2]. This means that all the ancestor
nodes of a node are stored in trie-based algorithms. By
using this characteristic, we propose a novel algorithm that
significantly reduces the false positives of a Bloom filter
when checking for node existence without increasing the
memory requirement of the Bloom filter. We verified the
proposed approach for the architectures of the binary
search on levels with a Bloom filter.
164
Mun et al.: On Reducing False Positives of a Bloom Filter in Trie-Based Algorithms
The rest of this paper is organized as follows. Section 2
briefly introduces related works. The proposed algorithm
is explained in Section 3. The performance evaluation
results using actual routing tables are shown in Section 4.
This paper is concluded in Section 5.
2. Related Work
2.1 Bloom Filters
A Bloom filter provides a simple but highly spaceefficient way of identifying the membership of a set. A
Bloom filter is composed of an array of m bits, which
contains the summary of members included in a set. For a
given set S = { x1 , x2 , ", xn } , the programming procedure
of a Bloom filter is as follows. First, every bit in the
Bloom filter is initialized to zero. The k hash functions
hi ( x ) for 1 ≤ i ≤ k are required to program the Bloom
filter. Hash indices obtained from these hash functions
should be in the range of 0, ", m − 1 . In programming an
element x j for 1 ≤ j ≤ n into a Bloom filter, the k bits
indicated by k hash indices obtained for x j are set to one.
This programming procedure is repeated for every element
included in set S .
The query procedure to check the membership of a
given input also uses the same k hash functions. For an
input y , the Bloom filter bits pointed by the indices
acquired from k hash functions hi ( y ) for 1 ≤ i ≤ k are
checked. If all these bits are set, y is considered a member
of set S . If any of these bits is zero, y is absolutely not a
member of set S . Bloom filters do not have false
negatives but have false positives. However, the false
positive rate can be properly controlled by increasing the
size of the Bloom filter and the number of hash functions
accordingly. For n elements, the false positive rate p f of
an m -bit Bloom filter can be calculated as follows [3].
kn ⎫
k
kn
⎛
−
⎜1 − e m
⎧⎪ ⎛
1⎞ ⎪
Pf = ⎨1 − ⎜ 1 − ⎟ ⎬ ≈
⎜
⎩⎪ ⎝ m ⎠ ⎪⎭
⎝
⎞
⎟
⎟
⎠
k
(1)
The optimal number of hash functions for an m -bit
Bloom filter of n elements can be calculated as follows.
kopt =
m
ln 2
n
(2)
2.2 Binary Trie
A binary trie is a tree-based data structure which stores
prefix information in a node of the trie [2]. The routing
information of a prefix of length l is located in a node at
level l of the trie, and the prefix value determines the path
from the root node to the node. Fig. 1 shows an example of
a trie of 7 prefixes: 000*, 010*, 1*, 1101*, 110101* 111*,
Fig. 1. A binary trie [2].
and 11111*. Each prefix is allocated in the trie according
to its value.
Searching the routing information corresponding to a
given input is linearly performed by examining each
address bit at a time along the trie, starting from the root
node. Because IP address lookup problem is to find out the
longest matching prefix, the search is finished when there
is no edge to follow. For example, when an input IP
address of 110111 comes, starting from the root node the
search goes to the right node because the first bit of the
input IP address is 1. The right node of the root is a prefix
node, and hence the routing information of P2 is
remembered. The search continues to lower levels.
Because the second bit of the input IP address is 1, the
search goes to the right, and so on. At level 4, a matching
prefix node, P4 , is remembered, and there is no branch to
follow. Therefore the routing information for P4 is
returned. The number of memory accesses for an IP
address lookup can be 32 for IPv4 in the worst-case
scenario [1]. In order to reduce the number of memory
accesses, adding a Bloom filter to trie-based architectures
has been studied [5].
2.3 Algorithms Based on Binary Search
on Trie Levels
To improve the search performance of the binary trie,
binary search on trie levels has been introduced by
Waldvogel et al. The Waldvogel’s binary search on levels
(WBSL) performs a binary search on levels of a trie. Each
level of the trie is stored in a hash table. The existence of a
node at each level leads a search to a longer level. When
there is no matching prefix in the longer level, backtracking should occur. To prevent back-tracking, a marker
and the best matching prefix (BMP) information should be
pre-computed in every internal node [6]. Fig. 2 shows the
WBSL trie, and the order of binary search on levels is
described on the right side of the figure. The figure also
shows the pre-computed markers and BMPs. Levels 1, 3, 4,
5, and 6 have prefixes, and the middle of these levels is 3.
Hence, level 3 is searched first. If a marker node is
encountered, the BMP is remembered and the search goes
to a longer level. Otherwise, if there is no matching node,
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
165
Fig. 2. Waldvogel’s binary search on levels [2].
Fig. 3. Binary search on levels in a leaf-pushed trie (LBSL) [2].
the search proceeds to a shorter level. The search ends at
the last level of access. For the same example of the input
IP address 110111, the search encounters marker node 110
at level 3. Hence the search continues at level 5, and no
matching node is found. Then the search goes to level 4
and encounters a prefix, P4 . There are no longer levels to
be searched, so the search procedure is finished by
returning the routing information of P4 .
Binary search on levels in a leaf-pushing trie (LBSL)
has been proposed to remove the requirement for precomputation of the markers and the best matching prefixes
[7]. Leaf-pushing relocates every internal prefix to leaf
nodes. Hence, an internal node guarantees that there is no
prefix node at shorter levels. Therefore, the precomputation is no longer required. Leaf-pushing removes
the nesting relationship between prefixes. Hence, when a
matching prefix node is found, the search can be finished
immediately. Fig. 3 shows a trie which is the leaf-pushed
version of the trie shown in Fig. 1. As shown in the figure,
each internal node prefix is relocated to a leaf in the leafpushed trie. Therefore, the search procedure can be
finished when a matching prefix is found. The order of
binary search on levels is described in the right side of Fig.
3. In accessing a level, if a matching prefix is encountered,
the search is immediately terminated. Otherwise, if a
matching internal node is encountered, the search goes to a
longer level. Otherwise, if there is no matching node, the
search proceeds to a shorter level. For the same example of
the input IP address 110111, the search encounters an
internal node 110 at level 3. Hence, the search continues at
level 5 and encounters a prefix, P4 . The search
immediately terminates by returning the routing
information for P4 .
To reduce the number of hash accesses, adding a
Bloom filter to these BSL-based algorithms was proposed,
and abbreviated as WBSL-BF and LBSL-BF [5]. In these
algorithms, Bloom filters determine the existence of a node.
Since Bloom filters do not have false negatives, the search
can proceed to a shorter level without a trie access when
the Bloom filter produces a negative for the query of a
node.
3. The Proposed Algorithm
It is well known that the size of a Bloom filter and
accordingly the number of hash indices should be
increased in order to reduce the false positive rate. In this
paper, we suggest a different way of reducing the false
positive rate. Our proposed method is to use more queries
by utilizing a characteristic of a trie: a node cannot exist
without ancestor nodes. In performing the binary search on
levels in a trie, every node at valid levels is stored. For the
example trie in Fig. 1, every node at levels 1, 3, 4, 5, and 6
166
Mun et al.: On Reducing False Positives of a Bloom Filter in Trie-Based Algorithms
positive rate of our proposed algorithm is p*f = p f L × p f A ,
Search (dstIP) {
min = minLevel; max = maxLevel;
while (min ≤ max) {
next = (min+max)/2;
qBF0 = queryBF(dstIP, next);
if (qBF0 is positive) {
qBF1 = queryBF(dstIP, next-1);
if (qBF1 is positive) {
node = accessHash(dstIP, next);
if (node == prefix node)
return node.info;
else if (node == internal node)
min = next + 1;
else /* false positive */
max = next - 1;
}
else /* when qBF1 is negative */
max = next - 1;
}
else /* when qBF0 is negative */
max = next - 1;
}
}
where p f L is the false positive of the current level and
p f A is the false positive rate of the ancestor level.
Building procedure for the proposed algorithm is
exactly the same as for WBSL-BF or LBSL-BF. The
search procedure for the proposed algorithm with LBSLBF is described in the pseudo-code in Fig. 4. The search
procedure for WBSL-BF is not presented because of the
similarity. In this pseudo-code, one direct ancestor is only
queried to verify the positive result of a node.
The proposed algorithm makes more Bloom filter
queries because it checks membership for a node and its
ancestor as well in the case of a Bloom filter positive in the
node. Because the size of a Bloom filter is small enough to
fit in an on-chip memory, the time taken by Bloom filter
queries can be ignored when compared with the time taken
by trie accesses. Furthermore, the proposed algorithm uses
exactly the same architecture as the original trie-based
algorithm. The decision on whether to check the number of
ancestor levels can be adaptively made depending on the
false positive rate of a level.
4. Performance Evaluation
Fig. 4. Search process of the proposed algorithm.
is stored. If a Bloom filter produces a positive result for a
node at level 3, we propose to query level 1 in this
example, which is an ancestor of the node at level 3, to
check whether it is also a positive. Because Bloom filters
have no false negatives, the negative of the ancestor means
that the positive for the current level is false. Therefore,
the false positive rate can be reduced. Assuming that hash
indices are chosen independently, the expected false
Five actual routing tables [8] were used to compare our
proposed algorithm with WBSL-BF and LBSL-BF. These
routing tables have prefixes roughly from 15000 to 227000,
and the number of input IP addresses used in the
simulation is three times the number of prefixes in each
routing table. A 64-bit cyclic redundancy check (CRC) is
used to generate hash indices for both a Bloom filter and a
hash table, and a perfect hashing is assumed for the hash
table. The size of the Bloom filter for simulation was
Table 1. Performance Evaluation Results with WBSL-BF (BF size: 2 Fs ).
WBSL-BF
BF size No. of BF
NT
N
Routing Data
(KB)
queries
Telstra
227223 452732 128
3255242
The Proposed
0.111
No. of trie
accesses
3.514
No. of BF
queries
5650394
Scaling
factor
1.736
0.085
No. of trie
accesses
3.389
pf
pf
Grouptlcom
112310 314986
128
2388570
0.081
3.371
4113662
1.722
0.068
3.311
PORT80
170601 225050
64
1590702
0.136
3.157
2654444
1.669
0.102
3.001
MAE-EAST
39464
172418
64
512900
0.093
2.754
838967
1.636
0.064
2.63
MAE-WEST
14553
76708
32
190281
0.084
2.728
309370
1.626
0.058
2.614
Table 2. Performance Evaluation Results with WBSL-BF (BF size: 4 Fs ).
WBSL-BF
BF size No. of BF
NT
N
Routing Data
(KB)
queries
Telstra
227223 452732 256
3255242
The Proposed
0.026
No. of trie
accesses
3.108
No. of BF
queries
5373923
Scaling
factor
1.651
0.018
No. of trie
accesses
3.070
pf
pf
Grouptlcom
112310 314986
256
2388570
0.012
3.047
3947997
1.653
0.009
3.037
PORT80
170601 225050
128
1590702
0.030
2.661
2487263
1.564
0.021
2.616
MAE-EAST
39464
172418
128
512900
0.011
2.401
797129
1.554
0.007
2.383
MAE-WEST
14553
76708
64
190281
0.008
2.395
294848
1.55
0.005
2.382
167
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Table 3. Performance Evaluation Results with LBSL-BF (BF size: 2 Fs ).
WBSL-BF
BF size No. of BF
(KB)
queries
227223 576370 256
3250168
Grouptlcom
112310 411122
128
2336879
PORT80
170601 299899
128
1586942
Routing Data
Telstra
N
NT
The Proposed
0.089
No. of trie
accesses
3.420
No. of BF
queries
4891309
Scaling
factor
1.505
0.035
No. of trie
accesses
3.134
0.132
3.308
3358695
1.437
0.059
2.916
0.114
3.069
2211064
1.393
0.048
2.710
pf
pf
MAE-EAST
39464
191757
64
562174
0.088
3.783
969992
1.725
0.062
3.643
MAE-WEST
14553
82156
32
213286
0.111
3.399
316190
1.482
0.061
3.108
Table 4. Performance Evaluation Results with LBSL-BF (BF size: 4 Fs ).
WBSL-BF
BF size No. of BF
NT
N
Routing Data
(KB)
queries
Telstra
227223 576370 512
3250168
The Proposed
0.014
No. of trie
accesses
3.066
No. of BF
queries
4760774
Scaling
factor
1.465
0.005
No. of trie
accesses
3.016
pf
pf
Grouptlcom
112310 411122
256
2336879
0.036
2.870
3252403
1.392
0.014
2.755
PORT80
170601 299899
256
1586942
0.019
2.623
2127905
1.341
0.007
2.557
MAE-EAST
39464
191757
128
562174
0.023
3.472
939824
1.672
0.015
3.432
MAE-WEST
14553
82156
64
213286
0.022
2.964
304959
1.430
0.011
2.904
Fig. 5. The comparisons with WBSL-BF in false positive rates.
chosen based on the size factor Fs = 2 2 ( T ) , where
NT is the number of stored nodes. The number of hashing
indices k for the Bloom filter was chosen to achieve the
minimum false positive rate as shown in Eq. (2).
Tables 1 through 4 show simulation results comparing
our proposed algorithm with WBSL-BF or LBSL-BF. In
these tables, N is the number of prefixes in each routing
table. The number of Bloom filter queries for each
algorithm is shown in the table. A scaling factor is the
number of queries in our proposed algorithm divided by
the number of queries in WBSL-BF (or LBSL-BF). As
shown in the scaling factors, our proposed algorithm
performs more BF queries in order to reduce the number of
false positives.
Figs. 5 and 6 show comparisons in the false positive
rates of both algorithms when the BF size is 4 Fs . The
false positive rates are significantly reduced, up to 67%
with our proposed algorithm. Our proposed method can be
log N
Fig. 6. The comparisons with LBSL-BF in false positive rates.
applied to various trie-based algorithms with Bloom filters
without changing the architectures of the algorithms.
5. Conclusion
This paper proposes a different way of reducing the
false positive rate of trie-based algorithms. We proposed to
refer the ancestors of a node to confirm that the positive of
the node is true. Simulation results show that querying one
ancestor of a node can reduce the false positive rate by up
to 67% with exactly the same architecture and the same
memory requirement. Because there is no change in the
architecture itself, our proposal can be adaptively applied
depending on the requirement of the false positive rate.
Moreover, the proposed approach can also be implemented
for other applications with trie-based algorithms
employing Bloom filters.
168
Mun et al.: On Reducing False Positives of a Bloom Filter in Trie-Based Algorithms
Acknowledgement
This research was supported by the National Research
Foundation of Korea (NRF) grant funded by the Korea
government (MEST) (2014R1A2A1A11051762). This
research was also supported by the MSIP (Ministry of
Science, ICT and Future Planning), Korea, under the ITRC
(Information Technology Research Center) support
program (IITP-2015-H8501-15-1007) supervised by the
IITP (Institute for Information & communications
Technology Promotion).
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Copyrights © 2015 The Institute of Electronics and Information Engineers
Hyesook Lim received the B.S. and
M.S. degrees at the Department of
Control and Instrumentation Engineering
in Seoul National University, Seoul,
Korea, in 1986 and 1991, respectively.
She received the Ph.D. degree at the
Electrical and Computer Engineering
from the University of Texas at Austin,
Texas, in 1996. From 1996 to 2000, she had been
employed as a member of technical staff at Bell Labs in
Lucent Technologies, Murray Hill, NJ, USA. From 2000
to 2002, she had worked as a hardware engineer for Cisco
Systems, San Jose, CA, USA. She is currently a professor
in the Department of Electronics Engineering, Ewha
Womans University, Seoul, Korea, where she does
research on packet forwarding algorithms such as IP
address lookup and packet classification, and research on
content centric networks. She is currently working as the
General Affair Director at the Institute of Electronics and
Information Engineers. She is a senior member of the
IEEE.
Ju Hyoung Mun received the B.S. and
M.S. degree at the Department of
Electronics Engineering in Ewha
Womans University, Seoul, Korea, in
2005 and 2007, respectively. From
2007 to 2013, she was employed at
DMC research center of Samsung
Electronics, Korea. She is currently
pursuing a Ph.D. degree from the same university. Her
research interests include packet forwarding algorithms
using Bloom filters and forwarding and cache utilization in
Content Centric Networks.
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.169
169
IEIE Transactions on Smart Processing and Computing
DEX2C: Translation of Dalvik Bytecodes into C Code and
its Interface in a Dalvik VM
Minseong Kim1, Youngsun Han2, Myeongjin Cho1, Chanhyun Park1, and Seon Wook Kim1,*
1
Department of Electrical and Computer Engineering, Korea University / Seoul, Korea
{kissofgod, linux, yasutaxi, seon}@korea.ac.kr
2
Department of Electronics Engineering, Kyungil University / Gyeongsan, Korea youngsun@kiu.ac.kr
* Corresponding Author: Seon Wook Kim
Received March 27, 2015; Revised April 9, 2015; Accepted April 17, 2015; Published June 30, 2015
* Short Paper
* Extended from Conference: Preliminary results of this paper were presented at the IEIE ICEIC in January 2015. This paper
has been accepted by the editorial board through the regular review process that confirms the original contribution.
Abstract: Dalvik is a virtual machine (VM) that is designed to run Java-based Android applications.
A trace-based just-in-time (JIT) compilation technique is currently employed to improve
performance of the Dalvik VM. However, due to runtime compilation overhead, the trace-based JIT
compiler provides only a few simple optimizations. Moreover, because each trace contains only a
few instructions, the trace-based JIT compiler inherently exploits fewer optimization and
parallelization opportunities than a method-based JIT compiler that compiles method-by-method.
So we propose a new method-based JIT compiler, named DEX2C, in order to improve performance
by finding more opportunities for both optimization and parallelization in Android applications. We
employ C code as an intermediate product in order to find more optimization opportunities by using
the GNU C Compiler (GCC), and we will detect parallelism by using the Intel C/C++ parallel
compiler and the AESOP compiler in our future work. In this paper, we introduce our DEX2C
compiler, which dynamically translates Dalvik bytecodes (DEX) into C code with method
granularity. We also describe a new method-based JIT interface in the Dalvik VM for the DEX2C
compiler. Our experiment results show that our compiler and its interface achieve significant
performance improvement by up to 15.2 times and 3.7 times on average, in Element Benchmark,
and up to 2.8 times for FFT in Smartbench.
Keywords: Dalvik, Bytecodes, JIT compiler, DEX2C compiler
1. Introduction
Dalvik [1] is a virtual machine (VM) that executes
Android applications under the Android runtime
environment. Since Dalvik VM’s runtime performance is
intrinsically restricted due to interpretation overhead, a
trace-based just-in-time (JIT) compiler [2, 3] has been
employed to improve performance by dynamically
compiling hot traces into native code and directly
executing them. However, the trace-based JIT compiler is
basically designed to apply very restricted optimizations,
such as constant propagation, redundant load/store
elimination, and so on, to each of the hot traces in order to
alleviate dynamic compilation overhead. Moreover,
because each trace contains only a few instructions, the
trace-based JIT compiler has few opportunities for
optimization and parallelization against a method-based
JIT compiler that handles all the instructions in a method.
In this paper, in order to improve the performance of
applications under the Dalvik VM, we propose a new
method-based JIT compiler named DEX2C. Also, we
employ C as an intermediate product of the method-based
JIT compilation in order to employ additional
optimizations of the GNU C Compiler (GCC), and we will
find parallelism in the C code by using the Intel C/C++
compiler [4] and the AESOP compiler [5] in our future
work. Through this approach, we are able to know which
optimizations are needed and which codes are supposed to
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Kim et al.: DEX2C: Translation of Dalvik Bytecodes into C Code and its Interface in a Dalvik VM
be parallelized in Android applications.
Our performance evaluation shows that the DEX2C
compiler achieves significant performance improvement of
up to 15.2 times and 3.7 times, on average, in Element
Benchmark. Also we achieve performance improvement of
up to 2.8 times under Smartbench.
Our paper is organized as follows. Section 2 describes
the DEX2C compiler infrastructure, and Section 3
evaluates the performance of our DEX2C architecture.
Finally, we offer a conclusion in Section 4.
2. DEX2C Compiler Infrastructure
In this section, we introduce both the overall
architecture of our DEX2C compiler and its interface. Also
we describe the detailed structure of the compiler and the
interface.
2.1 Overall Architecture
Fig. 1 shows the overall architecture of the DEX2C
compiler infrastructure and its overall compilation flow.
The infrastructure is composed of the following two
compilers: the DEX2C compiler for translating the DEX
code of a method into C, and GCC for generating an
executable object file with the generated C code. When
one of the hot-methods, detected in the profiling phase, is
first invoked by the Dalvik VM, the DEX2C compiler
performs DEX-to-C translation. After the translation
completes, GCC compiles the generated C code into an
object file. Finally, the Dalvik VM dynamically links the
object file and executes the target method, the native code
of the object file, instead of interpreting its DEX code.
2.2 DEX2C Compiler Structure
The DEX2C compiler performs the following
sequence: the compiler frontend analyzes method
information, such as method signature, local variables,
DEX code, and so on. After the analysis, the compiler
frontend builds an intermediate representation (IR) that
Fig. 1. Overall architecture of the DEX2C compiler.
basically contains both a symbol table and a control flow
graph with separated basic blocks by branch instructions
from DEX code. Before building the symbol table, the
compiler frontend makes a local variable map that contains
pairs of virtual register numbers and data types of the
register using information on local variables in the DEX
code. Since the DEX code is originally register-based,
resolving data types of registers is essential for DEX-to-C
translation. Unfortunately, since the data types of the
temporary registers used in DEX code are not evidently
specified, the compiler frontend performs a global liveness
analysis in order to find out the data types. In the global
liveness analysis, we employ Def-Use chains. Therefore,
unknown data types of the temporary registers are
ultimately determined with local variable information and
type-specific instructions such as mul-double, int-todouble, and so on. After the symbol table is constructed
with both local and temporary variables, the backend of
the DEX2C compiler traverses each basic block in the
control flow graph and translates its DEX code into a C IR.
The C IR is designed to be nearly equivalent to C language
syntax so that it is able to be directly converted to C.
Finally, the backend emits an epilog, such as a C-style
method signature, including return type, method name, and
parameters. It also emits definitions of the variables in the
symbol table and the C code directly from the C IR.
2.3 Method-based JIT Interface
In order to execute hot-methods as native code on the
Dalvik VM, we implement a method-based JIT interface,
as shown in Fig. 1. When a method is invoked, we
examine whether it is a hot-method or not. If not, a counter
associated with invoking the method is increased. At the
next visit, if the counter value meets a predefined threshold,
the method is set as a hot-method and is going to take a
hot-method path at the next invocation. For the path, we
provide two different ways: one updates a counter and
examines the counter value with the pre-defined threshold;
the other specifies a method to be translated by using a
configuration file. In other words, if we already know
which methods are hot-methods in applications, we can
directly specify the methods to be translated in the
configuration file.
When a method takes the hot-method path, we check
whether a translation of the method already exists or not. If
not, the method is translated into C by the DEX2C
compiler. Next, the generated C code is compiled into an
object file by the GNU C compiler and linked with runtime
libraries [6] that include routines for function calls from
the generated C code to the original application source
code in the Dalvik VM.
Finally, method arguments are copied from Dalvik's
argument stack into the native codes' argument registers
and stack. In Fig. 2, Dalvik has method arguments on its
stack, whereas the native code has its arguments in
registers and a stack. For example, if the number of
employed argument registers is four and the number of
method arguments is less than four, GCC uses registers for
those arguments from the beginning of the registers. If the
number of method arguments exceeds four, native code
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
171
3.1 Experimental Setup
The performance of our DEX2C compiler was tested
using Element Benchmark [7] and Smartbench [8] on
Nexus 7 [9]. Element Benchmark includes addition,
subtraction, multiplication, and division. Smartbench
contains Linpack, FFT, MonteCarlo, LU and Mandelbrot.
In order to analyze both the performance improvement by
executing native code and the overhead due to the methodbased JIT interface, we translated only one method of each
benchmark into C, which occupies most of the execution
time but different function call counts. The generated C
code from the benchmarks was compiled into object files
by using GCC 4.6.0 with -O2 optimization. Also, in the
performance evaluation, dynamic compilation overhead of
the DEX2C compiler was ignored by employing precompiled object files.
3.2 Evaluation Results
Fig. 2. Argument passing from Dalvik VM to native
code.
uses the registers for the first four arguments and the stack
for the rest of arguments. Therefore, the method-based JIT
interface needs to adjust for the difference between the
Dalvik’s argument stack and the native code’s argument
area. Finally, the target method is executed by updating a
program counter to the linking address. Also, the return
value must be transferred from return registers, r0 and r1,
into retval registers of the Dalvik VM.
3. Performance Evaluation
In this section, we present the experimental setup for
performance evaluation and the performance results of the
DEX2C compiler and its interface.
Fig. 3 shows the speedup of our tested benchmarks by
using our proposed scheme. We use the existing Dalvik
VM with the conventional trace-based JIT compilation as a
baseline and normalized all performance results against the
baseline.
There are two factors that determined overall
performance. One is execution time of the translated
method. As explained in Section 3, the method that has the
longest execution time was translated into C. Therefore,
the higher ratio of the execution time of the translated
method to the total execution time implies higher speedup.
The other is interaction between bytecodes and the
translated C code. As mentioned in Section 2.3, we
handled a function call from bytecodes to generated C
code by copying arguments and results between Dalvik’s
area and the native codes’ area. Therefore, more frequent
interaction between them incurs higher overhead during
execution.
As shown in Fig. 3, we could achieve improvement of
3.2 times the speedup in addition, 3.1 times in subtraction,
and 15.2 times in multiplication. Different from the other
benchmarks, division achieved only 1.2 times the speedup.
Those optimization opportunities are reduced because the
Fig. 3. The speedup of Element Benchmark and Smartbench.
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Kim et al.: DEX2C: Translation of Dalvik Bytecodes into C Code and its Interface in a Dalvik VM
division operation is supported by built-in libraries of
Dalvik and GCC. The overhead due to the function call
from bytecodes to the generated C code is almost nothing,
because each translated method in Element Benchmark
invokes once over the entire execution phase. Also, we
could achieve remarkable performance improvement of 2.8
times in FFT only in Smartbench. Linpack, LU, and
Mandelbrot showed almost the same performance as the
conventional Dalvik VM. Unfortunately, MonteCarlo
represents considerable slowdown.
In Element Benchmark, a method that is translated into
C takes 95% of the total execution time in each benchmark.
As a result, we achieve a significant performance
improvement of 3.7 times on average. Similarly, in FFT,
the transform_internal method that occupies 95% of the
total execution time is translated into C. In addition,
because there is no function call in FFT, there is no
function call overhead. Therefore, we could achieve
improvement of 2.8 times the performance. However, in
Linpack, LU, and Mandelbrot benchmarks, the translated
method occupies about 70% of the total execution time. In
addition, interaction occurs occasionally. Therefore, the
performance improvement from executing native code and
the performance slowdown from its interface overhead are
countervailed. As a result, we achieved almost the same
performance as baseline.
In MonteCarlo, the integrate method occupying only
44% time of the total execution time was translated into C.
In addition, a function call that causes performance
slowdown appears frequently. Consequently, we observed
a slowdown of 0.3 times the performance. To summarize,
in Smartbench, we get somewhat different performance
compared to Element Benchmark because of the
characteristics of the benchmarks.
4. Conclusion
To the best of our knowledge, our work is the first
attempt at implementing a method-based JIT compiler and
an interface that supports DEX-to-C translation and its
execution framework. The performance results show that
our DEX2C compiler and its interface achieve reasonable
performance improvement against the existing trace-based
JIT compiler under the Dalvik VM.
In future work, in order to find out what optimization
can be applied to Android applications, we are going to
evaluate performance with various optimization options of
the GCC using our DEX2C infrastructure. We will also
study how to parallelize Android applications with
parallelism opportunities found by the Intel C/C++
compiler and the AESOP compiler through the generated
C code of the DEX2C compiler.
Copyrights © 2015 The Institute of Electronics and Information Engineers
References
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intel.com/en-us/c-compilers, 2014. Article (CrossRef
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Autoparallelizing Computer for Shared Memory
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“Code Generation and Optimization for Java-to-C
Compilers,” Emerging Directions in Embedded and
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google.com/site/elementbenchmark, 2012. Article
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mobile.com, 2012. Article (CrossRef Link)
[9] Google, “Galaxy nexus,” http://www.google.com/
nexus/, 2014. Article (CrossRef Link)
[10] J. Dongarra, P. Luszczek, A. Petitet, “The LINPACK
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IEIE Transactions on Smart Processing and Computing
Exploring Smartphone-Based Indoor Navigation:
A QR Code Assistance-Based Approach
Vinjohn V Chirakkal, Myungchul Park, and Dong Seog Han
School of Electronics Engineering, Kyungpook National University / Daegu, Korea
{vinjohnvc@gmail.com, wndcalm@gmail.com, dshan@knu.ac.kr}
* Corresponding Author: Dong Seog Han
Received May 5, 2015; Accepted June 11, 2015; Published June 30, 2015
* Regular Paper
* Extended from a Conference: Preliminary results of this paper were presented at the IEEE ISCE 2014. This present paper
has been accepted by the editorial board through the regular reviewing process that confirms the original contribution.
Abstract: A real-time, Indoor navigation systems utilize ultra-wide band (UWB), radio-frequency
identification (RFID) and received signal strength (RSS) techniques that encompass WiFi, FM,
mobile communications, and other similar technologies. These systems typically require surplus
infrastructure for their implementation, which results in significantly increased costs and
complexity. Therefore, as a solution to reduce the level of cost and complexity, an inertial
measurement unit (IMU) and quick response (QR) codes are utilized in this paper to facilitate
navigation with the assistance of a smartphone. The QR code helps to compensate for errors caused
by the pedestrian dead reckoning (PDR) algorithm, thereby providing more accurate localization.
The proposed algorithm having IMU in conjunction with QR code shows an accuracy of 0.64 m
which is higher than existing indoor navigation techniques.
Keywords: Indoor navigation, Inertial measurement unit, Location based services, Pedestrian dead reckoning,
QR codes
1. Introduction
Increasing requirements for location-based services
have caused indoor navigation to evolve into a major
research area for human users as well as autonomous
systems. Precise indoor localization opens up a new
frontier of mobile services, and offers significant
opportunities to enhance navigation in indoor
environments. After a massive development effort to
enable outdoor navigation using global positioning
systems (GPS) [1], researchers are currently searching for
an enhanced technology to facilitate accurate navigation in
indoor environments. GPS, a technology commonly used
for outdoor positioning and navigation, cannot be used in
indoor environments. GPS signals suffer a significant
amount of attenuation in indoor environments, thereby
providing very low accuracy [3]. Besides GPS,
technologies that have been utilized for indoor
environment navigation include received signal strength
(RSS)-based techniques that involve WiFi [4, 5], GSM [6,
7] and FM [2], as well as other techniques such as radiofrequency identification (RFID) [8, 9], ultra-wideband
(UWB) [10], and other similar schemes. The technologies
mentioned above require the installation of surplus
infrastructure and sensors. This prevents these
technologies from achieving large-scale deployments [11].
Moreover, a number of these wireless technologies
consume large amounts of memory and battery power, and
may threaten the user’s privacy.
To overcome the above-mentioned hurdles, this paper
utilizes inertial navigation systems (INS) for indoor
navigation. This system records the navigation state, which
contains orientation and acceleration in all three
dimensions, with the aid of measurements from inertial
sensors. These systems have been used as guidance
systems [12] on ships, airplanes, submarines, satellites,
guided missiles, and spacecraft. This system measures
movements with an inertial measurement unit (IMU), a
device that may include sensors such as an accelerometer,
a gyroscope, and a magnetometer, depending on the degree
of freedom to measure the orientation and the acceleration
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Chirakkal et al.: Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
of the device. Owing to rapid advancements in the field of
micro-electro mechanical systems (MEMS), IMUs can be
produced in very small sizes, and have become a popular
smartphone feature in recent years [13]. Using the
information obtained from the IMU along with the user’s
initial position, the current motion of the user can be
tracked; thus, the path traversed by the user can be
recorded. Numerous methods can be used by IMUs to
provide the relative location change of the user. The strapdown integration [14] and pedestrian dead reckoning
(PDR) algorithms [15] are widely used positioning
methods. However, the INS sensor may produce errors
caused by bias, white noise, flicker noise, temperature
effects, and calibration issues [16]. These errors increase
drastically over time. Moreover, because of varying
magnetic fields, huge deviations are caused by the
compass, making INS unsuitable for use as a stand-alone
indoor navigation system [17]. Hence, this system must be
combined with another system that can compensate for the
errors generated by the INS.
Recently, the features of quick response (QR) codes
have been employed for the purpose of navigation, with
the assistance of image processing and recognizing
systems [18]. The QR code is a tag for a type of matrix
barcode. Compared to a traditional one-dimensional (1-D)
code, a QR code incorporates features such as rapid
readability and large storage capacity. Considering
minimal deployment costs for enabling indoor navigation,
this approach is very cost effective when combined with
other existing techniques. This paper proposes a QR codeaided, IMU-based indoor navigation model. This model
effectively reduces the significant error propagations
caused by the accelerometer and gyroscope and hence
provide a better indoor navigation for human users and
autonomous systems. This paper also provides a detailed
discussion of various PDR methods proposed by Weinberg
[19], Kim [20], and Scarlet [21], and also presents
comparisons between them. In addition, error deviations of
the conventional and proposed methods are discussed. This
paper is an extended version of [22].
The paper is structured as follows. Section II provides a
brief overview of the PDR approach and QR codes. The
proposed model is discussed in section III. Experimental
results for the proposed model and comparison results are
exhibited in Section IV. Conclusions are presented in
Section V.
direction cosine matrix, or quaternions. The quaternions
method is advantageous because it is less complex,
provides superior accuracy, and avoids singularity [23].
The strap-down integration method calculates the velocity
and the position by double-integrating the acceleration
obtained from the accelerometer. By integrating the
rotation rate from the gyroscope, the angular orientation is
determined. Because this process requires integrating the
acceleration component, a minor error in acceleration
would generate a significant error after integration. Hence,
the accuracy of the strap-down integration is generally
lower than other methods. In contrast, the PDR is a
pedestrian positioning method, which is based on additive
distance travelled from the initial position. The distance
traversed can be tracked by step detection using an
accelerometer, and the orientation can be calculated using
a gyroscope.
Implementation of the PDR method typically involves
operations such as orientation, projection, filtering, step
detection and step length estimation [15, 24]. Step length
estimation can be performed using either static or dynamic
method. The static method assumes all valid steps will
have equal lengths, whereas the dynamic method assumes
that valid steps can have different step lengths. When
compared to dynamic methods, static methods are less
accurate [25]. Therefore, this study implements dynamic
step length estimation, which will be discussed in detail in
Section III.
The PDR with step detection has numerous advantages.
It reduces errors accumulated by the navigation solution,
because it utilizes the sequential nature of pedestrian
motion [26]. The step detection approach confines the
error to a certain range, because the step length is a
random parameter, which is confined by the muscular
force of a human body [27]. However, one of the major
problems in using PDR for navigation is errors
accumulated over a time span or a distance travelled,
because the current location estimate is based on the prior
estimate of the last step. In addition, PDR must be seeded
with a precise initial position for effective estimation [28].
Hence, errors related to the stride length and orientation,
which are unavoidable with currently available
commercial grade sensors, make PDR unreliable when
used for long time periods or long distances. Therefore,
this technique is merged with other techniques to facilitate
better positioning. Accordingly, this study uses PDR in
conjunction with QR codes.
2. Background
2.2 QR code
Existing methods for indoor navigation using IMU and
a brief introduction to indoor navigation using QR codes
are discussed in this section.
2.1 Pedestrian Dead Reckoning
The well-known methods utilized for indoor
environment navigation with IMUs are the strap-down
integration and PDR algorithms. In the strap-down
integration algorithm, the attitude of the device to which
an IMU is attached is computed using Euler angles, the
A QR code is a 2D image similar to a common barcode,
featuring large information storage capacity and rapid
readability [29]. The QR code is square shaped and is
comprised of a coding region and a functional region [30].
The coding region is typically described by version, format,
and data characters. The functional region is combined
with localizing, correcting and seeking graphs. The QR
code can be read and decoded by smart phones or tablets in
a very straightforward manner. The QR codes in this paper
are embedded with grid locations, to navigate the user
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
175
Fig. 1. The existing PDR model using scarlet approach.
from the source to the destination. Costa-Montenegro et al.
[31] have demonstrated an indoor navigation system using
the QR code. This method requires location and map
servers to be deployed, thereby increasing the cost.
Alghamdi et al. [32] have also proposed a method for
indoor navigation using QR codes and RFID; however,
large-scale deployments of this method have also been
hampered because of high costs. Chiou et al. [33] proposed
a similar algorithm using PDR and QR codes, but this
algorithm provides lower accuracy than other methods.
3. Proposed QR Code-aided PDR system
In this section, one of the existing PDR models [25] is
discussed, followed by a discussion of the proposed
approach. The proposed approach is comprised of a
modified PDR model and a QR code-assisted PDR
approach.
The block diagram of the existing PDR method [25]
using the scarlet approach [21] as step length estimation is
displayed in Fig. 1. PDR Implementation using a
smartphone includes various processes such as filtering,
step detection, and step length estimation.
The raw values of three axis accelerometers and three
axis gyroscopes are obtained from the IMU of the
smartphone. As a first procedure, the absolute acceleration
is obtained from the raw acceleration values. These
absolute acceleration values are then filtered to obtain the
desired output signal. The acceleration values are first
filtered using a high pass filter and then using a low pass
filter. The high pass filtering is performed to eliminate the
influence of gravity and noise [24]. This can be
implemented using the following equations:
yh [i ] = x[i ](1 − α ) + yh [i − 1]α
z[i ] = x[i ] − yh [i ]
(1)
(2)
where yh [i ] is the mean of the signal, x[i ] is the raw
acceleration value, z[⋅] is the output of the high pass
filtered signal, and α is a constant used to optimize the
filter. Eqs. (1) and (2) represents the simplest way to
perform high pass filtering. The mean of the obtained
waveform, which represents the low frequency
components as displayed in (1) is subtracted from the
signal as displayed in (2); this ensures that only high
frequency components appear in the output and the offset
of the signal is zero. A low pass filter is applied to the
resulting zero offset signal by implementing a moving
average filter as
yl [i ] =
1
M
( M −1)/ 2
∑
j =− ( M −1)/ 2
z[i + j ]
(3)
Fig. 2. Vertical movement of hip while walking [19].
where yl [i ] is the average filtered output, z[⋅] is the signal
from the high pass filter, and M is the moving window
size.
The low pass filtering is implemented to decrease the
noise in the signal. Averaging reduces the high frequency
components in the signal, thereby smoothening the signal.
The moving average signal is obtained based on a subset
of the current and previously recorded data, thus
attenuating the high frequency samples; however, signal
flattening is performed in moderation to avoid losing the
original features of the waveform.
After applying the filters to the values of the detected
axis, the step detection algorithm should be applied,
because the distance travelled is represented by the user’s
steps. There are two step-detection methods that can be
used to analyze acceleration signals: peak detection [20,
24] and zero crossing detection [34, 35]. The zero crossing
method tallies signals that cross the zero level to determine
step occurrences. The time interval thresholding is
employed to reject false step detection. This method is not
suitable for detecting a user’s step, because a certain time
interval threshold is required to decide whether the zero
crossing represents a valid step. The problem occurs when
time intervals between footfalls vary for different subjects.
In the peak detection method, the main objective is to
detect the peaks of acceleration. The peaks of vertical
acceleration correspond to the step occurrences, because
the vertical acceleration is generated by the vertical impact
that occurs when the foot hits the ground.
In this paper, step detection is implemented using peak
detection rather than the zero crossing method. Peak
detection is performed using a variable threshold [15],
thereby detecting the maxima and minima. The upper
threshold is determined by adding the last valid minima
with a threshold value, while the lower threshold is
determined by subtracting the last valid maxima with a
threshold value.
As mentioned in Section II, there are two methods for
estimating the step length: the static and the dynamic
method. The static method assumes that all the valid steps
have the same step length, whereas the dynamic method
assumes all valid steps have different step lengths, which
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Chirakkal et al.: Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
can be estimated using certain approaches. This paper
discusses three approaches, proposed by Weinberg [19],
Kim [20], and Scarlet [21].
In the Weinberg approach, the vertical bounce, which
is caused by impact while walking, is proportional to the
step length as displayed in Fig. 2. The step length sw is
calculated using the peak to peak difference at each step as
sw = k w ⋅ 4 amax − amin
The Weinberg distance Dw is
multiplying the number of steps n as
Dw = n ⋅ sw
(4)
calculated
by
(5)
where amax and amin are the maximum and minimum
acceleration, respectively, and k w is a multiplier constant
given as 0.41.
In the Scarlet approach, the accuracy problem caused
by the spring variations in the steps of different people is
solved. This approach demonstrates a relationship between
maximum acceleration, minimum acceleration and average
acceleration of the step length ss as
ss = k s
aavg − amin
amax − amin
(6)
N
aavg = ∑ am / N
(7)
m =1
where aavg is the average acceleration, respectively, ks is a
constant multiplier given as 0.81, and moving average size
N is given as 16. The measured acceleration values are
denoted by am . The Scarlet distance Ds can be calculated
by multiplying the number of steps n as
Ds = n ⋅ ss
(8)
In Kim’s approach, a relation between step length skim
and average acceleration am is given as
skim = kk 3
∑
N
m =1
am / N
(9)
where kk is a constant given as 0.98, and moving average
size N is given as 16. The Kim distance Dkim can be
calculated by multiplying number of steps n .
Dkim = n ⋅ skim
(10)
However, the existing PDR model [25] using a
conventional scarlet approach [21] for step length
estimation, does not account for the orientation of the user
and hence likely to get more erroneous location estimates.
Hence, the proposed model as seen in Fig. 3 overcomes
this drawback by implementing a gyroscope to track the
Fig. 3. Block diagram for the proposed PDR implementation.
orientation of the user with the scarlet approach. A better
result is obtained in terms of accuracy when orientation is
used with the scarlet method for location estimation.
Furthermore, the proposed algorithm presents an efficient
indoor navigation technique using QR codes as seen in Fig.
4 to compensate for errors in the modified PDR technique.
The block diagram of the proposed PDR model by
incorporating orientation with scarlet method [21, 25] is
shown in Fig. 3. Raw gyroscope values are obtained, in
radians per second, from the IMU of the smartphone.
These raw gyroscope values are converted to degrees per
second to obtain the rotated angle. Using the rotated angle,
the orientation is calculated. The rotated angle is merged
with the step detection that utilizes peak detection, to
acquire the orientation of the user.
Furthermore, the proposed system using QR codes as
an error compensator is displayed in Fig. 4. This paper also
proposes an indoor navigation technique using IMU in
conjunction with QR codes. To enable the real time indoor
navigation, the smartphone must be equipped with the
blueprint of the building, as well as a database that stores
the QR code location with respect to the blueprint. The
user has the ability to key in the destination, in case the
database must be consulted to determine the nearest QR
code in the vicinity of the destination. The proposed
algorithm uses QR codes to assist PDR, thereby reducing
the drift errors generated by the accelerometer and
gyroscope. Therefore, the QR code is used as an error
compensator. Moreover, the important factor while
implementing indoor navigation using IMU is the initial
position, hence in order to have a more accurate initial
position QR code is used in this study. The PDR algorithm
runs continuously, tracing the path of the user. When a QR
code is read, the position or location is corrected to the one
represented by the QR code, thereby suppressing drift
errors. A performance analysis comparing the proposed
algorithm with a conventional algorithm using Weinberg
and Kim’s approach is presented in the subsequent section.
One of the primary considerations for the proposed QR
code-based algorithm is determining the number of QR
codes required for the implementation. Utilizing a greater
number of QR codes considerably increases the size of the
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
177
Fig. 4. Proposed PDR with QR code assistance for
navigation.
database, thereby reducing the performance of the system.
Based on the experimental data, an optimal performance is
achieved by placing a QR codes 10 m apart. However, this
represents a tradeoff because increasing the number of QR
codes can increase the accuracy of the system. Considering
this tradeoff between the number of QR codes and the
accuracy of the system, the selected distance of 10 m
demonstrates an optimal performance.
4. Experimental Results
In this section, the implementation of QR codes, the
experimental setup and the performance analysis are
presented. Unlike other techniques like foot or waist
mounted IMU, this study implements the PDR technique
on a smartphone.
4.1 QR Code Layouts
As an initial step, the blueprint of the entire building is
placed on a grid to identify each location in terms of
coordinates. The QR codes are placed 10 m apart on
floorings of the corridor as displayed in Fig. 5. The 10 m
separation is the result of the tradeoff considerations
discussed in the previous section. Each QR code placed on
the floor of the building will represent location coordinates,
to help determine the location of the user. (X, Y) values
are assigned to each QR code, based on the blueprint.
Finally, the blueprint augmented with the QR codes is
provided to the user through WiFi, Bluetooth, or other
similar data sources. The QR codes can be generated using
free software available online.
4.1 QR Code Layouts
To demonstrate navigation in an indoor environment,
the proposed algorithm was tested using a smartphone. For
experimental purposes, the path from room number 515 to
509 on the 5th floor of building IT-1 at Kyungpook
National University is considered. The floor layout is
shown in Fig. 5, where the entire layout has been
augmented with a grid. The sampling rate of the
smartphone’s IMU is set to 100 Hz for the experiment. The
smartphone was placed in the hand of the user with the
camera facing the floor of the building, making it feasible
Fig. 5. QR code placement on the blueprint augmented
with a grid, and the test path considered in the
experiment.
for the QR code placed on the floor to be read by the
smartphone. It is usually seen that during indoor
navigation the user ideally places the smartphone as
mentioned above rather than in other places.
In the real time navigating scenario, the blueprint
augmented with QR codes is first downloaded to the smart
phone or tablet using WiFi or Bluetooth, or directly from a
PC. The user is then able to navigate by reading the QR
codes, which are attached to the floor, with their
smartphone. The QR codes read by the smartphone are
utilized in conjunction with the PDR algorithm. The
unique algorithm used in this study restricts the location
estimates from deviating by using the QR codes. Once a
QR code is read, the location determined by the values of
the accelerometer and gyroscope is merged with the
location of the QR code, thereby restricting the errors from
the accelerometer and gyroscope.
4.2 Results
The simulation results of the PDR model presented in
Section III are presented here. The absolute acceleration is
obtained from the raw values of the three-axis
accelerometer, as shown in Fig. 6.
Absolute acceleration output obtained from previous
step is passed through a high pass filter using (1) and (2) is
shown in Fig. 7. The weighting value α in (1) is
considered to be 0.9 [24].
The low pass filter output applied to the high pass filter
result is displayed in Fig. 8. The low pass filter in (3) is
simulated with an M value of 15. On obtaining the
filtered result the next step is to detect the steps of the user.
Fig. 9 displays the zero crossing method for step detection.
It can be seen that it is inefficient in detecting the user’s
steps due to a fixed time interval thresholding. Hence a
peak detection method is employed instead of zero
crossing method for step detection.
The peak detection employed in this study can be
observed in Fig. 10. The threshold value is determined to
be 0.8. To ensure a valid step, a time interval of 150 ms
178
Chirakkal et al.: Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
Fig. 9. Zero crossing method for step detection.
Fig. 6. Absolute acceleration from raw values obtained
from the three- axis accelerometer.
Fig. 10. Peak detection using a variable threshold.
Fig. 7. Raw acceleration values filtered using a high
pass filter (HPF).
Fig. 8. The filtered signal after the HPF is filtered by a
low pass filter (LPF).
between maxima and minima is also determined
experimentally.
The obtained step detection is used to achieve step
length estimation using the Scarlet approach as per (6) (8). As per the proposed method, the orientation factor is
used with the Scarlet approach for step length estimation
for a better and accurate location estimation.
Hence, the gyroscope implementation as per Fig. 4 is
displayed below. The raw values of roll, pitch, and yaw
from a three axis gyroscope in radians per second are
displayed in Fig. 11. These values are then converted from
radians per second to degrees per second as displayed in
Fig. 12, to obtain the orientation.
The obtained result in degree per second is augmented
with step detection as per Fig. 4, to determine the step
rotation. This is displayed in Fig. 13. Finally, the obtained
step rotation is used along with the step length estimation
in order to calculate the position of the user.
In order to analyze the system in terms of accuracy, a
performance analysis is carried out on the proposed system.
The performance analysis of the system is divided into
two parts. First, the analysis of different step length estima-
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Fig. 11. Raw gyroscope values.
Fig. 12. Rotated angle in degrees per second.
Fig. 13. Step rotation angle.
179
Fig. 14. Traversed distance using PDR and various
step length methods.
Fig. 15. Comparison between conventional PDR and
the proposed method.
tion approaches is performed, followed by analysis of the
proposed model. As mentioned in section III, this paper
presents three step-length estimation approaches from
Weinberg, Kim, and Scarlet. A comparison between these
three approaches is presented in Fig. 14. Based on the
comparison graph displayed in Fig. 14, it is evident that
the average error rate of the Scarlet approach is much
lower than the error rates of the other approaches.
Therefore, the Scarlet approach is utilized to estimate the
step length. The implementation of the Scarlet approach on
the blueprint of the building is displayed in Fig. 16.
Employing the Scarlet approach, the proposed
algorithm using QR codes is established. The QR code
assists the PDR algorithm in determining the precise
location of the user. This is displayed in Fig. 15. In this
figure, the plot illustrates the comparison between the
conventional PDR approach and the proposed algorithm
using QR codes and PDR. As exhibited in Fig. 15, the
proposed method demonstrates enhanced performance
compared to conventional PDR approaches. The detailed
comparison is listed in Table 1. The proposed algorithm
provides an overall accuracy of 0.64 m, which is
180
Chirakkal et al.: Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
Table 1. Distance estimation Error.
Proposed Kim approach
Average Error
(meters)
1.40
Proposed Weinberg approach
1.41
Proposed Scarlet approach
1.22
Proposed Scarlet + QR code approach
0.64
Method
service systems. The system proposed is targeted for both
autonomous system as well as human users
Acknowledgement
This research was supported by the MSIP (Ministry of
Science, ICT & Future Planning), Korea, under the CITRC (Convergence Information Technology Research
Center) (IITP-2015-H8601-15-1002) supervised by the
IITP (Institute for Information & communication
Technology Promotion).
References
Fig. 16. PDR with QR Code navigation assistance in a
real time scenario.
significantly better than the conventional PDR algorithm
proposed in [24].
The implementation of the proposed algorithm using
QR codes and PDR on a blueprint of a building is
illustrated in Fig. 16.
5. Conclusion
This paper proposes two models for indoor navigation,
an improvement in the existing PDR technique (that
employs scarlet approach [21, 25]) by including the
gyroscope values and using this improved PDR technique
in conjunction with the QR code. Moreover, this paper also
provides a comparison of various step estimation
approaches and step detection methods; these results were
utilized for selecting the most suitable step estimation and
detection techniques for the proposed algorithm. Based on
the results displayed above, the improved PDR technique
used in conjunction with QR codes provides improved
accuracy in comparison with other methods.
The following features make the proposed approach
superior to other existing indoor navigation techniques. (i)
This technique provides greater accuracy. (ii) This
technique does not require the assistance of any wireless
based networks, other than the initial downloading of the
blueprint. (iii) Infrastructure costs are minimal, increasing
the viability of a wide range of indoor navigation
implementations. (iv) Real-time navigation is unaffected
by network traffic, because this method is not dependent
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the building, the whole system must be re-implemented.
The resolution of the camera also plays a vital role,
because adequate light is required for the QR code to be
visible for detection. Considering the tradeoffs, the
proposed technique is optimal for various location-based
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Chirakkal et al.: Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
Vinjohn V. Chirakkal received his B.
Tech in Electronics and Communication from Christ University, Bangalore,
India in 2013. He is currently pursuing
his M.S. degree in the School of
Electronics Engineering, Kyungpook
National University, Daegu, Korea.
His main area of research is in indoor
navigation, computer vision and image processing.
Myungchul Park received his B.S.
degree in electronics engineering and
computer sciences from Kyungpook
National University (KNU), Daegu,
Korea, in 2013. He is currently
working toward his M.S. degree in the
School of Electronics Engineering,
KNU. His research interests include
indoor navigation and MIMO-OFDM.
Dong Seog Han received his B.S.
degree in electronic engineering from
Kyungpook National University (KNU),
Daegu, Korea, in 1987, and his M.S.
and Ph.D. degrees in electrical engineering from the Korea Advanced
Institute of Science and Technology
(KAIST), Daejon, Korea, in 1989 and
1993, respectively. From October 1987 to August 1996, he
was with Samsung Electronics, Co. Ltd., where he
developed the transmission systems for QAM HDTV and
Grand Alliance HDTV receivers. Since September 1996,
he has been with the School of Electronics Engineering,
KNU as a Professor. He worked as a courtesy Associate
Professor in the Department of Electrical and Computer
engineering, University of Florida in 2004. He was
director at the center of Digital TV and Broadcasting in the
Institute for Information Technology Advancement (IITA)
from July 2006 to July 2008. His main research interests
include digital broadcasting and communication systems.
Copyrights © 2015 The Institute of Electronics and Information Engineers
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.183
183
IEIE Transactions on Smart Processing and Computing
A 10-bit 10MS/s differential straightforward SAR ADC
Behnam Samadpoor Rikan, Hamed Abbasizadeh, Dong-Soo Lee, and Kang-Yoon Lee
College of Information and Communication Engineering, Sungkyunkwan University / Suwon, South Korea
{behnam, hamed, blacklds, klee}@skku.edu
* Corresponding Author: Kang-Yoon Lee
Received April 29, 2015; Revised June 10, 2015; Accepted June 15, 2015; Published June 30, 2015
* Regular Paper
Abstract: A 10-bit 10MS/s low power consumption successive approximation register (SAR)
analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter
(DAC) is presented in this paper. In the proposed capacitive DAC, switching is always
straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most
significant bit (MSB) is decided without any switching power consumption. The application of the
straightforward switching causes lower power consumption in the structure. The input is sampled at
the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity
and a higher effective number of bits. The comparator applies adaptive power control, which
reduces the overall power consumption. The differential prototype SAR ADC was implemented
with 0.18µm complementary metal-oxide semiconductor (CMOS) technology and achieves an
effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure
consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious
free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95
fJ/conversion-step.
Keywords: SAR ADC, Straightforward, Comparator, CDAC
1. Introduction
High performance analog-to-digital conversion on a
nanometer scale is performed according to high-speed
switching rather than amplifying. The nature of a
successive approximation register (SAR) analog-to-digital
converter (ADC) is based on high-speed switching. While
low-power characteristics of a SAR ADC have increased
the application of this structure, it suffers from low speed
because, for each conversion, a large number of decision
cycles is required. The necessity for, and interest in, higher
speed and lower power consumption for SAR ADCs has
given rise to many efforts to increase the speed of these
blocks and surpass this drawback. Besides, a lot of
techniques are used to decrease the power consumption of
these blocks [1-4].
In this paper, we will present straightforward DAC
switching for SAR ADCs. Here, the most significant bit
(MSB) is decided without any switching energy. The input
voltage is sampled at the bottom plate and, in each cycle, the
capacitor will switch from common mode voltage (VCM) to
source voltage (VDD) or ground (VSS). Unlike the
conventional structures, in each cycle, only the next capacitor
in the DAC will switch up or down, and the capacitor that
has been switched to VDD or VSS in the previous step will
remain intact without any switching. So, the switching is
always straightforward. This sequence of switching
eliminates wasted switching steps and causes lower power
consumption. Besides, because in each step, we switch only
from VCM to VDD or from VCM to VSS, the speed of
charging and discharging the capacitors will increase.
The organization of this paper is as follows. Section 2
proposes a straightforward algorithm for SAR ADCs. A 10bit prototype SAR ADC using a straightforward switching
sequence is implemented in Section 3. Section 4 reports the
simulation results, and Section 5 concludes the paper.
2. Straightforward SAR ADC switching
sequence
The DAC switching sequence for a three-bit
differential straightforward SAR ADC is shown in Fig. 1.
This switching algorithm is slightly different than
184
Rikan et al.: A 10-bit 10MS/s differential straightforward SAR ADC
will decide MSB-1. The sequence for deciding the next bit
is similar.
In this structure, the largest capacitor in each CDAC is
2c, which is half of the conventional structures. If we
assume a single-ended structure, the number of unit
capacitors in a straightforward structure is half of that in a
conventional structure. Besides, in each cycle the
switching is from VCM to VREF or GND (which, in other
recent structures, is from VREF to GND, or vice versa).
The proposed structure for the SAR ADC is called
straightforward because, unlike other structures, in each
cycle, only the next capacitor in the CDAC will switch to
VREF or GND, and the capacitor that was switched in the
previous step will remain intact without any switching. It
reduces wasted power and increases the speed of the switching.
The bottom-plate, sampling-based, straightforward structure
can be used for higher resolutions because it provides
better linearity in principle [5].
Note that the MSB is decided without any extra
switching. The reference voltages for comparison are
implemented inside the CDACs.
previously reported Vcm-based structures [1, 2]. In the
first step (A), VIP and VIN (differential input voltages) are
connected to the bottom plates of the capacitors in
CDACY and CDACX, respectively. Besides, the top plates
of the CDACs are connected to the VCM. In this step,
VX=VCM-VIN and VY=VCM-VIP are sampled in
CDACX and CDACY. After sampling (B), the bottom
plates of the two CDACs are switched to the VCM. In this
step, we will have VX=2VCM-VIN and VY=2VCM-VIP,
and the MSB will be decided. If VX>VY (VIP>VIN), then
the output of the comparator will be high, and the MSB
will be 1; otherwise, it will be 0. For the next cycle, if the
MSB is 1, the 2c capacitors in CDACX and CDACY will
switch to GND and VREF, respectively (C). In this way,
VX will decrease to 2VCM-VIN-VCM/2, and VY will
increase to 2VCM-VIP+VCM/2. On the other hand, if
MSB is 0, the 2c capacitor in CDACX will connect to
VREF, and the one in CDACY will switch to GND and
VX=2VCM-VIN+VCM/2, VY=2VCM-VIP-VCM/2 voltages
will be available at the input terminals of the comparator
(D). After this redistribution is finished, the comparator
VIN
2c
c
CDACX
c
2c
YES
GND
2c
c
c
VX=2VCM-VIN-VCM/2
VX > VY ?
+
-
2c
c
YES
-
c
+
VY=2VCM-VIP
2c
c
NO
VCM
VX > VY ?
-
VCM
B
2c
c
c
VCM
VCM
VX > VY ?
-
2c
c
c
2c
c
c
+
VX=2VCM-VIN+VCM/4
VY=2VCM-VIP-VCM/4 2c
c
c
GND
VREF
VX > VY ? VCM
YES
VREF
2c
c
c
+
VX=2VCM-VIN+VCM/2
VY=2VCM-VIP-VCM/2
2c
c
VCM
VX > VY ?
VCM
VREF
-
2c
c
GND
NO
c
c
VX=2VCM-VIN+3VCM/4
VY=2VCM-VIP-3VCM/4
2c
c
+
VX > VY ?
-
c
GND
VCM
Sample mode (cycle 0)
Hold mode (cycle 1)
+
VX=2VCM-VIN-VCM/4
VY=2VCM-VIP+VCM/4
VCM
GND
VREF
D
c
NO
c
VREF
GND
VCM
c
VX=2VCM-VIN
c
VX > VY ?
-
VCM
VREF
GND
VREF
VCM
2c
+
VREF
+
A
c
c
VX=2VCM-VIN-3VCM/4
VY=2VCM-VIP+3VCM/4
c
VY=2VCM-VIP+VCM/2
2c
c
VCM
VX=VCM-VIN
VY=VCM-VIP
CDACY
c
VCM
VCM
VIP
2c
VCM
GND
C
Redistribution mode (cycle 2)
Fig. 1. 3 bit differential straightforward switching sequence.
Redistribution mode (cycle 3)
185
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
next sampling and bit decision, output of the ADC remains
intact unless the reset signal becomes low. A somewhat
similar switching structure has been applied [6], but the
difference is that the DAC structure is based on a C-R
hybrid DAC, which employs a two-step split-capacitor array.
The DAC structure we applied does not have the complexity
of the above-mentioned structure, and the overall structure
has comparable results. Also, according to our simulations,
applying a split capacitor array to a DAC structure degrades
the linearity of the system.
Fig. 3 presents a block diagram of the comparator [7, 8].
During the reset phase (CLK=0 and CLKD=0), the
intermediate nodes (m+, m-) and output nodes (O+, O-) are
charged to VREF through M1, M2 and M6, M7, which are
turned on by the inputs at around common-mode voltage.
In phase 1 during comparison (CLK=1 and CLKD=0), M5
is turned on, and a current path from supply to ground
through the dynamic inverter (M1-M4) is created.
Furthermore, the intermediate nodes (m+ and m-) are
discharged with a time difference (Δt) depending on the
comparator’s inputs and the skew rate of the dynamic
inverters. Also, adaptive power control (APC) has been
applied in this comparator. The APC signal reduces the
active time of the comparator, which causes total power
consumption to be reduced.
3. Prototype 10-bit SAR ADC structure
The top block diagram of the proposed SAR ADC is
shown in Fig. 2. This is a differential SAR ADC with a
straightforward switching sequence. VIN is sampled in
CDACX, and VIP is sampled in CDACY. In this structure
the inputs are sampled in bottom plates of the capacitors.
In the CDAC structures, unit capacitor values are 29fF,
which is limited with the process. The maximum capacitor
value in each CDAC is 256c, which is half of the
conventional ones. To decide each bit (except MSB), in
each CDAC, one of the capacitors switches from VCM to
VREFT or VREFB, which is the half their previously
reported counterparts. This causes higher speed and lower
power consumption. Besides, the decision as to the MSB
without charging or discharging an extra capacitor is
another reason for the lower power consumption of this
structure.
Moreover, in Fig. 2 we can see the timing diagram of the
ADC. At the rising edge of the clock, if the reset signal is
high, and we have high in the start signal, sampling of the
input will start. After sampling is finished, the structure
starts to decide the output bits from MSB to the least
significant bit (LSB). At each positive edge of the clock, one
bit is decided, and after the decision is finished, until the
VCM
256c
128c
2c
c
c
….
Control Bits
VIN
VCM
VREFT
VREFB
Control Bits
VIN-
Reference
Voltage
Generator
2n-2C
VT
VCM
VB
C C
CLK
...
+
Comparator
_
VIN+
SAR
LOGIC
VB
...
VCM
VT
2n-2C
C C
Control Bits
CLK
START
RESET
Sampling
`
ADCout
B9 – B0
`
Fig. 2. (a) Top block, (b) Timing diagram of the proposed ADC.
OUTPUT
186
Rikan et al.: A 10-bit 10MS/s differential straightforward SAR ADC
Magnitude(DBFS)
Fig. 4. DC Analysis Results.
0
-10
ENOB=9.35
SNDR=58dB
SFDR=65dB
-30
-50
-70
-90
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency(fIN/fS)
Fig. 3. Comparator structure and APC control.
Fig. 5. Spectrum of the output samples for the input 1.5
MHz at 10MS/s.
4. Simulation Results
Simulation results for the proposed ADC have been
implemented with 0.18-μm CMOS technology. Fig. 4
shows the DC analysis results for this ADC. The DC
analysis results that are extracted from ramp simulation are
as follows.
DNL max and DNL min are 1.0 and -1.0 LSB,
respectively. INL max and INL min are 0.55 and -0.69
LSB, and Sigma DNL and Sigma INL for this structure are
0.152 and 0.287 LSB.
Fig. 5 implements a fast Fourier transform (FFT) of the
output. In this simulation, the input is a 1.5MHz sine wave
sampled at 10MS/s. The effective number of bits (ENOB)
for this simulation is 9.35. SNDR and SNR are 58.02 and
59.98dB, respectively, and SFDR is 64.94dB. This ADC
consumes around 290µA from a 1.8V source, so the
current consumption of this structure is 522µW. In Fig. 6,
SNDR and SFDR for different input frequencies from DC
to Nyquist rates have been illustrated. The FOM was
calculated to be 95fJ/Conv-step according to the following
equation:
FOM =
2
ENOB
Power
× min{2 × ERBW , f s }
(1)
Finally, the summary of the simulation results and
Fig. 6. SNDR and SFDR for the different input ranges
from DC to Nyquist rate.
comparison is presented in Table 1.
6. Conclusion
In this paper, we have proposed a 10-bit SAR ADC.
We applied a straightforward structure for the CDAC and
adaptive power control for the comparator, which reduces
power consumption. This ADC was implemented with
CMOS 0.18-µm technology. The power consumption for
this structure is 522µW under a 1.8 V supply. It has 59.5
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Table 1. Summary and comparison results.
Parameters
Process (nm)
Resolution (bits)
Sampling Rate (MS/S)
Supply Voltage (V)
ENOBPeak
SNDRpeak (dB)
SFDRpeak (dB)
Sigma DNL (LSB)
Sigma INL (LSB)
Power (mW)
FOM (fJ/Conv-step)
[9]
180
10
14
1.8
9.76
60.5
72
0.51
0.98
4
343
[10]
180
10
5
1.2
9.12
56.7
67.8
0.32
0.42
3.6
-
This work
180
10
10
1.8
9.59
59.5
67.1
0.152
0.287
0.52
95
dB SNDR and 67.1 SFDR under a 10MS/s conversion
speed. In this conversion speed for all frequencies from
DC to Nyquist rate, the ENOB is above 9.1 bits. The figure
of merit is 95fJ/conversion-step.
Acknowledgement
This work was supported by the Industrial Strategic
Technology Development program, 10050689 funded by
the Ministry of Trade, Industry & Energy(MI, Korea).
This work was also supported by IDEC (IPC, EDA
Tool, MPW).
References
[1] B. G. Lee and S. G. Lee, “Input-tracking DAC for
low-power high-linearity SAR ADC,” Electronic
Letters, Aug. 2011. Article (CrossRef Link)
[2] C. Yuan and Y. Lam, “Low-energy and area-efficient
tri-level switching scheme for SAR ADC,”
Electronic Letters, Apr. 2012. Article (CrossRef Link)
[3] B. Kim, L. Yan, J. Yoo, N. Cho and H-J Yoo, “An
Energy-Efficient Dual Sampling SAR ADC with
Reduced Capacitive DAC,” Circuits and Systems,
ISCAS. IEEE International Symposium, 2009. Article
(CrossRef Link)
[4] J. Lin, W. Yu and G.C. Temes, “Multi-step capacitorsplitting SAR ADC,” Electronic Letters, Oct. 2010.
187
Nov. 2011. Article (CrossRef Link)
[8] M. Miyahara, Y. Asada, D. Paik and A. Matsuzawa,
“A Low-Noise Self-Calibrating Dynamic Comparator
for High-Speed ADCs,” IEEE Asian Solid-State
Circuits Conference, Nov. 2008. Article (CrossRef
Link)
[9] C. Y. Li, C. W. Lu, H. T. Chao and C. Hsia, “A 10Bit Area-Efficient SAR ADC with Re-usable
Capacitive Array,” IEEE International Conference on
Anti-Counterfeiting, Security and Identification
(ASID), 2012. Article (CrossRef Link)
[10] C. C. Lu, “A 1.2V 10-bit 5 MS/s CMOS Cyclic
ADC,” IEEE International Symposium on Circuits
and Systems (ISCAS), 2013. Article (CrossRef Link)
Behnam Samadpoor Rikan was born
in Urmia, Iran, in 1983. He received
his BSc in Electronic Engineering
from Urmia University, Urmia, Iran, in
2008 and an MSc in Electronic Engineering from Qazvin Azad University,
Qazvin, Iran, in 2013, where he is
currently working toward a PhD in the
School of Information and Communication Engineering at
Sungkyunkwan University, Suwon, Korea. His research
interests include the design of high-performance data
converters, bandgap reference voltage, low-dropout regulators
and ultra-low power CMOS RF transceivers.
Hamed Abbasizadeh was born in Suq,
Iran, in 1984. He received his BSc in
Electronic Engineering from Bushehr
Azad University, Bushehr, Iran, in
2008 and an MSc in Electronic Engineering from Qazvin Azad University,
Qazvin, Iran, in 2012, where he is
currently working toward a PhD in the
School of Information and Communication Engineering at
Sungkyunkwan University. His research interests include
the design of high-performance data converters, bandgap
reference voltage, low-dropout regulators and ultra-low
power CMOS RF transceivers.
Article (CrossRef Link)
[5] P. W. LI, M. J. Chin, P. R. Gray and R. Castello, “A
Ratio-Independent Algorithmic Analog-to-Digital
Conversion Technique,” IEEE Journal of Solid-State
Circuits, VOL. SC-19, NO.6, Dec. 1984. Article
(CrossRef Link)
[6] Y. M. Kim, J. S. Park, Y. J. Shin and S. H. Lee, “An
87 fJ/conversion-step 12 b 10 MS/s SAR ADC using
a minimum number of unit capacitors,” Analog Integr
Circ Sig Process, 2014. Article (CrossRef Link)
[7] C. H. Chan, Y. Zhu, U. F. Chio, S. W. Sin, S. P. U, R.
P. Martins, “A Reconfigurable Low-Noise Dynamic
Comparator with Offset Calibration in 90nm
CMOS,” IEEE Asian Solid-State Circuits Conference,
Dong-Soo Lee was born in Korea, in
1987. He received his BSc and MSc
from the Department of Electronic
Engineering at Konkuk University,
Seoul, Korea, in 2012, and in electronic engineering at Sungkyunkwan
University, Suwon, Korea, in 2014,
respectively. He is currently working
toward a PhD in electronic engineering at Sungkyunkwan
University. His research interests include CMOS RF ICs
and phase locked loops, silicon oscillators, and sensor
interface design.
188
Kang-Yoon Lee was born in Jeongup,
Korea, in 1972. He received his BSc,
MSc and PhD from the School of
Electrical Engineering at Seoul
National University, Seoul, Korea, in
1996, 1998, and 2003, respectively.
From 2003 to 2005, he was with GCT
Semiconductor Inc., San Jose, CA,
where he was a Manager in the Analog Division and
worked on the design of a CMOS frequency synthesizer
for CDMA/PCS/PDC and single-chip CMOS RF chip sets
for W-CDMA, WLANs, and PHS. From 2005 to 2011, he
was with the Department of Electronics Engineering,
Konkuk University as an Associate Professor. Since 2012,
he has been with the School of Information and Communication Engineering, Sungkyunkwan University, where he
is currently an Associate Professor. His research interests
include implementation of power integrated circuits,
CMOS RF transceivers, analog integrated circuits, and
analog/digital mixed-mode VLSI systems.
Copyrights © 2015 The Institute of Electronics and Information Engineers
Rikan et al.: A 10-bit 10MS/s differential straightforward SAR ADC
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
http://dx.doi.org/10.5573/IEIESPC.2015.4.3.189
189
IEIE Transactions on Smart Processing and Computing
Design of a 12b SAR ADC for DMPPT Control in a
Photovoltaic System
Sung-Chan Rho and Shin-Il Lim*
Department of Electronics Engineering, Seokyeong University / Seoul, South Korea {scrho, silim}@skuniv.ac.kr
* Corresponding Author: Shin-Il Lim
Received May 15, 2015; Revised June 10, 2015; Accepted June 15, 2015; Published June 30, 2015
* Regular Paper
* Extended from a Conference: Preliminary results of this paper were presented at the IEIE & IEEE ICEIC 2015. This present
paper has been accepted by the editorial board through the regular reviewing process that confirms the original contribution.
Abstract: This paper provides the design techniques of a successive approximation register (SAR)
type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking
(DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a VCM-based
switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With
these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog
converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is
exploited with the dual sampling technique during top-plate sampling. Simulation results show that
the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious
free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with
bipolar CMOS LDMOD (BCDMOS) 0.35μm technology. Total power consumption is 115uW under a
supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is
32.68fJ/conversion-step.
Keywords: SAR ADC, Low switching energy, Photovoltaic system, Distributed MPPT
1. Introduction
Solar electricity is one of today’s prospective
renewable energy sources. However, the power-generating
efficiency is reduced by weather conditions and the
surrounding environment, such as shadow. To improve
efficiency of the photovoltaic (PV) module, a maximum
power point tracking (MPPT) control system is usually
applied.
Fig. 1 shows the structure of a photovoltaic system to
which a distributed MPPT (DMPPT) is applied [1]. To
apply MPPT control, an analog-to-digital converter (ADC)
and a DMPPT control block are designed inside the system
on chip (SoC). And a PV cell module, a boost DC-DC
converter and loads are outside the SoC [1]. The 12b ADC
receives single-ended analog voltage from the PV cell and
provides the corresponding digital information to the
DMPPT control circuits of the photovoltaic system.
In this paper, we focus on the design of this 12b
successive approximation register (SAR) ADC for
DMPPT control in a photovoltaic system, while
conventional MPPT uses an 8b ADC [1]. The proposed
ADC is optimized for performance in terms of power,
accuracy, and small area.
2. Proposed 12b SAR ADC Architecture
Fig. 2 shows a block diagram of the proposed 12b SAR
ADC. It has a synchronous main control block, a
comparator, a digital output buffer and a single-todifferential 10-bit DAC. To enhance the accuracy of the
ADC, a single-to-differential converted DAC is exploited
with a dual-sampling technique [2].
Both the top-plate sampling technique and VCM-based
switching technique are also applied to the 12b capacitor
digital-to-analog converter (CDAC). With these techniques,
we can implement a 12b SAR ADC with a 10b capacitor
array DAC. More details are described in Section 3.
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Rho et al.: Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
Fig. 1. Block diagram of a PV system.
Fig. 2. Block diagram of the proposed 12b SAR ADC.
3. Design of Proposed 12b DAC
Fig. 3(a) shows the conventional 12b DAC with
attenuation capacitor under bottom-plate sampling
techniques. This attenuation capacitor reduces the total
capacitor array, and hence, reduces the chip area
remarkably [7]. During the sampling periods, VIN is
sampled at all the bottom plates of capacitor arrays. In the
very first step during the holding and conversion periods,
for the most significant bit (MSB) decision, the 32C
capacitor is switched to VRT (or VRB), then the difference
of the VIN and one half of VRT (VRT/2) is compared. As
a result, the MSB is determined. After the MSB is
determined, the next (second) MSB is resolved by
switching the 16C capacitor to VRT (VRT/4). These
operations continue for 12 steps until the least significant
bit (LSB) is resolved. The total number in the conventional
capacitor array is 256Cs for differential operation.
Fig. 3(b) shows the proposed single-to-differential 12b
DAC by adopting a dual sampling technique that is
basically the same as a top-plate input sampling technique
in differential operation. To improve accuracy, the singleended input signal (PV voltage) is converted to a
differential signal by selectively sampling the single-ended
input signal of VIN. That is, for the upper capacitor array,
the analog single-ended input signal VIN is sampled at the
top plate of the capacitor array, and for the lower capacitor
array, the analog single-ended input signal VIN is sampled
at the bottom plate. This means that the plus (+) VIN
signal is sampled at the non-inverting input of the
comparator, and the minus (-) VIN signal is also sampled
at the inverting input of the comparator. With this dual
sampling technique, differential signal processing is
possible with the single input signal in this photovoltaic
system application. Since the differential VIN is applied to
the comparator, the MSB can be directly determined with
this differential sampled input signal. In this case, we do
not need to switch 32C to VRT (or VBT). This means that
the MSB can be determined without the 32C capacitor
array for the MSB in holding mode as with the
conventional design. The remaining bits can be resolved
from the second MSB by using the half of the capacitor
array in holding and conversion periods. This dual
sampling technique reduces the MSB capacitor array by
half. Total number in the capacitor array with this
sampling technique is 192Cs for differential operation.
Fig. 3(c) shows the proposed 12b DAC with 10b
capacitor array by adopting both the dual sampling
technique and the VCM-based switching technique [3]. By
switching the reference voltage on the last unit capacitor
between (VRT, VCM) instead of (VRT, VRB), additional
LSB comparison is allowed. The comparator can be
directly combined with this DAC output signal, and the
final digital code is generated. In this case, we do not need
additional lower capacitors for LSB as in the conventional
design. With this VCM-based switching technique in the
LSB decision, we can reduce the lower sub-capacitor array
by half. As mentioned earlier, we can reduce the MSB 32C
capacitors in the main array with the dual sampling
technique. And with this VCM-based LSB switching
technique, we can also reduce another 32C in the sub-array.
As a result, this VCM-based LSB switching technique,
together with aforementioned dual sampling technique,
allowed us to implement a 12-bit ADC with a 10-bit
capacitor array DAC as shown in Fig. 3(c). Total number
of the capacitor array with this VCM-based LSB switching
technique, together with the dual sampling technique, is
128Cs for differential operation. Compared to the
conventional design of Fig. 3(a), this technique reduces the
total DAC capacitor array by half.
Since the dual sampling technique and VCM-based LSB
switching technique reduces the capacitor array by two
times, these reduced capacitors in a DAC inherently reduce
the switching energy by two times. Moreover, we can save
more switching energy by applying top plate sampling and
also by adopting a proposed low switching energy
technique. Fig. 4(a) shows the conventional switching
process of a three-bit DAC as an example.
In the sampling periods, VIN is sampled at the bottom
plate of the capacitor arrays. During the first conversion
process in the holding periods, the MSB capacitors are
switched to VRT and other capacitors are connected to
VRB in the upper array of the DACP. And reverse
reference voltages are also connected in the lower array of
the DACN. In this case, all the capacitors are switched to
the reference voltage, and hence, consume the switching
power of 4CV2. Also, during the second and third
conversion processes in the holding period, this
conventional switching technique consumes more
switching energy, as shown Fig. 4(a).
191
IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
(a)
(a)
(b)
(b)
Fig. 4. (a) Conventional switching process with 3b DAC
example, (b) proposed low switching energy process
with 3b DAC example.
(c)
Fig. 3. (a) Conventional 12b differential DAC, (b) 12b
DAC with a dual sampling technique, (c) the proposed
12b DAC with 10b capacitor array by using a VCM-based
switching technique together with a dual sampling
technique.
Fig. 4(b) shows the process of the proposed low
switching energy technique with a three-bit DAC as a
conceptual example. If both VIP and VIN are sampled at
the top plate of each capacitor array, there we have zero
switching energy during the first conversion. But, due to
the single-to-differential operation in the sampling period
in this application, the VIN in DACN is not sampled at the
top-plate. This first conversion needs the switching energy
of 2 CV2 for the MSB decision in the first cycle. But for
the remaining LSB decisions, we need zero switching
energy in the second conversion cycle and 1/8CV2 in the
third conversion cycle, as shown Fig. 4(b).
Fig. 5 shows a circuit diagram of the dynamic
comparator that we used. It has a preamp followed by a
dynamic latch. The comparator was optimized to have low
noise and also to have high accuracy.
Fig. 5. Circuits of dynamic comparator.
4. Simulation Results and Performance
Summary
The proposed 12b SAR ADC was designed with
0.35μm bipolar CMOS LDMOD (BCDMOS) technology.
The fast Fourier transform (FFT) simulation results are
shown in Fig. 6 with an input signal of 14.3KHz and a
sampling frequency of 1.25MHz. The proposed ADC
achieves an SNDR of 70.75dB, an SFDR of 83.28dB, and
an ENOB of 11.46 bits. The core area, as shown in Fig. 7
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Rho et al.: Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
5. Conclusion
The 12-bit SAR ADC was designed for DMPPT
control in a photovoltaic system. Both a top-plate sampling
technique and a VCM-based switching technique are
applied to the 12b capacitor digital-to-analog converter.
With these techniques, we can implement a 12b SAR ADC
with a 10b capacitor array DAC. To enhance the accuracy
of the ADC, a single-to-differential converted DAC is
exploited with a dual sampling technique during top-plate
sampling. A low switching energy technique is also
applied to the capacitor DAC.
Fig. 6. FFT simulation results (4096 point).
Acknowledgement
This research was supported by the Ministry of Science,
ICT and Future Planning (MSIP), Korea, under the
Information Technology Research Center (ITRC) support
program (IITP-2015-H8501-15-1010) supervised by the
Institute for Information & Communications Technology
Promotion (IITP) and was also supported by the Technology
Innovation Program (10049009, Development of Main IPs for
IoT and Image Based Security Low-Power SoC) funded by
the Ministry of Trade, Industry & Energy (MOTIE), Korea.
References
Fig. 7. Chip layout (w/o pad).
Table 1. Performance Summary.
Parameters
Values
Process
BCDMOS 0.35μm
Resolution
12 bits
Power Supply
3.3V
Sampling Rate
1.25MHz
Input Signal Voltage Range
0 ~ 3.3V
Power Consumption
34.8μA (at 3.3V)
SNDR/SFDR
70.75dB / 83.28dB
ENOB
11.46 bits
FoM
32.68 fJ/conv
Layout Area
664μm * 933.5μm
is 600μm x 935.5μm, excluding pads. The power
consumes 115μW at a sampling frequency of 1.25MHz
under the supply voltage of 3.3V. And the figure of merit
(FoM) is 32.68fJ/conversion-step. We can further reduce
power consumption if we adopt asynchronous control. The
performance is summarized in Table 1.
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(CrossRef Link)
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[6] B. P. Ginsburg and A. P. Chandrakasan, "An EnergyEfficient Charge Recycling Approach for a SAR
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IEIE Transactions on Smart Processing and Computing, vol. 4, no. 3, June 2015
Sung-Chan Rho received a BSc from
the Department of Electronics Engineering at Seokyeong University,
Seoul, Korea, in 2015. Since 2015, he
has been in the master’s course at
Seokyeong University. His research
interests include analog and mixedmode IC design for biomedical and
sensor applications.
Shin-Il Lim received his BSc, MSc
and PhD in electronic engineering
from Sogang University, Seoul, Korea,
in 1980, 1983, and 1995, respectively.
He was with the Electronics and
Telecommunications Research Institute
(ETRI) from 1982 to 1991 as senior
technical staff. He also was with the
Korea Electronics Technology Institute (KETI) from 1991
to 1995 as a senior engineer. Since 1995, he has been with
Seokyeong University, Seoul, Korea, as a professor. His
research areas are in analog and mixed-mode circuits
design for communication, consumer, biomedical and
sensor applications. He was the TPC chair of ISOCC’2009
and also was the general chair of ISOCC’2011. And he
was the finance chair of ISCAS’2012.
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