IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
1047
Advanced Thin-Film Silicon-on-Sapphire
Technology: Microwave Circuit Applications
Robb A. Johnson, Member, IEEE, Paul R. de la Houssaye, Member, IEEE, Charles E. Chang, Member, IEEE,
Pin-Fan Chen, Student Member, IEEE, Michael E. Wood, Graham A. Garcia, Member, IEEE,
Isaac Lagnado, Life Member, IEEE, and Peter M. Asbeck, Member, IEEE
Abstract—This paper reviews the prospects of thin-film siliconon-sapphire (TFSOS) CMOS technology in microwave applications in the 1–5 GHz regime and beyond and presents the
first demonstration of microwave integrated circuits based on
this technology. MOSFET’s optimized for microwave use, with
0.5-m optically defined gate lengths and a T-gate structure,
have f t values of 25 GHz (14 GHz) and f max values of 66 GHz
(41 GHz) for n-channel (p-channel) devices and have noise figure
values below 1 dB at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET’s to date.
On-chip spiral inductors exhibit quality factors above ten. Circuit
performance compares favorably with that of other CMOS-based
technologies and approach performance levels similar to those
obtained by silicon bipolar technologies. The results demonstrate
the significant potential of this technology for microwave applications.
Index Terms— CMOSFET’s, microwave integrated circuits,
silicon-on-insulator technology, thin-film inductors, transceiver
I. INTRODUCTION
A
LTHOUGH the development of thin-film silicon-onsapphire (TFSOS) CMOS technology has been undertaken primarily for digital and analog applications, the technology has numerous advantages that make it very attractive
for microwave circuits. At the same time, the demand for
microwave circuits, at increasingly higher levels of integration,
has grown explosively with the recent deployment of mobile
wireless communication systems. In this paper, we discuss
the potential of TFSOS CMOS technology operating in the
microwave regime, and summarize a number of specific circuit
implementations that demonstrate this potential. We have fabricated and measured key microwave building block circuits,
including a low-noise amplifier, microwave switch, and mixer.
We show that the circuits perform significantly better than
comparable ones based on bulk CMOS, reach performance
Manuscript received June 2, 1997; revised November 4, 1997. The review
of this paper was arranged by Editor J. G. Fossum.
R. A. Johnson was with the Department of Electrical and Computer
Engineering, University of California at San Diego, La Jolla, CA 92093 USA.
He is now with IBM Microelectronics Division, Essex Junction, VT 05452
USA.
P. R. de la Houssaye, M. E. Wood, G. A. Garcia, and I. Lagnado are with
SPAWAR Systems Center, San Diego, CA 92152-7633 USA.
C. E. Chang was with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA. He
is now with Rockwell Science Center, Thousand Oaks, CA 91360 USA.
P.-F. Chen and P. M. Asbeck are with the Department of Electrical and
Computer Engineering, University of California at San Diego, La Jolla, CA
92093 USA.
Publisher Item Identifier S 0018-9383(98)02968-2.
levels comparable with Si bipolar (the current workhorse for
wireless system applications) and approach the realm of GaAs
MESFET-base circuits. The results point to a promising future
for SOI in this application area.
After a brief description of the status of current TFSOS
technology, we discuss the characteristics of our T-gate MOSFET’s. Next the characteristics of our spiral inductors are
shown and compared to inductors fabricated on bulk silicon.
Finally, the building block circuits for a 2.4 GHz transceiver
are discussed.
II. TECHNOLOGY CHARACTERISTICS
Silicon-on-sapphire has all the advantages of other SOI technologies as well as many others relevant to microwave circuits.
These include reduced self-heating effects (due to higher thermal conductivity, 0.46 W/cm K, of sapphire as compared to
SiO , 0.014 W/cm K), reduced device parasitic capacitances,
radiation hardness, reduction of latch-up in CMOS structures,
higher packing density, and improved isolation. TFSOS also
has lower minority carrier lifetimes ( 1 nS) that result in
higher source-drain breakdown voltage and reduced parasitic
bipolar gain. Another TFSOS characteristic to note is that the
silicon film is under compressive stress. This stress splits the
light and heavy hole valence bands leading to increased hole
mobilities over that of bulk silicon. At the same time, this
stress also causes lower electron mobilities as compared to
bulk [1]. This is similar to the effects seen in SiGe on Si [2].
As a result, n- and p-channel TFSOS MOSFET’s are more
closely matched than in other CMOS variants.
Sapphire, the single crystal form of alumina, a popular
microwave substrate, has been known for many decades to
have excellent dielectric properties. The dielectric constant, di,
electric loss tangent, and resistivity of sapphire are
at 3 GHz, and
cm. Hence, in
addition to the desirable traits of other SOI technologies, the
sapphire wafer makes an excellent microwave substrate for
passive elements such as transmission lines and inductors.
Despite the fact that the electron mobility in TFSOS is
typically less than in III–V technologies, TFSOS has the
advantage of complementary circuits due to its much higher
hole mobility. In addition, the availability of high levels of
integration and ease of manufacturability using the established
silicon infrastructure, makes TFSOS CMOS more desirable
than III–V technologies for combined microwave/digital apbit parallel multiplier with 0.75- m
plications. A
gate lengths and a 1 K SRAM with 1.25- m gate lengths
0018–9383/98$10.00  1998 IEEE
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
(a)
(a)
(b)
(b)
Fig. 1. I –V characteristics of (a) n-channel and (b) p-channel T-gate MOSFET’s with Lg = 0:5 m and Wg = 100 m.
Fig. 2. Microwave characteristics of (a) n-channel and (b) p-channel T-gate
MOSFET’s with Lg = 0:5 m and Wg = 100 m.
were fabricated in TFSOS and were reported by Offord
in 1992 [3]. The multiplier had a loaded gate delay of
243 pS at 5.0 V supply voltage. The SRAM exhibited an
access time of 20 nS. Sadana [4] has demonstrated 0.25- m
TFSOS devices with dc characteristics superior to devices
fabricated on other SOI technologies (SIMOX and BESOI).
These large circuits demonstrate the potential of combined
microwave/digital applications.
In order to realize microwave circuits with TFSOS CMOS,
it was necessary to modify the conventional “digital” FET to
realize a FET optimized for microwave applications. Second,
passive elements such as inductors and capacitors must be
developed and characterized.
A. Microwave Transistor
A transistor targeted for microwave applications differs
from a transistor targeted for digital applications in many
ways. Besides the high-speed requirement expressed as
and governed by gate length, microwave transistors require
high power gain expressed through the maximum frequency of
oscillation,
. Circuits operating at microwave frequencies
typically require
values three to four times greater than
the operating frequency. Additionally, microwave transistors
require low noise (of little significance in digital applications).
From the equations for
and Fukui’s noise figure [5] of a
transistor
, is easy to
is very important in designing
see that the gate resistance
a transistor for microwave circuit applications.
Our process uses a titanium salicide process in which the
source, drain and gate regions become silicided. The silicided
gate poly typically has a resistance of a few ohms per square,
which helps decrease the gate resistance but leads to values
still not low enough for microwave circuit applications. A
MOSFET with 0.5- m gate length and 50- m gate width
can have a gate resistance of a few hundred ohms [6]. By
incorporating a metal strap, or “T-gate,” over the optically
defined polysilicon gate, the gate resistance can be reduced to
a few Omega [7], [8].
The fully-depleted MOSFET’s were fabricated on 1000 Å
thick silicon films that underwent an implantation and solidphase epitaxial regrowth process to reduce defect and improve
crystal quality [9], [10]. The devices have optically defined
gate lengths of 0.5 ms (0.35 m effective gate lengths) and
have a 120 Å thick gate oxide. The processing and electrical
characteristics of the MOSFET’s have been discussed elsecharacteristics and microwave
where [7], [8]. Typical dc
characteristics are shown in Figs. 1 and 2, respectively. Both
n- and p-channel devices have as minimum noise figure below
values are above 60 GHz (30 GHz) for
1 dB at 2 GHz.
NMOS (PMOS) transistors.
JOHNSON et al.: ADVANCED THIN-FILM SILICON-ON-SAPPHIRE TECHNOLOGY
SUMMARY OF THE AC
AND
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TABLE I
NOISE PERFORMANCE OF OUR T-GATE MOSFET’s
Results of the microwave and noise performance are summarized in Table I. The metal T-gate dramatically increases
the performance of the MOSFET’s, which reaches the level
needed for microwave circuit applications. Moreover, the
fabrication process has not been significantly altered and can
readily be incorporated into any existing bulk or SOI process.
B. Spiral Inductors
Inductors are important elements of microwave circuits
used for impedance matching or filtering, which require high
self-resonant frequencies,
, and high quality factors, .
Planar inductors on silicon were investigated in the 1960’s
but it was concluded that use on silicon integrated circuits
was impractical [11]. In 1990, Nguyen and Meyer showed,
however, that inductors could be used in silicon IC’s [12]
which stirred many researchers to reinvestigate the potential of
fabricating inductors on bulk silicon substrates. Novel processing techniques such as deep trench etches [13], [14] and thick
gold metallization [15], [16] have recently been investigated.
Our inductors use a standard digital CMOS process with
aluminum metallization and rely only on the sapphire substrate
to improve their performance. This eliminates the need to
develop costly and less reliable process steps.
Circular spiral inductors with 5- m metal width and spacing
were fabricated using a double level metal process optimized
for digital applications. The inductors were processed on both
TFSOS and bulk silicon ( 8–10 cm) for comparison. For
the latter case, a 1.7- m thick SiO insulating layer was
deposited on top of the bulk silicon wafers before fabricating
was
the inductors. A thick metallization with 20 m
realized by stacking first (0.5- m TiW/Al/Ti) and second
(1.6- m TiW/Al/Ti) level metals.
The results of the inductor investigation have been reported
elsewhere [17] and are summarized here. Two-port s-parameter
measurements were made using an HP8510B network analyzer
from 0.5 to 20 GHz. The self-resonant frequency and peak
quality factor versus inductance for inductors on TFSOS and
bulk silicon are plotted in Fig. 3. The TFSOS inductors have
both higher self-resonant frequency and quality factor than
the bulk silicon inductors.
It is important to note that at low frequencies the quality
factor is limited by the metal resistance of the spiral and
the inductors on TFSOS and Si are comparable. However, at
higher frequencies, the is limited by the substrate losses and
the TFSOS inductors have a distinct performance advantage.
To achieve a higher , additional metallization layers can
be added or a lower resistance metal such as gold can be
used [5], [6]. Should even higher
be desired, e.g., for extremely sharp notch filters, high-temperature superconductors
can be used in conjunction with TFSOS. TFSOS has been
uniquely demonstrated to be monolithically integrable with
Fig. 3. Self-resonant frequency and peak quality factor for inductors on
TFSOS and bulk silicon.
Fig. 4. Schematic of the transmit/receive switch.
high-temperature superconductor devices and circuits, both on
the same sapphire substrate and operating at 77 K [18], [19].
In addition, performance of the TFSOS devices, especially
that of the p-channel, has been shown to greatly improve at
cryogenic temperatures [1].
Small signal modeling has shown that the capacitive coupling to ground and the resistive substrate lead to the decreased
performance of the bulk silicon inductors [17]. The thickness
of the oxide below the inductors fabricated in bulk silicon is
on the order of what would be found in an SOI process such
as BESOI or SIMOX. Hence, unless the SOI wafer utilizes a
high resistivity substrate, inductors fabricated on SOI would
be expected to have the same results as the ones fabricated on
bulk silicon presented here.
III. CIRCUITS
To explore the potential of the above devices in microwave
circuits, basic building blocks of a 2.4 GHz transmitterreceiver (transceiver) were designed and fabricated. These
blocks include a transmit/receive switch, mixer, and low-noise
amplifier.
A. Transmit/Receive Switch
A transmit/receive (TR) switch is needed to connect the
antenna to the receiver chain (receive mode) or the transmit
chain (transmit mode). It is important for the switch to have
very low insertion loss to not degrade signal-to-noise ratio
prior to the low-noise amplifier on the receive side, or reduce
efficiency on the transmit side. Non-linearity must be small
to accommodate large output power. At the same time, it is
important for the switch to have high isolation from one side
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
Fig. 5. Photograph of the fabricated transmit/receive switch (die size: 1:2 mm
2 0 55 mm).
:
Fig. 7. Schematic of the mixer.
Fig. 6. Measured insertion loss and isolation of the transmit/receive switch.
to the other. TFSOS is very well suited to this combination
of requirements.
Fig. 4 shows the circuit schematic of the SPDT switch
which uses a combination of a series and shunt switch nMOSFET’s in each leg. DC voltages of 3.3 V are used to
control the switch state. 1 K resistors were inserted in the
gate lines to minimize signal injection through the gate-source
capacitance. These resistors help reduce insertion loss but also
cause a slight reduction in isolation. The circuit was laid out
for on-wafer probing and is shown in Fig. 5. Chip dimensions
mm
mm.
were
Circuit simulations were carried out using HP/EEsof’s LIBRA to determine the optimal gate width (300 ms) of
the MOSFET’s. The circuit was left unmatched to retain
broadband operation and to save circuit area that would have
been used by on-chip inductors; despite this, it attains high
performance.
The switch was measured on an HP8510 network analyzer
from 1 to 5 GHz with an input power of 0 dBm. Fig. 6 shows
the insertion loss and the isolation of the switch as a function of
frequency. At 2.4 GHz, the TFSOS switch had an insertion loss
around 1.7 dB and an isolation greater than 30 dB. At 5 GHz
the insertion loss dropped to only 2.0 dB and the isolation
remained greater than 25 dB. The insertion loss and isolation of
the same switch fabricated on SIMOX were 4.9 and 36 dB at
2.4 GHz and considerably worse, 6.2 and 33 dB, at 5 GHz. The
higher insertion loss of the SIMOX switch can be explained
by the presence of the conducting substrate. Signals couple
to the substrate through the metal traces and through FET to
substrate capacitances leading to an increase in the insertion
loss for the SIMOX switch. Similarly, this coupling helps to
slightly improve the isolation of the SIMOX switch over that
of the TFSOS switch.
The TFSOS switch also displays excellent linearity
and power handling capability. Two tone measurements
GHz,
GHz) were carried out to
(
determine the linearity of the switch. The input referred third
order intercept point (IIP3) was 18 dBm. In bulk CMOS,
forward biased drain-substrate junctions limit the voltage
excursion and thus the microwave power.
While other technologies such as GaAs offer improved
switch performance with insertion losses on the order of 1 dB
or lower, they cannot be readily integrated with low-power
VLSI circuits such as the case with TFSOS. This integration
can make up for individual circuit performance by eliminating
other losses resulting from multi-chip packages.
JOHNSON et al.: ADVANCED THIN-FILM SILICON-ON-SAPPHIRE TECHNOLOGY
Fig. 8. Photograph of the fabricated mixer (die size: 1:2 mm
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2 0 875 mm).
:
TABLE II
SUMMARY OF RECENT CMOS MIXER RESULTS
Fig. 9. Measured two-tone power transfer characteristics of the mixer.
B. Mixer
Another important transceiver component is the mixer used
in up and down conversion of the carrier frequency (RF) to
the intermediate frequency (IF). Mixers must have good local
oscillator (LO) and RF isolation, as well as high IP3 and
low-noise figure. For our work we chose an all n-FET mixer
topology shown in Fig. 7. As opposed to a Gilbert cell mixer
with high gain and usually poor IP3, our design targets high
IP3 with little or no gain. This is a viable tradeoff in that it
is easier to increase gain in the receiver chain (such as in the
next power amplifier) than to increase IP3. For good isolation,
we chose a doubly-balanced mixer configuration. The mixer
uses a single transistor with LO fed into the gate and RF fed
Fig. 10. Schematic of the single-stage low-noise amplifier.
into the source. A photograph of the mixer is shown in Fig. 8.
mm
mm.
Chip dimensions are
GHz,
GHz) power
Two-tone (
transfer characteristics for the mixer are shown in Fig. 9.
The LO frequency and power were 2.15 GHz and 0.7 dBm,
respectively; the IF was at 250 MHz. At representative bias
V with
mA (including output
conditions of
) of 8.4 mW.
source followers), the dc power dissipation (
At the same time the fundamental power ( ) remains linear
over a wide range of input power with a high input IP3 of
5 dBm. The mixer has about 5 dB conversion loss consistent
with its design to favor high IP3 at the expense of gain.
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Fig. 11.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
Photograph of the fabricated low-noise amplifier (die size: 1:3 mm
2 0 95 mm).
:
Through the use of TFSOS technology, the nonlinearity of
the substrate coupling and body effect can be greatly reduced.
This prevents LO and RF signals from feeding through to the
IF. Further, due to the high
of our PMOS devices, current
reuse schemes [20] can be used to increase mixer performance.
A summary of recently reported CMOS mixers are shown
in Table II. Our mixer compares favorably, particularly with
respect to its high IIP3 to dc power ratio and high frequency
of operation. As mentioned before, the mixer was designed
for high IP3. Consequently, the mixer has a conversion loss
of 5 dBm. Due to measurement problems, the noise figure of
the mixer was not obtained.
C. Low Noise Amplifier
The low-noise amplifier (LNA) is a critical element of the
receive path which must have very low noise as well as
high gain and output IP3 (OIP3). Fig. 10 shows the circuit
schematic of our LNA. Spiral inductors and MIM capacitors
were used to match the FET’s to the minimum noise figure at
. Circuit parameters were:
m,
m,
nH,
nH,
nH,
nH,
pF,
pF, and
pF. The circuit
was laid out for on-wafer probing and is shown in Fig. 11.
Dimensions of the chip are
mm
mm.
Fig. 12. Power transfer characteristics of the LNA.
The LNA was operated at
,
V. The
dc current consumption at low input power levels is 8.8 mA
(while it rises to 9.9 mA for an input power corresponding to
the 1-dB compression point.) This corresponds to an average
power dissipation of 14 mW. This bias condition gave the optimal dc power consumption, gain and noise figure. Using the
spiral inductors, the LNA is well matched for gain (10 dB) and
GHz,
noise figure (2.8 dB) at 2.4 GHz. Two-tone (
JOHNSON et al.: ADVANCED THIN-FILM SILICON-ON-SAPPHIRE TECHNOLOGY
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TABLE III
SUMMARY OF RECENT CMOS LNA RESULTS
[8]
[9]
[10]
GHz) linearity measurements of the LNA were
performed and are shown in Fig. 12. The output referred 1 dB
compression point and third-order intercept (OIP3) are 4 and
14 dBm, respectively.
These results represent the highest frequency CMOS lownoise amplifier reported to date. Table III summarizes recently
reported CMOS LNA results. The noise characteristics of this
LNA are of the order of those required for numerous wireless
systems and on the same order as obtained with silicon bipolar
circuits. On the basis of simulation, we believe that even lower
noise figure would be possible if the metal thickness used
to realize the on-chip inductors was greater. The excellent
linearity observed may be attributed to the good turn-off and
low output conductance of the TFSOS FET’s, together with
the absence of the body effect. The combination of low-noise
figure, high OIP3 and low-power consumption is particularly
desirable for wireless receiver circuits.
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
IV. CONCLUSION
Silicon-on-sapphire CMOS is very well suited for circuits
operating in the microwave regime. The combination of highperformance MOSFET’s and inductors make possible the
integration of an RF front end and VLSI digital circuits
on the same substrate. This combination, with performance
unachievable in bulk silicon technologies, can reduce cost and
increase circuit performance of chipsets targeted at wireless
communication applications. These first pass circuits represent
some of the first CMOS-based circuits operating above 2 GHz.
With further circuit optimization and scaling of device geometries, TFSOS should be able to achieve RF circuits operating
in the 10 GHz regime and beyond.
[19]
[20]
[21]
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Garcia, and I. Lagnado, “Microwave characterization of submicron nand p-channel MOSFET’s fabricated with thin-film silicon-on-sapphire,”
in 1994 MTT-S Int. Microwave Symp. Dig., vol. 1, pp. 405–408.
[7] P. R. de la Houssaye, C. E. Chang, B. Offord, G. Imthurn, R. A.
Johnson, P. M. Asbeck, G. A. Garcia, and I. Lagnado, “Microwave
Robb A. Johnson (S’90–M’97) received the B.S.
degree in 1992, the M.S. degree in 1993, and the
Ph.D. degree in 1997, all in electrical engineering,
from the University of California at San Diego,
La Jolla. His dissertation was on technology development and circuit design with silicon-on-sapphire
MOSFET’s for microwave circuit applications. He
has worked on device characterization and highspeed circuit design in AlGaAs/GaAs and lnP-based
HBT technologies.
He is currently with IBM Microelectronics Division, Burlington, VT, working on process development and device characterization with SiGe BiCMOS technology.
1054
Paul R. de la Houssaye (S’83–M’88) received the
B.S. degree in applied physics from the California
Institute of Technology, Pasadena, in 1980, and the
M.S. and Ph.D. degrees in applied physics from
Stanford University, Stanford, CA, in 1982 and
1988, respectively. Following work at Advanced
Micro Devices in Sunnyvale, CA, in device/EPROM
simulation, his graduate career included work in
both silicon and III–V device fabrication and characterization culminating in a thesis involving 50-nm
gate length III–V MODFET’s. He then went on
to do post-doctoral work with the Laboratoire de Microstructures et de
Microelectronique at the Centre National de la Recherché Scientifique (CNRS
L2M), Bagneux, France, working with high aspect ratio nanostructures and
resonant tunneling devices.
He then joined SPAWAR Systems Center, San Diego, CA [formerly Naval
Electronics Laboratory Center (NELC), Naval Ocean Systems Center (NOSC),
and Naval Command Control and Ocean Surveillance Center (NCCOSC
RDTE DIV or NRaD)], where he initially worked with activation of boron
in natural diamond samples. For the past six years, his work has been mostly
in the fabrication and characterization of high-speed, low-noise FET’s in
ultra-thin-film silicon-on-sapphire and in the monolithic integration of hightemperature superconductors and semiconductor devices and circuits. He has
authored or coauthored more than 25 publications in the open literature and
presently holds one U.S. patent.
Dr. de la Houssaye is a member of the American Vacuum Society, the
Electrochemical Society, and Sigma Xi.
Charles E. Chang (S’92–M’96) was born in San
Gabriel, CA, on January 17, 1969. He received the
B.S. degree in 1991, the M.S. degree in 1993, and
the Ph.D. degree in 1995, all in electrical engineering, from the University of California at San
Diego, La Jolla. His graduate work focused on lowpower/high-speed HBI device design and MMIC
development as well as SOS CMOS microwave
device development and RF circuit design.
Since 1995, he has been a Senior Member of
the Technical Staff at the Rockwell Science Center,
Thousand Oaks, CA, focusing on the design of 10 Gb/s lightwave IC’s and
systems. He is also involved in HBT modeling and the design of high-speed
data acquisition systems for satellite applications.
Pin-Fan Chen (S’93) received the B.S. degree
in electrical engineering from the University
of California, Los Angeles, in 1992 and the
M.S. degree in electrical engineering from the
University of California at San Diego, La Jolla,
in 1993, where he is currently pursuing the Ph.D.
degree.
His
present
research
interests
include
GalnP/GaAs DHBT device physics’ high-power
added efficiency switching microwave power
amplifiers, and CMOS RF power amplifiers. He
has also designed resonant tunneling diode logic circuits.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
Michael E. Wood received the B.S. degree in
physics in 1977 and the Ph.D. degree in physics
in 1988, both from the University of California,
Davis. He served as an officer in the Army Corps
of Engineers after receiving the B.S. degree.
Since 1988, he has worked in the Integrated
Circuit Research and Fabrication Branch of
SPAWAR Systems Center, San Diego, CA [formerly
Naval Electronics Laboratory Center (NELC),
Naval Ocean Systems Center (NOSC), and Naval
Command Control and Ocean Surveillance Center
(NCCOSC RDTE DIV or NRaD)], in the fields of semiconductor device
physics, radiation effects, device modeling, and semiconductor processing. He
has nine years experience in the design, fabrication, and testing of submicron
devices in fully-depleted and partially-depleted thin-film silicon-on-insulator
(SOI) technology. He has published a number of technical articles in the field
of semiconductor devices.
Graham A. Garcia (M’87) received the B.A. degree in physics from the University of California,
Berkeley, in 1969, and the Ph.D. degree in solidstate physics from the University of Washington,
Seattle, in 1976.
Following post-doctoral work in the application
of synchrotron X-radiation to studies of solids at
high pressure, in 1978 he joined the Naval Ocean
Systems Center (NOSC), San Diego, CA, where
he has been involved with the characterization of
silicon-on-insulator (SOI) materials and the development of ultrathin SOI devices and IC fabrication processes. Since 1992, he
has headed the Integrated Circuit Fabrication Facility at NOSC’s successor
organizations, the Naval Command, Control, and Ocean Surveillance Center
and presently SPAWAR Systems Center, San Diego. He has published more
than 50 articles, and holds 11 U.S. patents.
Isaac Lagnado (M’59–LM’96), photograph and biography not available at
the time of publication.
Peter M. Asbeck (M’75) received the B.S. and Ph.D. degrees from the
Department of Electrical Engineering, Massachusetts Institute of Technology,
Cambridge, in 1969 and 1975, respectively.
He was with Sarnoff Research Center, Princeton, NJ, and Phillips Laboratory, Briarcliff Manor, NY, where he worked in the areas of quantum
electronics and GaAlAs/GaAs laser physics and applications. In 1978, he
joined Rockwell International Science Center, Thousand Oaks, CA, where he
was involved in the development of high-speed devices and circuits based on
III–V compounds and heterojunctions. He investigated the influence of GaAs
substrates on the behavior of field-effect transistors. He participated in the
effort to develop heterojunction bipolar transistors based on GaAlAs/GaAs
and InAlAs/InGaAs materials systems, and has contributed in the areas of
physics, fabrication, and circuit applications of these devices. In 1991, he
joined the University of California at San Diego, La Jolla, as Professor
in the Department of Electrical and Computer Engineering. His research
interests include the development of high-speed heterojunction transistors and
optoelectronic devices.