IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 2, MARCH 1999
381
An Instantaneous Reactive Volt–Ampere
Compensator and Harmonic Suppressor System
Kishore Chatterjee, B. G. Fernandes, and Gopal K. Dubey, Senior Member, IEEE
Abstract—A novel control method for a reactive volt–ampere
compensator and harmonic suppressor system is proposed. It
operates without sensing the reactive volt–ampere demand and
nonlinearities present in the load. The compensation process is
instantaneous, which is achieved without employing any complicated and involved control logic. The compensator is operated in
cycle-by-cycle reference-current-controlled mode to achieve the
instantaneous compensating feature. A mathematical model of
the scheme is developed. Detailed analysis and simulation results
are presented. A laboratory prototype of the compensator is
developed to validate the results.
Index Terms—Active power filter, instantaneous compensation,
load compensation, power factor correction, SCSVC, SVC.
I. INTRODUCTION
O
VER THE YEARS, there has been a continuous proliferation of nonlinear type of loads due to the intensive use
of power electronic control in all branches of industry as well
as by the general consumers of electric energy. As a result, the
utility supplying these loads has to provide large reactive volt
amperes. Also, it gets polluted by the harmonics generated
by the load. The punitive tariffs levied by utilities against
excessive vars and the threat of stricter harmonic standards
have led to extensive research in the field of load compensation. The basic requirements of the compensation process
involve precise and continuous reactive volt–ampere control
with fast response time, reduced inrush currents, avoidance
of resonances created by peripheral low-frequency current
sources, and the on-line elimination of the effect of the load
harmonics. To satisfy the above criteria, the traditional methods of compensation consisting of switched capacitor or fixed
capacitor and phase-controlled reactor coupled with passive
filters have been increasingly replaced by new approaches
utilizing the concept of synchronous link converters [1]. This
new class of compensators, which has generated tremendous
interest among the researchers, is known by several terminologies such as var generators [2], advanced static var generators
[3], synchronous solid-state var compensators [4], pulsewidth
modulation (PWM) inverter var compensators [5], etc. The
Manuscript received November 7, 1996; revised August 25, 1997. Recommended by Associate Editor, P. Enjeti.
K. Chatterjee and B. G. Fernandes are with the Department of Electrical
Engineering, Indian Institute of Technology, Bombay, India.
G. K. Dubey is with the Department of Electrical Engineering, Indian
Institute of Technology, Kanpur 208016, India (e-mail: gdubey@iitk.ernet.in).
Publisher Item Identifier S 0885-8993(99)01839-6.
authors here will call this class of var compensators as selfcommutated static var compensators (SCSVC). When SCSVC
is utilized for harmonic compensation, it is known as an active
power filter [6]–[10] or power line conditioner [21]. Several
topologies of SCSVC and active power filters are reported in
the literature, but most of them have noninstantaneous transient
response [3]–[14]. The schemes based on indirect current
control technique have a poor transient response [4], [5], [13].
Schemes utilizing current control principle either use: 1) a
reactive volt–ampere calculator to set the compensator current
reference or 2) error between the dc-link voltage reference
and the sensed dc-link capacitor voltage to set the amplitude
of the source current reference. In type 1), the presence of
the reactive volt–ampere calculator generates a delay in the
compensation process. In type 2), a low-pass filter is required
to eliminate ripple from the sensed dc-link voltage. Inclusion
of this filter introduces finite delay in the control structure.
This coupled with the inertia presented by the dc-link capacitor
while absorbing or releasing energy introduces a cumulative
delay of at least two–three cycles in the dc-link capacitor
voltage response. As a result, the amplitude of the source
current reference has a low-frequency distortion and a dc
component as long as the transient persists. Hence, the current
drawn from the source during transients is not in phase with the
utility voltage and not free from low-order harmonics. Other
schemes having instantaneous compensation feature employ
complicated and an involved control strategy [15], [16]. But
these schemes can only be applied for three-phase case.
The present paper proposes a new technique of compensation of var and load harmonics for low- and medium-power
applications using an insulated gate bipolar transistor (IGBT)
as the switching device. The novel features of the present
technique are as follows.
1) The compensation process is instantaneous.
2) The control logic and the associated hardware are simple, thereby enhancing the system reliability.
3) The compensation is achieved without sensing either the
load reactive volt–ampere demand or the load harmonics.
case
4) Unlike [15] and [16], it can be used for the
as well.
The scheme is developed both for single- and three-phase
systems, and the performance is found to be satisfactory. A
mathematical model of the proposed compensation process
is developed and analyzed. A detailed simulation program
of the scheme is developed to predict its performance for
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or
(3)
where
From Fig. 1,
amplitude of the inphase component
of the load current;
amplitude of the quadrature component of the load current.
, therefore
(a)
(4)
where
(4), if
is the amplitude of the current reference. Now, in
is made equal to
, is obtained as
(5)
(b)
Fig. 1. (a) 1
0 and (b) 3 0 compensator.
different operating conditions. To demonstrate the viability
of the scheme, a laboratory prototype is developed, and
experimental results are presented.
II. OPERATING PRINCIPLE
The power circuit configurations for the single- and threephase compensators are shown in Fig. 1. It is operated in
a controlled current boost-type converter mode. The current
is made to follow a sinusoidal
drawn from the utility
within a fixed hysteresis band. The
reference current
width of the hysteresis window determines source current
profile, its harmonic spectrum, and switching frequency of
the devices. The dc-link capacitor voltage is kept constant
throughout the operating range of the compensator. In the
and
will increase
case of single phase, turning on
, whereas turning on
and
will decrease it [17]. For
the three-phase case, three current references inphase with
the respective phase to neutral voltages are taken, and each
phase of the compensator is controlled independently [18]. To
increase the current of a particular phase, the lower switch of
the compensator associated with that particular phase, i.e.,
or
is turned on while to decrease the current the upper
or
of the respective compensator phase
switch, i.e.,
is turned on.
A. Estimation of the Reference Current
The technique to determine the reference current is explained for the single-phase compensator. The same approach
is applicable for the three-phase case.
be given by
Let the utility voltage
(1)
Consider a linear load drawing a current
utility voltage by an angle . Therefore
, which lags the
(2)
From the above development, it can be inferred that if the
source current is made to follow a current reference which is
equal to the inphase component of load current and inphase
with the utility voltage, the compensator current is equal and
opposite to that of the quadrature component of the load
current. As in the present scheme, the reactive volt–ampere
requirement of the load is not sensed, the magnitude of the
inphase component of the load current is to be determined
indirectly. Since the average power consumed by the compensator is zero, the average dc-link capacitor voltage remains
constant. However, there will be losses taking place in the
compensator which will be replenished at the expense of the
stored energy of the capacitor. This results in reduction of the
capacitor voltage. To maintain the capacitor voltage, the losses
of the compensator has to be supplied from the utility. This
. Moreover, if
is achieved by choosing a proper value of
the load reactive volt–ampere increases, the compensator loss
increases and the capacitor voltage drops further. A similar
situation arises if there is an increase in the real component of
the load current. When there is a decrease in the reactive and/or
real component of the load current, the capacitor voltage rises.
Thus, by monitoring the average capacitor voltage a suitable
can be chosen.
value of
As the source current is made to follow the sinusoidal
reference current within a small hysteresis band, the improvement in the harmonic spectrum of is significant. This
improvement is again achieved without sensing or estimating
49 , which
the load harmonics. The higher order harmonics
are present in the source current, will get eliminated by the
short circuit impedance of the utility.
III. CONTROL STRATEGY
It is well known that in the case of
synchronous
link converters, the dc-link capacitor voltage is superimposed
case, although
with second harmonic ripple [1]. In the
the magnitude of sixth harmonic dc-link voltage ripple is
insignificant while compensating linear loads, it increases
while compensating nonlinear loads. If the dc-link voltage
is sensed and compared with the reference dc voltage to
control the amplitude of the reference current, then source
current will also have second or sixth harmonic distortion. To
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CHATTERJEE et al.: VOLT–AMPERE COMPENSATOR AND HARMONIC SUPPRESSOR SYSTEM
Fig. 2. DC-link voltage profile for 1
383
0 and 3 0 topology.
Fig. 4. Control block diagram of the current reference generator.
Fig. 3. Control block diagram of the 1
0 topology.
overcome this difficulty, the dc-link voltage is sensed and the
harmonics present in it are filtered out. The inclusion of the
filter introduces a delay in the compensation process and the
transient response becomes poor. Here, a novel control strategy
is proposed to make the compensation process instantaneous.
Fig. 2 shows the steady-state voltage profile of the dc-link
capacitor along with the source voltage waveform for both
single- and three-phase topologies. It can be noted from the
figure that the magnitude of the capacitor voltage remains
constant at all zero-crossing instants of the source voltage.
Instead of continuous monitoring, if the dc-link voltage is
can be avoided
sampled only at these instants, distortion in
without employing the filter.
The basic control block diagram of the proposed scheme
for single-phase case is shown in Fig. 3. Latch-1 and Latch-2
are made transparent only at the positive going zero crossings
of the source voltage. This ensures that the error information which is to be passed to the proportional–integral
(PI) controller and the processed error to be passed to the
reference current generator block is made available only at
the positive going zero-crossing instants. This implies that the
set at the beginning of a cycle
reference current level
is maintained constant throughout the cycle. The reference
produces
current generator based on the information of
which is inphase with the
the required reference current
and based
utility voltage. The comparator compares with
on this error information switching pattern of the compensator
is decided so that is made to follow
within a hysteresis
band.
is maintained constant throughout
Since the amplitude of
a sampled cycle of the utility voltage, the source current is
maintained distortion free and inphase with the utility voltage
both during steady state and transient operation. Hence, the
compensation process is instantaneous. The dc-link capacitor
is specially designed for this purpose so that the dc-link
voltage does not fall below the source current controllability
limit. However, as the source current is forced to follow the
reference within a hysteresis band some finite delay is still
expected. The authors have found through extensive simulation
studies that even in the worst case of transients this delay
comes out to be less than 50 s, i.e., less than 1 of the
power cycle, which is insignificant for all practical purpose.
The fact that this insignificant delay does not affect the
instantaneous compensating feature is corroborated in [15],
where the compensator current is made to track the synthesized
reference current by bang–bang control.
For the three-phase case, the positive zero-going instant of
any one of the phases is taken as the sampling instant. The
current reference generator produces three current references
and
which are inphase with the respective
.
phase to neutral voltages and having an equal amplitude
The other features of the controller are same as that of the
single-phase topology.
A. Current Reference Generator
The internal block diagram of the current reference gener8-b EPROM is used to
ator is shown in Fig. 4. A 1024
store the sinusoidal current reference. It is being addressed by
a 10-b counter. The counter counts the VCO pulse output of
the PLL, the frequency of which is set to 1024 times the utility
frequency. The output of the EPROM which is the digitized
version of the sine wave is fed to the DAC for converting it
to the analog sine wave. The amplitude of the sine wave is set
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 2, MARCH 1999
Similarly, rms compensator current is written as
(9)
where
rms inphase component of the compensator current;
rms quadrature component of the compensator current.
The rms source current is then
Fig. 5. Single line diagram of the compensator connected to the utility.
by the AI input of the DAC which is connected to the output
latch of the PI controller of Fig. 3.
As the reference is synthesized from a previously programmed EPROM and not directly derived from the utility, the
presence of any distortion in the utility voltage or occasional
dips in it will not have any effect on the reference and, hence,
on the source current wave shape.
For three-phase cases, three such units are used. The AI
inputs of the three units are together connected to the output
latch of the PI controller. Outputs of the three DAC’s provide
the reference currents for the three phases.
But
, therefore
(10)
Power input to the compensator is given by
(11)
where
for single-phase topology and
for three-phase topology.
Power loss in the resistance is given by
IV. MATHEMATICAL MODEL
The rate at which the dc-link capacitor voltage responds
to the changes in the reference source current is analyzed
here. Although the dynamic response of the dc-link voltage
has no effect on the instantaneous compensating feature of
the scheme, a mathematical model is required for stability
analysis and, hence, for determining the parameters of the PI
controller. The principle of average power balance is used to
determine the approximate model of the compensator. This is
valid since the magnitude of the current reference does not
change within a cycle of the utility voltage. The mathematical
model is derived based on the following assumptions.
1) The utility voltages are balanced and contain no harmonics.
2) Only the fundamental components of currents are considered as the harmonic components do not affect the
average power balance expressions.
3) All losses of the system are lumped and represented by
an equivalent resistance connected in series with the
line inductor .
4) Ripple in the dc-link capacitor voltage is neglected.
From Fig. 5
(6)
(7)
The load current is assumed to be lagging the utility voltage
can be written as
by an angle . The rms load current
(8)
(12)
Average rate of change of energy associated with the inductor
Since
is constant for a particular operating point
(13)
Average rate at which energy is being absorbed by the capacitor
(14)
is the instantaneous dc-link voltage. Equating
where
average rate of change of energy associated with ac link and
and
is obtained for a
dc link, the relation between
particular operating point, which is given by
(15)
is applied in the inphase comIf a small perturbation
about a steady-state
ponent of the compensator current,
, the average dc-link voltage will also
operating point
about its steady-state
get perturbed by a small amount
. Putting
operating point
where
rms inphase component of the load current;
rms quadrature component of the load current.
and
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CHATTERJEE et al.: VOLT–AMPERE COMPENSATOR AND HARMONIC SUPPRESSOR SYSTEM
385
Fig. 6. Transfer function model of the open-loop plant.
in (15), the small-signal perturbed equation neglecting the
higher order differential terms is obtained as
Fig. 7. Comparison of output response of the mathematical model to that of
the actual model for single-phase topology.
(16)
The steady-state equation from (15) is
(17)
Subtracting (17) from (16), the linear relationship between
and
is obtained as
(18)
The transfer function model of the compensator for a
particular operating point is obtained from (18) as
Fig. 8. Comparison of output response of the mathematical model to that of
the actual model for three-phase topology.
For this case,
and
are obtained as
(19)
where
The block diagram of the proposed open-loop compensator is
shown in Fig. 6. The sampled data model of the compensator
is obtained as
(20)
A realistic system is chosen to simulate the performance
characteristics of the proposed compensating scheme. The
system specifications are as follows:
230 V;
20 A (rated max);
20 A (rated max);
500 V;
2000 F;
0.5 ;
0.25 A (the chosen operating point).
For a unit step input of
, the response of
derived from the mathematical model and that obtained by
simulating the actual system for single- and three-phase cases
are shown in Figs. 7 and 8, respectively. The closeness of the
two responses shows that the mathematical model developed
is in close agreement with that of the actual system.
The closed-loop configuration of the scheme is shown in
Fig. 9. The PI controller is designed to obtain acceptable gain
margin of 5 dB and phase margin of 45 , respectively. The
and
are found to be
parameters of the PI controller
0.37 and 6.0, respectively, for single-phase topology and 0.14
and 4.5, respectively, for three-phase topology. The openloop frequency response curves of the single- and three-phase
compensators along with the above mentioned PI controllers
are shown in Figs. 10 and 11, respectively.
V. DESIGN
OF
DC-LINK CAPACITOR
The value of the dc-link capacitor is chosen to restrict the
ripple of the dc-link voltage within a permissible limit. The
ripple is proportional to the magnitude of reactive volt ampere
to be compensated. Therefore, the capacitor value is decided
by the maximum var to be handled. In the present scheme, as
the link voltage is controlled in a discrete mode, the capacitor
may have to supply the real power demand of the load for
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Fig. 9. Transfer function model of the compensated closed-loop plant.
(a)
(a)
(b)
(b)
Fig. 10. Open-loop frequency response of the single-phase compensator with
a PI controller in the feedforward path. (a) Gain versus frequency plot and
(b) phase versus frequency plot.
one cycle of the utility voltage in the worst case of transient.
Hence, the capacitor design is based on the maximum real
power rating of the load. The design equation based on this
principle is derived as follows.
W and the
Let the peak power rating of the load be
V. Therefore, the maximum energy
rms utility voltage be
that the capacitor has to supply in the worst case of transient
is given by
(21)
Let the minimum allowable dc-link voltage be
fore
. There(22)
is the set dc-link voltage and , the value of the
where
dc-link capacitor. Equating (21) and (22), is obtained as
(23)
where
(24)
The value of is judiciously chosen so that the source current
controllability is ascertained at all operating points.
Fig. 11. Open-loop frequency response of the three-phase compensator with
a PI controller in the feedforward path. (a) Gain versus frequency plot and
(b) phase versus frequency plot.
VI. SIMULATED RESULTS
Simulation studies are carried out to predict the performance
of the proposed SCSVC. A dedicated computer program
is employed for the purpose and simulated waveforms are
presented next for the cases of linear and nonlinear load
compensation. In all the cases studied, the width of the
hysteresis window is maintained at 0.5 A and the upper limit
of the average switch frequency is found to be 5 KHz.
A. Simulated Waveforms for Linear Load Compensation
1) Single-Phase Topology: In order to validate the transient
KVA
as well as the steady-state behavior, a
load is initially connected. At 61 ms, i.e., just after the commencement of the fourth cycle, the load is abruptly changed
KVA. The waveforms of the source current,
to
load current, dc-link voltage along with the utility voltage are
shown in Fig. 12. The source current is near sinusoidal and is
inphase with the utility voltage. The displacement factor and
power factor of the source current are found to be 0.999 985
and 0.999 907, respectively. The harmonic spectrum of the
fifth cycle of the source current is shown in Fig. 13. Although
the dc-link voltage transients take some time to settle down
after the disturbance, the source power factor is maintained
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387
(a)
(a)
(b)
(b)
(c)
Fig. 12. Simulation waveforms of the single-phase topology for an increment
in the real component of the load current. (a) DC-link voltage, (b) source
voltage and source current, and (c) load current.
Fig. 13.
Fig. 12.
Harmonic spectrum of the fifth cycle of the source current of
unity throughout this entire period. This implies that the
compensation process is instantaneous
Similar waveforms for change of load from
KVA to
KVA are shown in Fig. 14.
Displacement factor and power factor of the source current
are found to be 0.999 97 and 0.999 192, respectively.
2) Three-Phase Topology: Similar tests are carried out with
the three-phase compensator. At 61 ms, i.e., just after the
(c)
Fig. 14. Simulation waveforms of the single-phase topology for an increment
in the reactive component of the load current. (a) DC-link voltage, (b) source
voltage and source current, and (c) load current.
beginning of the fourth cycle of the phase-A source voltage,
KVA load is abruptly changed to
a
KVA. The waveforms of the utility voltages, source
and load currents of the three phases and the dc-link capacitor
voltage are shown in Fig. 15. The source currents are near
sinusoidal and inphase with the respective phase voltages. The
transient period in the dc-link voltage has no effect on the
phase relationship between the source currents and the utility
voltages; they are always maintained inphase with each other
even during the transients. Similar waveforms for a change of
KVA to
KVA are
load from
shown in Fig. 16.
B. Simulated Waveforms for Nonlinear Load Compensation
The nonlinear load is simulated by a phase-controlled thyristorized converter operating at a phase delay of 45 and
supplying 10 A of dc current. The waveforms of the compensation process for single-phase case is shown in Fig. 17.
Although the load current is quasi-square wave having a
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(a)
(a)
(b)
(b)
(c)
(c)
Fig. 16. Simulation waveforms of the three-phase topology for an increment
in the reactive component of the load current. (a) DC-link voltage, (b) phase-A
source voltage and source current, (c) phase-A load current.
(d)
the source current is shown in Fig. 19. The displacement factor
and power factor of the source current is found to be 0.999 98
and 0.999 84, respectively.
The waveforms of the three-phase compensation process is
diode bridge supplying 10
shown in Fig. 20. Here, a
A of dc current is taken as the load. The displacement factor
and power factor of the load current are 0.9107 and 0.8783,
respectively, whereas the displacement factor and power factor
of the source current are found to be 0.9999 and 0.9988,
respectively.
VII. EXPERIMENTAL RESULTS
(e)
Fig. 15. Simulation waveforms of the three-phase topology for an increment
in the real component of the load current. (a) DC-link voltage, (b) phase-A
source voltage and source current, (c) phase-A load current, (d) phase-B source
voltage and source current, and (e) phase-B load current.
displacement factor of 0.586 60 and power factor of 0.544 52,
the source current is found to be near sinusoidal. The harmonic
spectrum of the load current is shown in Fig. 18 and that of
A scaled-down laboratory prototype is developed to validate
the simulation results of single- and three-phase topologies of
the proposed compensation schemes. Oscillogram records of
the various waveforms of the single-phase topology are shown
in Figs. 21–25. Fig. 21 shows the steady-state performance of
compensator while compensating a lagging load
the
A. The harmonic spectrum of the
current of
compensated source current is shown in Fig. 22. It can be
inferred that low-order harmonics are not introduced and the
magnitude of the higher order harmonics are less than 1% of
the fundamental. This is achieved at a fairly low switching
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(a)
389
(a)
(b)
(b)
(c)
(c)
Fig. 17. Simulation waveforms of the single-phase topology compensating
a nonlinear load. (a) DC-link voltage, (b) source voltage and source current,
and (c) load current.
Fig. 18.
Fig. 20. Simulation waveforms of the three-phase topology compensating a
nonlinear load. (a) DC-link voltage, (b) phase-A source voltage and source
current, and (c) phase-A load current.
Harmonic spectrum of the nonlinear load current of Fig. 17.
Fig. 21. Steady-state performance: Tr1: dc-link voltage (50 V/div); Tr2:
utility voltage (60 V/div); Tr3: source current (4 A/div); and Tr4: load current
(5 A/div) time scale = 5 ms/div.
Fig. 19.
Harmonic spectrum of the compensated source current of Fig. 17.
frequency of 2 KHz. Fig. 23 shows the compensation of a
nonlinear load. The load in this case is ac–dc fully controlled
thyristor bridge having a mismatch of firing angle delay
between the positive and negative half cycles so that the
current drawn contains a dc component in addition to the
harmonics. Fig. 24 shows the transient behavior when an
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390
Fig. 22.
KHz.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 2, MARCH 1999
Harmonic spectrum of the source current. Frequency range: 0–2.5
Fig. 23. Steady-state performance: Tr1: dc-link voltage (50 V/div); Tr2:
utility voltage (60 V/cm); Tr3: source current (4 A/div); and Tr4: nonlinear
load current (1 A/div) time scale = 5 ms/div.
Fig. 24. Transient performance for increment in load: Tr1: dc-link voltage
(15 V/div) and Tr2: source current (4 A/div). Time scale = 0:1 s/div.
incremental step change of
to
A is introduced in the load current, while Fig. 25 shows the
utility voltage and source current along with the load current
during the same condition. The source current is found to
be inphase with the utility voltage even during the transients
thereby validating the instantaneous compensation feature of
the scheme.
Oscillogram records of the three-phase topology are shown
in Figs. 26–32. Figs. 26 shows the steady-state behavior of
Fig. 25. Transient performance for increment in load: Tr1: utility voltage
(30 V/div) and source current (4 A/div) and Tr2: load current (4 A/div). Time
scale = 20 ms/div.
Fig. 26. Steady-state performance: Tr1: phase-A utility voltage (120 V/div);
Tr2: phase-A source current (10 A/div); Tr3: phase-A load current (10 A/div);
and Tr4: phase-B source current (10 A/div); time scale = 5 ms/div.
Fig. 27. Steady-state performance: Tr1: phase-A utility voltage (120 V/div);
Tr2: phase-A source current (10 A/div); Tr3: phase-A nonlinear load current
(10 A/div); and Tr4: phase-B source current (10 A/div); time scale = 5 ms/div.
the
compensator compensating a linear lagging load
A/phase. Fig. 27 shows the waveforms
current of
of nonlinear load compensation. The load considered is a
diode bridge rectifier supplying a resistive load. Fig. 28 shows
the spectrum of the nonlinear load current while Fig. 29 shows
the spectrum of the compensated phase-A source current.
Steady-state behavior for compensating an unbalanced
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Fig. 28. Harmonic spectrum of the phase-A nonlinear load current. Frequency range: 0–5 KHz.
391
Fig. 31. Transient performance for increment in dc voltage reference: Tr1:
dc-link voltage (44 V/div) and Tr2: phase-A source current (4 A/div). Time
scale = 0:1 s/div.
Fig. 29. Harmonic spectrum of the phase-A source current. Frequency range:
0–5 KHz.
Fig. 32. Transient performance for increment in dc voltage reference: Tr1:
phase-A utility voltage (30 V/div) and phase-A source current (10 A/div)
and Tr2: phase-B utility voltage (30 V/div) and phase-B source current (10
A/div). Time scale = 20 ms/div.
and source current of phase B for the same condition of
transience. Here again the instantaneous compensation feature
is observed.
VIII. CONCLUSIONS
Fig. 30. Compensating an unbalanced load: Tr1: phase-A source current (10
A/div); Tr2: phase-A load current (10 A/div); Tr3: phase-B source current (10
A/div); and Tr4: phase-B load current (10 A/div). Time scale = 5 ms/div.
load is shown in Fig. 30. Here, the phase-A load current is
reduced to 50% to that of the phase-B and phase-C load
currents. It is observed that the source currents are balanced.
compensator,
For studying the transient behavior of the
step change in the reference dc-link voltage is introduced
instead of changing the load. Fig. 31 shows the dc-link voltage
and phase-A source current when an incremental step change
of 220–260 V is introduced. Fig. 32 depicts the utility voltage
and source current of phase-A along with the utility voltage
A new reactive volt–ampere compensator and harmonic
suppressor system is proposed for low- and medium-power
applications. The proposed technique makes the compensation
process instantaneous. This feature is achieved using simplified
control technique thereby enhancing the system reliability.
Mathematical model of the scheme is derived. Simulation
results supported by experimental validations are presented.
REFERENCES
[1] V. R. Kanetkar, M. S. Dawande, and G. K. Dubey, “Recent advances
in synchronous link converters,” in Power Electronics and Drives, G.
K. Dubey and C. R. Kasarbada, Eds. India: IETE, 1994.
[2] L. Gyugi, “Reactive power generation and control by thyristor circuits,”
IEEE Trans. Ind. Applicat., vol. IA-15, pp. 521–532, Sept./Oct. 1979.
[3] C. W. Edwards, K. E. Mattern, E. J. Stacey, P. R. Nannery, and J.
Gubernick, “Analysis and design of a advanced static var generator
employing GTO thyristors,” IEEE Trans. Power Delivery, vol. 3, pp.
1622–1627, Oct. 1988.
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 31, 2008 at 03:53 from IEEE Xplore. Restrictions apply.
392
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 2, MARCH 1999
[4] L. T. Moran, P. D. Ziogas, and G. Joos, “Analysis and design of a
three-phase synchronous solid-state var compensator,” IEEE Trans. Ind.
Applicat., vol. 25, pp. 598–608, July/Aug. 1989.
[5] G. Joos, L. T. Moran, and P. D. Ziogas, “Performance analysis of a
PWM inverter VAR compensator,” IEEE Trans. Power Electron., vol.
6, pp. 380–391, July 1991.
[6] J. Nastran, R. Cajhen, M. Seliger, and P. Jereb, “Active power filter for
nonlinear ac loads,” IEEE Trans. Power Electron., vol. 9, pp. 92–96,
Jan. 1994.
[7] H. Akagi, A. Nabae, and S. Atoh, “Control strategy of active power
filters using multiple voltage-source PWM converters,” IEEE Trans. Ind.
Applicat., vol. IA-22, pp. 460–465, May/June 1986.
[8] H. Akagi, Y. Tsukamoto, and A. Nabae, “Analysis and design of an
active power filter using quad-series voltage source PWM converters,”
IEEE Trans. Ind. Applicat., vol. 26, pp. 93–98, Jan./Feb. 1990.
[9] F. J. Peng, H. Akagi, and A. Nabae, “A study of active power
filters using quad-series voltage-source PWM converters for harmonic
compensation,” IEEE Trans. Power Electron., vol. 5, pp. 9–15, Jan.
1990.
[10] H. L. Jou, J. C. Wu, and H. Y. Chu, “New single phase active power
filter,” Proc. Inst. Elect. Eng., vol. 141, no. 3, pp. 129–134, 1994.
[11] S. Deb, B. W. Sherman, and R. Hoft, “Resonant converter power line
conditioner: Design and evaluation,” IEEE Trans. Ind. Applicat., vol.
29, pp. 500–509, May/June 1993.
[12] J. D. Van Wyk, D. A. Marshall, and S. Boshoff, “Simulation and
experimental study of a reactively loaded PWM converter as fast
source of reactive power,” IEEE Trans. Ind. Applicat., vol. IA-22, pp.
1082–1090, Nov./Dec. 1986.
[13] L. T. Moran, P. D. Ziogas, and G. Joos, “Analysis and design of a novel
3 solid-state power factor compensator and harmonic suppressor
system,” IEEE Trans. Ind. Applicat., vol. 25, pp. 609–619, July/Aug.
1991.
[14]
, “A solid-state high-performance reactive-power compensator,”
IEEE Trans. Ind. Applicat., vol. 29, pp. 969–978, Sept./Oct. 1993.
[15] H. Akagi, Y. Kanazawa, and A. Nabae, “Instantaneous reactive power
compensators comprising switching devices without energy storage
components,” IEEE Trans. Ind. Applicat., vol. IA-20, pp. 625–630,
May/June 1984.
[16] J. L. Willems, “A new interpretation of the Akagi-Nabae power components for nonsinusoidal three-phase situations,” IEEE Trans. Instrum.
Meas., vol. 41, pp. 523–527, Aug. 1992.
[17] O. Stihi and B. T. Ooi, “A single-phase controlled-current PWM
rectifier,” IEEE Trans. Power Electron., vol. 3, pp. 453–459, Oct. 1988.
[18] B. T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, “A threephase controlled-current PWM converter with leading power factor,”
IEEE Trans. Ind. Applicat., vol. IA-23, pp. 78–84, Jan./Feb. 1987.
0
B. G. Fernandes was born in Mangalore, India, on
May 17, 1962. He received the B.Tech. degree in
1984 from Mysore University, India, the M.Tech.
degree in 1989 from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree in 1993
from the Indian Institute of Technology, Bombay,
India.
He was with M/S Development Consultant Ltd.
from 1984 to 1987. From 1993 to 1997, he was with
the Department of Electrical Engineering, Indian
Institute of Technology, Kanpur, as an Assistant
Professor. Currently, he is with the Department of Electrical Engineering,
Indian Institute of Technology, Bombay. His current research interests are
in PMSM drives, vector-controlled drives, quasi-resonant dc-link converter
topologies, modern var compensators, and active power filters.
Gopal K. Dubey (SM’83) was born on November
17, 1939. He received the B.E. degree (with honors)
from Jabalpur University, India, in 1963 and the
M.Tech. degree in drives and controls and Ph.D.
degree from the Indian Institute of Technology,
Bombay, India, in 1965 and 1972, respectively.
He was an Assistant Professor at the Indian
Institute of Technology, Bombay, until 1977 and has
been Professor at the Indian Institute of Technology,
Kanpur, since 1978. He was an Honorary Visiting
Research Fellow and Commonwealth Scholar at the
University of Bradford, U.K., from 1974 to 1975 and a Visiting Professor at the
University of British Columbia, Vancouver, Canada, from 1983 to 1984 and
at the Virginia Polytechnic Institute and State University, Blacksburg, from
1984 to 1985. He was a Senior Visiting Fellow at the National University
of Singapore in 1995. His fields of interest include electrical drives, power
electronics, control systems, and engineering education. He has written several
books including: Power Semiconductor Controlled Drives (Englewood Cliffs,
NJ: Prentice-Hall, 1989), Thyristorized Power Controllers (New Delhi: Wiley
Eastern, 1986), and Fundamentals of Electrical Drives (New Delhi: Narosa,
1994). He edited Power Electronics and Drives (New Delhi: Tata–McGrawHill, 1993) and has published 150 research papers. He is an Honorary Editor
of the IETE Journal of Research.
Dr. Dubey received the Bimal Bose Award of IETE in 1990 for excellence
in power electronics. He is a Fellow of the IETE, Institution of Engineers, and
Indian National Academy of Engineering. He was Chairman of the IEEE UP
Subsection and then Section for five years (1989–1993). He is an Associate
Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.
Kishore Chatterjee was born in Calcutta, India, on
July 20, 1967. He received the B.E. and M.E. (power
electronics) degrees from M.A.C.T., Bhopal, India,
and Bengal Engineering College, India, in 1990 and
1992, respectively. In 1998, he received the Ph.D.
degree in power electronics from the Indian Institute
of Technology, Kanpur, India.
From 1997 to 1998, he was a Senior Project Associate at the Indian Institute of Technology, Kanpur,
where he was involved with a project on power
factor correction and active power filtering, which
was being sponsored by the Central Board of Irrigation and Power, India.
Since December 1998, he has been an Assistant Professor in the Department
of Electrical Engineering, Indian Institute of Technology, Bombay. His current
research interests are modern var compensators, active power filters, utilityfriendly converter topologies, and S.R.M. drives.
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