Proceedings of the 14th International Middle East Power Systems Conference (MEPCON’10), Cairo University, Egypt, December 19-21, 2010, Paper ID 115.
Firing Approach for Higher Levels of Diode Clamped
Multi-Level Inverters
Mohammed El Gamal
SUMED Co., Alex., Egypt
m_sumed@yahoo.com
Ahmed Lotfy
AAST&MT, Egypt
alotfy@aast.edu
G. E. M. Ali
Tanta University, Egypt
and the difficulty associated with controlling their voltage
level.
1.2 Diode clamped multilevel inverters
Abstract - For Diode Clamped Multi-Level Inverters “DCMLI”
with higher than three levels, the commonly applied space vector
pulse width modulation gets more complicated as the inverter
levels increase. In this paper an easy to implement procedure is
proposed for generating PWM firing signals for higher level
DCMLI. The performance of the proposed procedure is modeled
in PSCAD-EMTDC environment for various modulation indices
with respect to voltage waveforms and total harmonic distortion.
The last and most common multilevel converter family is the
diode clamped multilevel inverter (DCMLI). The converter
topology, theory of operation and traditional firing instances
based on the space vector modulation approach (SVM) are
clarified in [12-16]. SVM depends on creating a number of
space vectors that increases linearly with the number of levels
such that the number of vectors is equal to the number of
levels raised to power three. The firing depends on selecting
certain vectors relevant to the required modulation index to be
fired consecutively with calculated on/off time intervals.
Several control techniques were proposed for this type of
inverters [17-21]. Diode clamped multilevel inverters are
found in several applications like induction motor drives [22],
dynamic voltage restorers [23], unified power flow controllers
[24] and static synchronous compensator [25].
However, the implementation of the space vector modulation
for a multilevel inverter is complicated. The complexity is due
to the difficulty of determining the location of the reference
vector, the calculation of on-times, the determination and
selection of switching states and the existence of many
redundant switching vectors as the number of levels increase.
For an m-level diode clamped inverter there are (m)3
switching vectors. The number of switching vectors for the
five and seven levels inverters is thus 125 and 343
respectively.
In this paper a generalized approach for constructing the
gating signals for the power electronic switching devices of an
m-level diode clamped multilevel inverter is proposed rather
than the complicated space vector modulation technique. This
approach consists of eleven steps; the first four steps are the
coarse tuning for the firing angles of each device in phase leg
A of the inverter. The fifth step is like a fine tuning to the final
firing angles. Steps from six to nine are precautions and facts
to be considered for the ON and OFF instants of all the
switching devices of the m-level inverter. Step 10 is the
creation of firing angles of phases B and C. The eleventh step
is concerned with how the pulse width modulation PWM is
implemented in such an inverter.
1. INTRODUCTION
1.1 Multilevel inverters
Multilevel converter topologies are used for static power
conversion in medium and high voltage systems. These
topologies use series connected semiconductor devices to
block the higher voltage levels involved. By precisely
controlling the modulation process, these converters can attain
higher voltage capability with substantially reduced output
harmonic distortion, and reduced electromagnetic interference
emission even at relatively low switching rates. At present
three major converter families exist; flying capacitor, cascaded
multilevel inverter and diode clamped multilevel inverter as
depicted in [1, 2].
As for cascaded multilevel inverters they are implemented
through the series connection of single-phase modular power
bridges as shown in [3]. Higher number of voltage levels or
over-destination operation is also used in cascaded multilevel
inverters [4]. They are applied for high-voltage, high-power
applications, such as flexible ac transmission systems
(FACTS) including static VAR generation (SVG), power-line
conditioning, series compensation, phase shifting, voltage
balancing and photovoltaic utility systems interfacing [5].
Several control techniques applied to the multilevel cascaded
inverter are depicted in [6, 7]. The deficiency of the cascaded
multilevel inverters arises from being inconvenient in the back
to back configuration besides the requirement for using
separate DC source for each module.
Flying capacitor multilevel inverters (FCMLI) have been used
for distribution shunt compensation systems called distribution
static compensators (DSTATCOM) [8], and transmission
shunt and series compensation systems like static
compensators (STATCOM) and static synchronous series
compensators (SSSC) [9]. Control techniques applied to flying
capacitor inverters are shown in [10, 11]. Nevertheless, their
application was limited due to the numerous used capacitors
2. PROPOSED APPROACH
Step 1 - For an m-level inverter there is a number of 2(m-1)
switching devices in one leg.
50
Such that
Step 2 - At any time there are (m-1) consecutively connected
devices that are ON at any instant of time.
Step 3 - There will be (2m-1) switching states in one cycle.
Step 4 – “Coarse tuning”; the 360 degrees comprising one
cycle will be divided equally by (2m-2) switching states, but
state “1” will take only half the degrees with the other half
given to state “(2m-1)”.
Applying the above mentioned procedure to construct higher
levels (above 3), results in elimination of some levels
comprising the line voltage. For such a step, the switching
instants and the duration of conduction for each upper leg
device of a 7_level DCMLI will be as shown in table I.
Vm= Vdc1 + Vdc2 + …. + Vdc(m-1).
Æ4
After applying step 5 the exact firing instants for the upper leg
switching devices are shown in table II.
Table II Switching instants and duration of upper leg
devices by applying step 5.
Upper leg device
Table I Switching instants and conduction duration of upper leg
devices by applying step 4.
Upper leg
device
Switching and duration in degrees
a1
From
163.8
To
180
Duration
16.2
a2
135.18
224.64
89.46
a3
104.22
254.52
150.3
a4
75.07
284.22
209.15
a5
45.27
315.7
270
a6
14.4
344.52
330.12
Switching and duration in degrees
a1
From
147.96
To
211.86
Duration
63.9
a2
120.24
240.68
120.44
a3
100.8
258.68
157.88
a4
78.68
280.8
202.12
a5
59.65
30033
240.68
a6
31.89
328.1
296.21
Figure2. Line voltage waveform by fine tuning
The line to line voltage waveform is shown in figure [2]. It is
clear that the voltage steps are 13 steps.
Step 6 - The firing pattern of the switching devices in one leg
will be such that the ON time of the top-most device in a leg’s
upper half will be equal to the OFF time of the top-most
device in the same leg lower half, and the ON time of the next
top device in the same leg upper half will be equal to the OFF
time of the next top device in the leg lower half and so on.
Step 7- For an odd level inverter there is an even number of
switching devices in the upper and lower halves of one leg (m
– 1). The first top (m – 1)/2 devices in the upper half leg and
the last (m – 1)/2 devices in the lower half leg will conduct for
less than a complete half cycle. And the next (m – 1)/2 devices
in the upper half leg and the first (m – 1)/2 devices in the
lower half leg will conduct for longer than half a cycle.
Step 8- For an even level inverter there is an odd number of
switching devices in each half leg. The first (m – 2)/2 devices
in the upper half leg and the last (m – 2)/2 devices in the lower
half leg will conduct for less than a complete half cycle and
the last (m – 2)/2 devices in the upper half leg and the first (m
– 2)/2 devices in the lower half leg will conduct for more than
Figure1. Line voltage waveform by coarse tuning
The resulting line to line voltage waveform is shown in figure
[1]. It is clear that there are only 5 voltage steps.
Step 5 – “Fine tuning” The exact firing instances of the
switching devices will be derived in such a way that the
fundamental component of the phase voltage with respect to
the common node of one leg of the DCMLI will be a pure
sinusoidal waveform shifted to the positive side so that the
peak to peak value of the inverter phase voltage with respect
to the common node is equal to the sum of all the DC
voltages, and the shift herein will be half this amount. This
idea is demonstrated by the following equations (1-4):
Va =(Vm/2) sin ( ωt – п/2) + Vm/2 Æ 1
Vb =(Vm/2) sin (ωt + 5п/6) + Vm/2 Æ 2
Æ3
Vab =( Vm ) sin (ωt – п/3)
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half a cycle. And only the middle device in the upper and
lower half legs that is centered at (m/2) will conduct for
exactly a complete half cycle.
Step 9- In the selection of switching devices of a diode
clamped multilevel inverter, the above mentioned rule of
switching periods of the devices should be considered to allow
use of lower ON time switching losses devices instead of over
rating almost half the devices in the inverter when selecting all
the devices of the inverter with the same rating.
Step 10- The firing signals of the similar devices existing in
phases B and C will be displaced from those in phase A by
120 degrees and 240 degrees consecutively.
Step 11- To control the output voltage of the inverter, the
pulse width modulation technique will be applied such that the
ON times will be achieved as mentioned in the proposed
approach and the OFF times of the PWM will be achieved by
firing all the devices in the lower half leg and inhibiting the
firing signals of all the upper half switches.
3. VALIDATION OF PROPOSED APPROACH
3.1 Seven level diode clamped multilevel inverter
To clarify the approach, the 7-level diode clamped inverter
shown in figure [3] will be considered. There are 6 DC
sources, 30 clamping diodes and 36 switching devices (IGBT),
12 devices for each leg (phase). The upper six devices "a1" to
"a6" are complementary to the lower six devices "ac1" to
"ac6". The firing signals for the switching devices of the upper
half of phase leg “A” are depicted in figure [4].
Figure3. Seven-level diode clamped inverter leg.
Figure4. Firing signals for leg “A” upper half
3.2 Test circuit
52
The proposed approach is tested using PSCAD. Figure [5]
shows a seven-level diode clamped inverter module connected
to six external 50 kV DC sources. The three phase output of
the inverter is connected to a star resistive load of 1000 ohms
per phase.
4.2 Harmonic distortion
The total harmonic distortion of the line to line voltage
waveform with modulation index of one is 0.39 %. Figure [7]
shows the total harmonic distortion “THD” versus the
modulation index “m”. It is evident that the total harmonic
distortion does not exceed 0.9 % at very low modulation index
of 10 %. Figure [8] show the line to line voltage wave form at
m = 10%. Figures [9], [10] show the line voltage harmonic
spectrum at modulation indices of 1 and 10% respectively.
THD Ver sus modulat ion index
THD
3
2.5
2
1.5
1
0.5
0
M odul a t i on I nde x
Figure5. Test case circuit of a 7_level inverter
4. TEST RSULTS
Figure7. THD versus modulation index.
4.1 Voltage waveforms
As stated before, the proposed approach assumes that the
phase voltage to ground is a shifted sine wave with a peak-topeak voltage value of the sum of the total DC voltage sources
which is 30 kV in the present case, and the resulting waveform
has seven steps. Figure [6] shows the line-to-line voltage
waveform and its fundamental value, and the resulting
waveform is a thirteen steps waveform.
Figure8. Line to line voltage waveform at m = 10 %
Line voltage Harmonic Spectrum at Modulation Index = 1
RMS voltage
20
RMS voltage
18
16
14
12
10
8
6
4
2
0
1
2
3
4
5
6
7
8
Harm onic No.
Figure6. Line to line voltage waveform.
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9
10
11
12
13
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Figure9. Line voltage harmonics at modulation index of 1.
Line voltage Harmonic Spectrum at Modulation Index = 0.1
RMS voltage
1.6
1.4
RMS voltage
1.2
1
0.8
0.6
0.4
0.2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Harm onic No.
Figure10. Line voltage harmonics at modulation index of 0.1
5. CONCLUSION
A simple approach is proposed for gating the switching
devices of higher levels of voltage source inverters. This
approach was found to be easier to implement compared to the
space vector modulation technique. The resulting voltage
waveforms and the associated total harmonic distortion were
both within acceptable limits. The burden of dealing with so
many switching vectors as the case of SVM was alleviated.
Furthermore, the switching losses are significantly decreased.
Over-rating of switching devices is minimized by applying the
proposed approach; enabling significant cost reduction.
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