International Conference on Innovations in Electrical and Electronics Engineering (ICIEE'2012) Oct. 6-7, 2012 Dubai (UAE)
DC Link Capacitors Voltage Balancing in
Diode-Clamped Multilevel Inverter
Ali Ajami and Hossein Shokri
The above mentioned features are obtained when the
voltage divisions on the capacitors under different working
conditions are equal. Non-uniform voltage on the capacitors
can be reduced the quality of inverter output voltage [7]. Main
problem of DCMC is unbalanced charging of capacitors in
different operating points. The following methods are used to
overcome the unbalanced charging of capacitors voltage:
1- Reform and changing the switching pattern and
controlling of switches [3-10].
2 - Installation of capacitor voltage balancing circuits on the
DC side of the inverter.
The first solution is preferable in terms of cost and reduces
the complexity of system and additional circuits and increases
the flexibility of the circuit.
Increasing switching frequency in conventional choppers
causes to reduction of output ripple, size and weight of circuit.
But Increasing switching frequency has some problem such
as:
1- High stress on switches [7].
2- Increasing the Electromagnetic interference (EMI) [1-4].
3- Increasing the switching losses [7].
In this paper a novel chopper circuit is proposed to
overcome the voltage unbalance problems in capacitors of a
DCMC. In comparison with conventional choppers, it requires
less number of switches. Also, switching frequency and stress
on the switches are reduced and all mentioned problems are
solved without increasing the circuit size and weight.
Simulation results carried out by MATLAB/Simulink in
different operating conditions are presented to verify and
validate features of presented topology.
Abstract—In all multilevel topology with several DC link, the
voltage balancing problem of DC capacitors is a key problem. This
paper proposes a new topology of chopper circuit for dc capacitor
voltage balancing in diode clamped multilevel inverters (DCMLI). In
the presented topology the number of switches is reduced respect to
other proposed topology in literatures. Suggested topology is modular
and has high reliability. Based on presented control system for
chopper switches, only one switch is turn on at each time. Therefore
the conduction and switching losses of chopper system are reduced.
The presented simulation results show fast dynamic response of
suggested chopper and reduction the voltage stress on its switches.
Computer
aided
simulations
are
performed
through
MATLAB/Simulink software. The simulations results are presented
to verify the performance of proposed chopper circuit and its control
system for DC capacitor voltage balancing in diode clamped
multilevel inverter.
Keywords— Chopper, Capacitor voltage balancing, Diode
clamped inverter, H-bridge.
I. INTRODUCTION
I
N recent years, multilevel inverters have presented an
important development to reach high power with increasing
voltage levels. the multilevel converter present great
advantage compared with conventional two level converters
such as ; high power quality of wave forms, low switching
losses, high voltage capability, low electromagnetic
compatibility (EMC), etc [1, 2]. Multilevel converters can be
divided into diode clamped multilevel converter (DCMC),
flying capacitor multilevel converter (FCMC), and cascaded
multilevel converter (CMC) with separate DC sources [3, 4].
Recently, attention has been paid to multilevel inverters for
medium-voltage and high-power applications such as
STATCOM, SSSC, UPFC, high voltage direct current
transmission as well as SVC applications, etc. [5, 6]. The
DCMC some features as below:
1- The dc capacitors can be easily pre-charged
2- The control of switches is very simple.
3- The protection of this inverter circuit is less complex
than other inverter [8- 9].
II. PROCEDURE FOR PAPER SUBMISSION
A single phase of five levels DCMC is considered here and
its circuit is shown in Fig.1(a).Fig.1(b)and1(c)show
conventional chopper and three level flying capacitor based
chopper circuit for capacitor voltage balancing, respectively.
Fig.1(b) the inverter side DC link includes capacitors C1-C4
which the voltage of each capacitor must be equal to V dc / 4.
With considering the point n as neutral reference, the
inverter output voltages can be expressed as Table 1[7, 8].
In the Table 1, state 1 means switch is on and state 0 means
switch is off. When currents i2 and i4 have a non-zero average
value, DC link Capacitors of DCMC will be suffer imbalanced
voltage [9-10]. To avoid this phenomenon, the presented
chopper circuits in Fig.1 (b) and 1 (c) are discussed in [7].
Both chopper in Fig.1 (b) and 1 (c) consist two separate
Ali Ajami is with Azarbaijan Shahid Madani University, Tabriz, Iran
(e-mail: Ajami@azaruniv.edu).
Hossein Shokri is MSC student in Azarbaijan Shahid Madani University,
Tabriz, Iran (e-mail: mailto:hossein_shokri64_07@yahoo.com).
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International Conference on Innovations in Electrical and Electronics Engineering (ICIEE'2012) Oct. 6-7, 2012 Dubai (UAE)
III. PROPOSED CHOPPER CIRCUIT
parts. It should be noted that the resistances R1 and R2 in
Fig.1 (b) represent the resistance of the corresponding
inductors and capacitors Cf1, Cf2 in Fig.1(c) are called
suspension capacitance that these suspension capacitances are
keeping the voltage stress of switches on V dc /4.
C1
Vdc
S1
D1
S2
D2
S3
D3
S4
D4
R L
S11
C3
D21
S31
D31
S41
D41
S1
D2
S2
D3
L2
𝑉𝑑𝑑
R3
S2
D2
i1
n
S3
D3
C3
S4
D4
i3
A. Performance of proposed chopper in different modes
The main objective of proposed chopper is capacitors
charging. Fig. 3 shows the paths of current flow in different
modes. According to Fig. 3, the first charging priority is with
capacitor C1 and then C2, C3 and C4 are charged,
respectively.
With these priorities as circuit strain function when every
capacitor charging in himself lawful band and it capacitor via
switch in the parallel branches issue the certain path (For
example, capacitor C1 switches S2) and the next capacitor
starts to charge up, and this procedure until all the capacitors
in Range considered to be charged, it will continue.
Assume ago startup the circuit all of the capacitor consist of
zero primary voltage and all of the switch are no connected,
then in the T = 0 (at start-up circuit), switch S 1 is connected
since V c1 is zero (V c1 =0), with connecting the switch S 1 the
capacitor C 1 to be charged to the capacitor C 2 and the same
procedure will continue up until the next capacitors are
charged (C 3 -C 4 ).
Because all diodes in this circuit are directly Bias (D 1 -D 4 ),
so if C 1 or any of the capacitors have extra energy can be this
extra charge through the diodes transfer to the next capacitors.
It should be noted that the resistors R1 = R2 = R3 = R4 in fig4
(a) represent the winding resistance of corresponding
inductors L1-L4.
With note the up detail in each section of circuit function
alone one switch is on, only when C4 start to charge the two
switches S3 and S4 in the period will be on simultaneously.
Switching states of suggested chopper are given in Table 2.
In this table terms "1" and "0" mean that switch is turned on
and off, respectively.
C3
i4
C4
Fig.1(b) conventional chopper
S1
D1
C1
D2
R1 L1
S2
𝐶𝑓1
𝐶𝑓2
S3
D3
S4
D4
S5
D5
S6
D6 R2 L2
S7
S8
C2
n
D7
D8
i1
i2
C3
i3
C4
i4
L4
Fig 2. The proposed chopper scheme
L2
R2
C2
C4
i2
C2
L3
S4
R4
D1
C1
R1 L1
L1
C1
Fig.1(a) One phase leg of a five level diode-clamped inverter
S1
D1
R1
R2
S3
D11
S21
C4
this paper a novel chopper circuit based on parallel switches
for capacitors voltage balancing is presented. The presented
chopper can be used in DCMC and is shown in
Fig. 2. The proposed new multi-level chopper has the
benefits of conventional and flying capacitor choppers that
were described in the previous section. Also, it can partially
overcome to the problems of previous mentioned choppers.
Fig.1(c) Flying capacitor chopper
TABLE I
SINGLE PHASE FIVE LEVEL DCMC SWITCHING SCHEME
V an
S1
S2
S3
S4
S 11
S 22
S 33
S 44
V dc /2
1
1
1
1
0
0
0
0
V dc /4
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
-V dc /4
0
0
0
1
1
1
1
1
-V dc /2
0
0
0
0
1
1
1
1
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International Conference on Innovations in Electrical and Electronics Engineering (ICIEE'2012) Oct. 6-7, 2012 Dubai (UAE)
TABLE II
SWITCHING SCHEME FOR FOUR LEVEL CHOPPER
State
no.
1
2
3
4
5
𝑉𝑑1 …𝑉𝑑4
𝑉𝑑1 …𝑉𝑑4 < 𝑉𝑟𝑒𝑓 + 𝐻𝐵
𝑉𝑑1 ≥ 𝑉𝑟𝑒𝑓 + 𝐻𝐵
𝑉𝑑2 …𝑉𝑑4 < 𝑉𝑟𝑒𝑓 - 𝐻𝐵
𝑉𝑑1 …𝑉𝑑2 ≥ 𝑉𝑟𝑒𝑓 + 𝐻𝐵
𝑉𝑑3 …𝑉𝑑4 < 𝑉𝑟𝑒𝑓 - 𝐻𝐵
𝑉𝑑1 …𝑉𝑑3 ≥ 𝑉𝑟𝑒𝑓 + 𝐻𝐵
𝑉𝑑4 < 𝑉𝑟𝑒𝑓 - 𝐻𝐵
𝑉𝑑1 …𝑉𝑑4 ≥ 𝑉𝑟𝑒𝑓 + 𝐻𝐵
𝑆1
1
𝑆2
0
𝑆3
0
𝑆4
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
𝑖1
𝑖1 < 0
𝑖2
0
𝑖3
0
𝑖4
0
Energy transfer
Charging 𝑐1
Charging 𝑐2
(Discharging 𝑐1 to 𝑙2 & 𝑙2 to 𝑐2 )
Charging 𝑐3
0
(Discharging 𝑐1 &𝑐2 to 𝑙3
𝑖1 < 0 𝑖2 < 0 𝑖3 > 0
& 𝑙3 to𝑐3 )
Charging 𝑐4
(Discharging 𝑐1 &𝑐2 to 𝑙4 &
𝑖1 < 0 𝑖2 < 0 𝑖3 < 0 𝑖4 > 0
𝑐3 to𝑙3
𝑙3 ′ 𝑙4 to 𝑐4 )
𝑖1 < 0 𝑖2 > 0
0
0
𝑖1 < 0 𝑖2 < 0 𝑖3 < 0 𝑖4 < 0
Discharging 𝑐1 … 𝑐4 to load
reference voltage value of each capacitor will be Vdc/4. The
capacitor charging produce is as follows:
When the capacitor voltage exceeds from upper band, the
capacitor charging is stopped and its extra charge is transfered
through the diode. Also when the capacitor voltage is less than
the lower band, switch in it’s parallel branches will be turn off
and so the capacitor starts to charge. Therefore the capacitor
voltage required to scrutiny and their reference values are kept
constant. Because of Some reasons such as snaber resistances,
asymmetric behavior of components, and switching transients
and etc. the Capacitor voltage will be devious from their
reference values, in which case the presented control system
returns the capacitors voltage to their reference values.
For example, operation in one of case is explained.
Assume, When the capacitor C3 is charged, then capacitor
C1 voltage is below the lower limit, then the switch S3 will be
off and switch S1 will be on and diode D2 forward bias, so the
capacitor C2 can be provide c1 deficiency charge through
diode D2 with DC power supply until the capacitor C1 will be
charged to requirement value. After this process the control
system comeback to the normal operation and controlles the
capacitors voltage at their reference values, respectively.
In presented topology, each capacitor is charged through
DC source, directly. Therefore, the charging process is very
fast and the lack of charging and extra charging of capacitors
will be negligible .In other word, the voltage ripple of
capacitors are not visible. Consequently, the presented
topology and control system for voltage balancing have fast
dynamic response.
This topic will be displayed in the simulation results.
In the proposed chopper, the capacitors are charged to their
order. So the sequences of switching states are based on Table
2. Based on this switching algorithm, the block diagram of
proposed control method is shown in Fig 5. It can be seen
from this figure implementation of presented control system is
very simple.
Fig.3. Different operating modes of proposed chopper.
B. Cascading DCMC with H Bridge
Fig 4 (a) shows a five level inverter with chopper for
capacitor voltage balancing. if the proposed chopper is
connected to a five level inverter as Fig 4a, then output
voltage of inverter will has only five positive level. For
creating positive and negative levels one H-Bridge will be
connected to output of inverter Fig 4a. Fig 4b shows a nine
level inverter with positive and negative levels.
7B
IV. CONTROL SYSTEM DESCRIPTION
3B
In this paper, for the balancing the capacitor voltage at its
reference value, the hysteresis control method is used. It must
be noted that the DC link consists four capacitors (C1-C4) and
charging capacitor is done by voltage dividing. Therefore
236
International Conference on Innovations in Electrical and Electronics Engineering (ICIEE'2012) Oct. 6-7, 2012 Dubai (UAE)
chopper inductors are taken as L1 = L2 = L3= L4=2 mH and Δ
= 2 V (Δ is the hysteresis band set across VC = 50 V).All of
the applied Capacitors in the chopper circuit are same and are
taken as C1 = C2 = C3 = C4 = 330 μF.
The charging of dc link capacitors (C1-C4) to its desired
value is evident from Fig. 6(a), 6(b), 6(c) and 6(d),
respectively. The dc link capacitor voltages are also equalized
in this process.
The afore-presented simulation shown voltages stress on
switches S 1 , S 2 , S 3 , S 4 (Fig 7) and these voltage stresses are
reduced to one-quarter and one-tenth.
The nine-level inverter output voltage and load current is
shown in Fig(8).
Fig 4(a).inverter without H-bridge
Fig 4(b).inverter with H-bridge
(c)
Fig. 5. Control block diagram of a Parallel Switch Based On Chopper
Circuit
V. SIMULATION RESULTS
To exemplify the functioning and control of the proposed
chopper circuit in Fig (2), and its connection to the inverter in
Fig. 4(b) simulation studies are performed on a five-level
diode clamped inverter.
The phase disposition modulation strategy is considered with
an amplitude modulation index (ma) =0.8 and a frequency
modulation index (mf) = 21. The inverter is supplying an RL
load with R = 20 Ω and L = 35 mH. The dc-link voltage is 200
V, and the inverter devices are assumed to be nearly ideal. The
Fig.6. Voltage of capacitors in the four- level chopper.
(a)VC1
(b)VC2 (c) VC3 (d)VC4
237
International Conference on Innovations in Electrical and Electronics Engineering (ICIEE'2012) Oct. 6-7, 2012 Dubai (UAE)
VI. CONCLUSION
This paper has proposed a Parallel Switch Based on
Chopper Circuit for DC Capacitor Voltage Balancing in
Diode-Clamped Multilevel Inverter, and they consist of
chopper circuit and diode-clamped inverter structures. The
structure and the operation principle of this topology are
introduced for single-phase mode and simulation results for
both of the single-phase and three-phase mode with the
asymmetric load have been presented. It requires additional
inductors but of reduced voltage rating compared with the
conventional chopper and flying-capacitor-based chopper.
This topology reduced the device voltage stresses by onequarter and one-tenth.
The various operating modes of the chopper are described
according table 2 to achieve the desired performances.
The chopper circuits are applied to balance the voltage of
DC link capacitors with any load conditions, as well as
participate in synthesizing the output voltage levels.
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Fig.7. Voltage stress on switches.(a)S1.(b)S2.(c)S3.(d)S4
Fig.8.Single phase inverter.(a) Inverter output voltage, (b)Load
current
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