13.05 GHz PLL based LO generator in SiGe:C
Marcel J.M. Geurts1, Louis Praamsma1, Hasan Gül1, Fanfan Meng1, Henk Bontekoe1, Rainier Breunisse1,
Henk Visser1, Cicero S. Vaucher2, Edwin van der Heijden2
1
2
NXP Semiconductors, Nijmegen, 6534 AE, the Netherlands
NXP Semiconductors, Eindhoven, 5656 AE, the Netherlands
Abstract — This paper presents our system choice and
measured results of an LO generator in SiGe:C technology. The
application for this IC is in Ku band Linear Block Up Converter
for VSAT systems. The system requires the generation of an
extremely low phase noise at 13.05 GHz from a 10 MHz
reference. The reference signal has high frequency accuracy but
poor phase noise. We demonstrate overall system performance
with a 2 PLL based solution. The first PLL has a low bandwidth
and uses a Xtal based VCO. It cleans up the 10 MHz, and
converts the frequency to 204 MHz. The second PLL, subject of
this work, converts the 204 MHz to 13.05 GHz. Measured
performance show: (offset frequency in Hz, phase noise density
in dBc/Hz) 1 k, -97; 10k, -97; 100k; -97; 1M, -104; 10M, -130.
Output power of -5 dBm, Reference spurii < -71 dBc. Maximum
current consumption is 104 mA from a supply of 3.3 V at 85 deg
C. Measurements are performed on a packaged device in a
HVQFN24 (SOT 616-1), on a 20 mil RO4003 board.
In this article we discuss the Local Oscillator (LO)
generator for a linear BUC. ‘Linear’ means the IF to RF
conversion is done by mixing with an LO. The linear BUC for
Ku band use either 13.05 GHz (for standard range) or 12.8
GHz (for extended range) as LO frequency. To enable precise
frequency and time multiplexing the downlink signal provides
an accurate frequency reference (10 MHz). The indoor unit
frequency multiplexes this with the uplink IF signal. The LO
signal in the BUC needs to be frequency locked to this
reference. The specifications are we used are listed in TABLE
I.
Satellite
Index Terms — BiCMOS analog integrated circuits, Satellite
communication, Integrated circuit packaging, Integrated circuits,
Microwave frequency conversion, Microwave oscillators, Phase
locked loops, Printed circuit layout, Satellite communication
earth terminals, Phase Noise.
VSATs
HUB
I. INTRODUCTION
A Very Small Aperture Terminal is a two-way satellite
ground station with a dish antenna diameter in the range of 1.2
to 3 m (definitions vary). VSAT data rates typically range
from narrowband up to 4 Mbit/s. VSATs access satellites in
geosynchronous orbit to relay data from small remote earth
stations (terminals) to other terminals or master earth station
"hubs". The network is depicted in fig. 1. VSATs are most
commonly used to transmit narrowband data (point of sale
transactions such as credit card), or broadband data (for the
provision of Satellite Internet access to remote locations, VoIP
or video) [1].
Both Time Division Multiple Access and Frequency
Division Multiple Access techniques are used to share the
satellite bandwidth over the terminals [2].
A VSAT consists of 3 main subsystems: the dish antenna,
the outdoor unit (for frequency translation between RF and
IF) and the indoor unit (processing the signals between the
outdoor unit and the indoor network). The outdoor unit
consists of an uplink/downlink separator (typically a
microwave component isolating the downlink from the uplink
signals), a Low Noise Block (LNB) for receiving the
downlink signals and a Block Up Converter (BUC).
Fig. 1 VSAT Network
TABLE I
BUC LO GENERATOR SPECIFICATION
Parameter
Temperature
Supply voltage
Supply current
Phase noise
Spurious
Output power
Conditions
MIN
-40
3.0
Offset freq.
100
1k
10k
100k
-7
MAX
85
3.6
200
UNIT
ºC
V
mA
-55
-72
-82
-92
-70
-3
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBm
The synthesizer of the clean up PLL can be implemented as an
Integer N in e.g. a CPLD [3]. The resulting values are for
13.05 GHz (12.8 GHz between brackets): Reference division
ratio = 64 (48), comparison frequency = 156.25 (210 ) kHz
and main division ratio = 1305 (960)
III. DESIGN CONSIDERATIONS
The system we designed is a cascade of 2 PLLs: the cleanup PLL and the RF PLL. To determine the intermediate
frequency the phase noise is considered. The RF PLL is
realized in a 120 GHz fT SiGe:C process (QuBiC4X [4]).
Free-running VCO phase noise performance of –87 dBc/Hz at
100 kHz offset frequency have been reported in a similar
technology [5]. This is not sufficient to meet the required –92
dBc/Hz. We therefore considered the required Phase
Frequency Charge Pump (PFDCP) Figure of Merit (FOM) [6]
[
L( f ) = FOM dBc
Hz 2
] + 20 log
10
N + 10 log10 f ref
[dBc Hz ]
IV. COMPLETE LO GENERATOR
The complete LO generator we propose consists out of 2
PLLs. First we convert the 10 MHz to 203.90625 (200) MHz
(values for 12.8 GHz between brackets). The output of the
clean-up PLL is used as reference for the RF PLL: the
TFF1003HN. This is an integrated synthesizer VCO. The
VCO has a tuning range from 12.8 to 13.05 GHz. The input
and output are differential. The divider can be set to 16, 32,
64, 128, 256. In this article we describe the results in the 64
setting. The output is –5 dBm. The device has a lock detect
output.The output of the TFF1003HN is filtered and amplified
to drive the mixer. The complete block diagram is shown in
fig. 2.
(1)
The FOM reported in the technology is –222 dBc/Hz2 [5],
giving a synthesizer noise floor of –108 dBc/Hz @ division
ratio=16 (reference frequency 816 MHz) increasing with 3 dB
per division ratio octave to –96 @ division ratio=256.
We choose division ratio = 64 (204 MHz reference), resulting
in a synthesizer noise floor of –102 dBc/Hz. This will give
enough margin over Process, Voltage and Temperature, as
well as an acceptable complexity for the clean-up PLL. The
latter serves 2 goals: 1) frequency conversion from 10 MHz to
204 MHz; 2) removal of unwanted phase noise of the 10 MHz
reference to the BUC. The phase noise of the 204 MHz signal
should be small compared to the input phase noise of the
TFF1003 which is: –102 – 20log10(64)= –138 dBc/Hz.
Commercially available VCXOs can meet this requirement
[7][8]. By applying a very small loop bandwidth (30 Hz) we
achieve an excellent tracking of the reference combined with a
superb phase noise, determined by the VCXO at offset
frequencies higher than the loop bandwidth.
Note that in the 12.8 GHz output case, the reference frequency
should be set to 200 MHz.
V. PACKAGE
The package used for the TFF1003HN is an HVQFN24
(SOT616-1). The assignment of pins has been done for
optimal performance: Three voltage domains are used to
separate the blocks on the IC. 2 pins for each output (OUT_P
and OUT_N) have been reserved to match a typical linewidth
of a Z=50 Ohm microstrip on Rogers 4003 20 mil board (1.1
mm). Ground pins have been placed next to the reference
input and the output. The supply pins are all on the same side
of the IC to minimize crossings in the application. A block
diagram is depicted in fig. 3.
Mixer
Band
Pass
Filter
Solid
State
Power
Amp
Synchronized QPSK data on L band carrier in the range 0.95~1.45 GHz (extended range: 0.95~1.7 GHz)
From
indoor
unit
13.05 GHz settings
(12.8 GHz settings)
10 MHz
/64
(/48)
PFD
Amp
12.8~13.05
on-chip VCO
203.90625 (200) MHz
LF
PFD
LF
Band
Pass
Filter
156.25 kHz
(203.33 kHz)
/1305
(/960)
/64
TFF1003HN
Clean up PLL build around VCXO
Loop bandwidth 30 Hz
203.90625 (200) MHz > 13.05 (12.8) GHz
TFF1003 @ DIV=64 PLL with on-chip VCO
Fig. 2 Complete LO generator for linear Block Up Converter. The values indicated are for the 13.05 GHz output frequency (values for the
extended range with 12.8 GHz LO frequency are between brackets)
2
C2
R1
C1
GND = 0
open or 3.3 V = 1
64=010
1nF
R2
C3
6
NSL2
5
NSL1
7
LCKDET
3
VTUNE
Lock: 2.5 V
2
CPOUT
1
VREGVCO
10 pF
VCC(DIV)
(3.3V)
100 kΩ pull ups
24
GND3(OUT)
10 pF
2.7 V
Window
Detector
No lock: 0 V
8
GND1(REF)
50 Ω
4
NSL0
23
OUT2_P
VCC(OUT)
100 kΩ pull down
CPOUT
Z0 = 50 Ω
Z0 = 50 Ω
22
OUT1_P
DC block
Agilent
11742A
DC block
21
OUT2_N
Z0 = 50 Ω
51 Ω
Termination
50 Ω
VCO
PFD CP
10 nF
51 Ω
50 Ω
50 Ω
VTUNE
9
IN(REF)_P
50 Ω
Reference source
R&S SMA
DIVIDER
10
IN(REF)_N
10 nF
NSL0
NSL1
NSL2
11
GND2(REF)
Z0 = 50 Ω
TFF1003HN
3.3 V
R&S SPA
12
VCC(REF)
20
OUT1_N
V to I
19
GND2(OUT)
2.7 V
13
VCC(DIV)
14
GND(DIV)
50 Ω
Termination
15
VREGTAIL
16
VTAIL
17
GND1(OUT)
18
VCC(OUT)
*
*
*) Optional for Po(OUT) adjustment
Fig. 3 Detailed block diagram of TFF1003HN and the setup as measured. The pin assignment in for the TFF1003HN is identical to the
physical IC pin assignment
V. MEASUREMENT SETUP
The measurements we present in this article are performed on
the TFF1003HN demo-board (fig. 3), using the set up
described in TABLE II.
TABLE II
MEASUREMENT SETUP
Reference source
Spectrum analyzer
Power supply
Reference connection
AC coupling input
Output connection
AC coupling output
Rohde & Schwarz
Rohde & Schwarz
TTI
AC coupled to REF_P
REF_N AC terminated
On-board 10 nF
AC coupled to OUT_P
OUT_N AC terminated
Agilent
SMA
FSU26
QL355TP
11742A
Fig. 4. Measurement board
V. MEASUREMENT RESULTS
Current consumption: T=-40 ºC: 92mA; T=25 ºC: 99 mA;
T=85 ºC: 104 mA.
-3.0
– 40 º C
Output power [dBm]
-60
Phase noise density [dBc/Hz]
-70
-40 º C
-80
25 º C
-90
85 º C
-100
25 º C
-4.0
85 º C
-110
-120
-130
-5.0
12.80
-140
-150
12.85
12.90
12.95
13.00
13.05
LO frequency [GHz]
Fig. 8. Output power (13.05 GHz carrier). Output power stays
between –3.2 and –4.2 over temperature and frequency.
-160
1k
10k
100k
1M
10M
100M 1G
V. CONCLUSIONS
The TFF1003HN used in conjunction with a clean-up PLL
Fig. 6. Phase noise density (13.05 GHz carrier). Performance exceeds the performance as is required for LO generation in
for VSAT linear up conversion. This gives an easy to use
better than –94 dBc/Hz.
solution for this subsystem.
Offset frequency from carrier [Hz]
Reference spur [dBc]
-60
-40 º C
25 ºC
85 º C
-40 º C
25 ºC
85 º C
The authors are thankful to Ron Schiltmans from ASC Signal
Krefeld, Germany, for technical discussions.
REFERENCES
-70
[1]
[2]
[3]
[4]
-80
-90
[5]
-100
10
11
12
13
14
15
16
Frequency [GHz]
[6]
Fig. 7. Spurious from 204 MHz reference (13.05 GHz carrier).
Performance better than –71 dBc
[7]
[8]
[9]
4
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