ACCEPTED ON JAN. 12, 2013 BY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, DOI: 10.1109/TCSII.2013.2240852
1
Phase Noise Modeling for Integrated PLLs in
FMCW Radar
Frank Herzel, Arzu Ergintav, and Yaoming Sun
Abstract—The effect of frequency modulation on the phasenoise spectrum of a charge pump (CP) phased-locked loop (PLL)
for FMCW radar is investigated. The static phase error is
calculated as a function of frequency ramp slope and basic PLL
design parameters. The phase-noise spectrum under frequency
modulation is deduced from the spectrum in the steady state.
Design guidelines for integrated PLLs to be used in FMCW radar
are derived from theoretical considerations and experimental
results from the literature.
Index Terms—frequency
FMCW radar, phase noise
synthesizer,
phase-locked
loop,
II. C ALCULATION OF PHASE ERROR
A. Derivation of differential equation
For our calculation we consider a standard second-order
charge pump (CP) PLL as depicted in Fig. 1. The PD is
φREF(t)
φ(t)
I. I NTRODUCTION
NTEGRATED transceivers are needed for low-cost ranging systems. Several ranging methods such as pulseradar, UWB radar and frequency modulated continuous wave
(FMCW) radar are possible candidates. FMCW has the advantage of not requiring a high peak-to-average power ratio
(PAPR) or wideband operation. A 77 GHz FMCW radar
transceiver IC with an accurate FMCW chirp signal generator
using a 90 nm CMOS process was presented in [1]. Here, a
direct digital frequency synthesizer (DDFS) drives a 78 GHz
integer-N PLL. As an alternative, a fractional-N PLL can be
used in conjunction with a constant input frequency as the
FMCW generator [2], [3].
Regardless of the method used, FMCW radar requires a
linear frequency ramp at high frequencies. When realized as
a PLL, its output frequency f (t) must be swept over a sweep
bandwidth bs within a sweep duration Ts . For a high resolution
and short-range radar, the ramp slope bs /Ts must be large,
which drives the PLL away from the steady state. This raises
the question of how frequency error and phase error at the
phase detector (PD) input are affected by the frequency drift.
Moreover, the dependence of the phase-noise spectrum on the
ramp slope and on PLL design parameters must be understood
in order to find a good compromise between spatial resolution
and noise performance.
In this paper, we deduce the phase-noise spectrum under
frequency modulation (FM) approximately from a steady-state
situation without FM and derive PLL design guidelines.
DN
PFD / CP
V(t)
R
VCO
ω(t)
1/N
I(t)
C
I
Accepted for publication in IEEE Transactions on Circuits and Systems II:
Express Briefs on Jan. 12, 2013. published version appears in TCAS2, vol.
60, no. 3, pp. 137-141, Mar. 2013, doi: 10.1109/TCSII.2013.2240852
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The authors are with IHP, Im Technologiepark 25, 15236 Frankfurt (Oder),
Germany (e-mail: herzel@ihp-microelectronics.com).
UP
Fig. 1.
Schematic of second-order charge-pump PLL.
composed of a phase-frequency detector (PFD) and a CP. The
UP input of the PFD is driven by a reference signal with phase
ϕREF (t). The VCO output frequency is divided by N and the
divider output is connected with the DOWN input of the PFD.
Assuming that the phase ϕ(t) of the divided signal lags the
reference phase, the CP will generate a positive current flowing
through the first-order loop filter. This will increase the VCO
control voltage V (t) and the VCO output angular frequency
ω(t).
A frequency drift of ω(t) can be obtained by changing the
reference (angular) frequency ωREF (t) = dϕREF /dt as in [1],
or by changing the divider ratio N in small steps as in [2],
[3]. The latter approach requires a fractional-N PLL with fine
frequency steps. We consider a PLL with a reference frequency
ramp in the remainder:
ωREF (t) = ωREF (0) + αREF t ,
(1)
where αREF = 2π (dfREF /dt) is the angular acceleration. We
define the phase error at the PD input by
ϕe (t) = ϕREF (t) − ϕ(t) .
(2)
Its first derivative is given by
dϕe (t)
dϕ(t)
= ωREF (t) −
.
dt
dt
(3)
Substituting (1) in (3) we obtain the second derivative given
by
d2 ϕ(t)
d2 ϕe (t)
= αREF −
.
(4)
2
dt
dt2
ACCEPTED ON JAN. 12, 2013 BY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, DOI: 10.1109/TCSII.2013.2240852
This equation will be useful to eliminate ϕ(t) from the
differential equation describing the loop dynamics.
In the following, we consider a linear, time-invariant
continuous-time model (CTM) to keep the analysis of the
FM-induced phase error as simple as possible. In reality, a
CP-PLL behaves like a time-discrete system as shown in [4]
for integer-N PLLs. The time-varying behavior of all-digital
PLLs has been discussed in [5]. A CTM combined with linear
frequency-domain analysis is unable to account for the in-band
noise contributions and spurs caused by spectrum folding.
Fortunately, for typical automotive FMCW-radar applications
the radar signal is in the range from 100 kHz to 1 MHz [6]. In
this offset frequency range the CTM is relatively accurate [4].
For short-distance radar with moderate ramp slope, however,
the validity of our assumptions should be checked. If needed,
more accurate phase noise models should be used, avoiding
the simplifications mentioned above.
Next, we will describe the transfer functions of the various
PLL blocks. The PD gain is given by
KPD =
ICP
,
2π
I(t) = ϕe (t)KPD ,
and its first derivative reads
(8)
where the VCO gain is referred to the VCO frequency f (t) =
ω(t)/2π and is given in units of Hz/V. Substituting (8) into
(9) we find
1 dω(t)
d2 ϕ(t)
=
.
2
dt
N dt
ϕ0e =
CN αREF
.
2πKPD KVCO
ϕ0e =
CN αREF
.
ICP KVCO
(16)
Replacing αREF with sweep bandwidth bs (in units of Hz)
and sweep duration Ts according to
N αREF =
we obtain
ϕ0e =
2πbs
Ts
2π C bs
.
ICP KVCO Ts
(17)
(18)
In order to solve (14) for the general case, we define the
dynamic phase error ϕde (t) by
(19)
Substituting (19), (15) and (5) into (14) we obtain the homogeneous differential equation
d2 ϕde (t) ICP KVCO R dϕde (t) ICP KVCO d
+
+
ϕe (t) = 0 . (20)
dt2
N
dt
CN
This is the well-known differential equation describing a
damped harmonic oscillator [7]. Introducing the damping
constant γ and the angular frequency ω0 by
ICP KVCO R
2N
√
and
ω0 =
ICP KVCO
,
CN
(11)
we can write (20) as
(12)
dϕde (t)
d2 ϕde (t)
+
2γ
+ ω02 ϕde (t) = 0 .
dt2
dt
For γ < ω0 , the solution is a damped oscillation
[√
]
ϕde (t) = A exp(−γt) sin
ω02 − γ 2 t + B ,
Replacing the current by the phase error using (6) we find
(15)
Substituting (5) into (15) we obtain
(10)
Substituting (10) into (11) we obtain
2πKVCO R dI(t) 2πKVCO
d2 ϕ(t)
=
+
I(t) .
dt2
N
dt
CN
In a first step, we consider the steady state defined by
dϕe /dt = 0. Strictly speaking, a steady state cannot exist
due to the finite sweep duration Ts . However, if Ts is larger
than the PLL settling time ts , we can approximately assume
a steady state for the time interval Ts > t > ts . In this case,
we obtain from (14) the steady-state phase error
γ=
According to Fig. 1, the PD input phase obeys
(14)
B. Solution of differential equation
ϕe (t) = ϕde (t) + ϕ0e .
According to Fig. 1, the output frequency of the VCO obeys
the equation
dω(t)
dV (t)
= 2πKVCO
,
(9)
dt
dt
dI(t)
I(t)
dω(t)
= 2πKVCO R
+ 2πKVCO
.
dt
dt
C
d2 ϕe (t) 2πKPD KVCO R dϕe (t)
+
+
dt2
N
dt
2πKPD KVCO
+
ϕe (t) = αREF .
CN
(6)
where 0 ≤ ϕe < 2π is assumed. The resulting voltage across
the loop filter is given by
∫
1 t
V (t) = RI(t) +
I(τ )dτ + const ,
(7)
C 0
dV (t)
dI(t) I(t)
=R
+
.
dt
dt
C
Finally, we eliminate ϕ(t) by using (4) and obtain an inhomogeneous second-order differential equation
(5)
where ICP is the CP current in the ON state. In a continuoustime model of the PLL the average CP output current reads
2
(21)
(22)
(23)
(24)
2
2πKPD KVCO R dϕe (t) 2πKPD KVCO
d ϕ(t)
=
+
ϕe (t) .
dt2
N
dt
CN
(13)
where the constants A and B are to be determined from the
initial conditions. The settling requirements depend on the
ACCEPTED ON JAN. 12, 2013 BY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, DOI: 10.1109/TCSII.2013.2240852
system. An approximate expression for the settling time is
given by
20N
ts ≈ 10/γ =
.
(25)
ICP KVCO R
In this case, the exponential factor exp(−γt) of the solution
(24) is as small as 4.5 × 10−5 . Assuming an initial phase error
of ϕde (0) = 180◦ , the dynamic phase error |ϕde (t)| is smaller
than 0.008◦ for t > ts . This value is on the same order as
typical rms phase errors at the PD input for integrated PLLs.
To minimize VCO phase noise, KVCO should be large
enough to cover the required tuning range under all conditions
with sufficient margin, but not larger. By contrast, the charge
pump current should be as large as possible. This will minimize the static phase error and the PLL settling time, as evident
from (16) and (25). The only limitations are the available
power budget for the CP and, possibly, signal integrity.
Summarizing this section, for a linear input frequency ramp
the PLL phase error at the PD input converges to a steadystate value describing the phase lag of the PLL. This value
is proportional to the ramp slope and can be minimized by
using a large CP current. The remaining part of the phase
error obeys the same differential equation as for the case of
constant reference frequency.
III. P HASE NOISE CONSIDERATIONS
Obviously, a large static phase error at the PD input implies
a high CP activity. This increases the CP duty cycle αCP =
TON /TREF , where TON is the CP activation time and TREF
is the reference period. In the steady state, the CP duty cycle
is related to the static phase error via
ϕ0e
.
(26)
2π
In a charge-pump PLL, the in-band phase noise is usually
limited by thermal noise and 1/f noise of the CP transistors [8].
The white noise power spectral density (PSD) of the charge
pump output current due to thermal noise and shot noise is
2
proportional to αCP , whereas 1/f noise is proportional to αCP
[9]. Adding the two noise contributions, we obtain for the PSD
of the CP output current [10]
(
)
αCP fc
white
αCP 1 +
SCP = SCP
,
(27)
f
αCP =
where fc is the 1/f noise corner frequency of the transistor.
white
The parameter SCP
corresponds to the CP current noise
PSD due to white noise sources at 100% CP duty cycle.
Transforming the noise current PSD to the PD input using
(5), we obtain for input-referred phase PSD
1 2
.
(28)
Sϕ,in = SCP KPD Substituting (27) and (5) into (28) yields
2
)
(
αCP fc 2π white
Sϕ,in = SCP
αCP 1 +
ICP .
f
doubling the CP current ideally reduces the corresponding PLL
phase noise contribution by 3 dB.
The measurement of a PLL phase-noise spectrum for a
ramped input frequency is very difficult, since the PLL is
not in steady state. The main goal of our paper is to define
a steady-state situation, where the PLL spectrum is similar.
This will allow the phase-noise spectrum under frequency
modulation to be deduced from measurements or simulations
with constant input frequency. In [11] an offset current to
ground was used to generate a static offset at the PD input.
The motivation for this was to improve the linearity of the
PD in the fractional-N PLL used there. If the offset current
is a sufficiently large down current, then only the UP current
will respond to phase error changes in the steady state. This
improves the linearity of the phase detector and reduces phase
noise significantly. In this case, the output current I of the
CP is a continuous function of the phase error ϕ at the PFD
input, ideally a linear function. This idea was used in the
integer-N 10 GHz PLL presented in [8], where the measured
phase noise was monitored as a function of the offset current.
With a CP current ICP of 8 mA the offset current IOS was
varied between 0 and 2 mA, corresponding to a CP duty cycle
αCP = IOS /ICP between 0 and 25%. According to (26), this
corresponds to a static phase error between 0 and 90◦ . The
measured in-band phase noise was increased by typically 4 dB
in this duty cycle range, from -105 dBc/Hz to -101 dBc/Hz at
100 kHz frequency offset. With a larger static phase error,
the in-band noise will further increase. This is especially
troublesome for CMOS implementations, since the relatively
high 1/f noise increases in proportion to the squared phase
error according to (27). The allowable phase noise depends on
the application and must be carefully determined from system
simulations, which are beyond the scope of our paper. Such
simulations have been performed in [6], where the impact of
phase noise parameters on target signal detection in FMCWradar systems for automotive applications was investigated.
The spatial resolution was shown to depend strongly on the
VCO phase noise, especially for multi-target scenarios. This
suggests that the VCO phase noise be reduced by PLL highpass filtering using a large loop bandwidth and a large CP
current [8].
Let us assume, as an example, that a CP duty cycle of 10%
is allowed from the phase noise point of view. For a fractional
PLL this phase offset is usually sufficient to linearize the
PD, reducing in-band phase noise and spurs due to folding
of quantization noise [11]-[14]. Since αCP =10% corresponds
to ϕ0e = 2π/10 according to (26), we obtain from (16) an
upper bound for the angular acceleration
2π ICP KVCO
αREF <
.
(30)
10
CN
According to (18), this corresponds to the recommendation
10 C bs
.
(31)
ICP KVCO
For a numerical illustration, we consider the following parameter set: bs = 1 GHz, C = 1 nF, KVCO = 1 GHz/V, ICP =
2 mA. From (31) we obtain the recommendation Ts > 5 µs
for these PLL parameters. This means that the sweep duration
Ts >
(29)
For a given CP topology with programmable CP current ICP ,
white
SCP
is proportional to ICP . From this we conclude that
3
ACCEPTED ON JAN. 12, 2013 BY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, DOI: 10.1109/TCSII.2013.2240852
IV. L INEARITY CONSIDERATIONS
So far we have assumed a constant VCO gain. In reality,
the VCO gain varies with the control voltage, especially,
if an integrated VCO is used. Using special circuit design
techniques, the VCO gain can be equalized to some extent
[15]. In addition, the VCO gain variations in a PLL can further
be reduced by using two VCO tuning inputs for fine and coarse
tuning. If the fine tuning dominates the loop dynamics and
the fine tuning voltage is kept roughly constant by proper DC
biasing, the effective VCO gain can be kept fairly constant
over the PLL tuning range [8], [16], [15]. The problem of
using two parallel tuning loops in the context of FMCW is
that the coarse tuning loop must not be too slow in order
to achieve the required frequency ramp slope. This results
in a subtle trade-off for the coarse tuning loop capacitance
value, which has been discussed in [17] in the context of
WLAN applications. If the fractional-N PLL approach with
programmable N is used, the frequency dependence of KVCO
can be compensated by the frequency dependence of N .
This approach is especially useful for ultra-wideband FMCW
radar and was experimentally demonstrated in [3]. Another
promising approach to linearize a PLL for FMCW radar is
adaptive input predistortion [18].
Despite all efforts, some nonlinearity will remain and must
be minimized. As evident from (16), the static phase error and
its absolute variations with the VCO control voltage can be
minimized by increasing the CP current and by reducing the
loop capacitance C. While a small C may increase the PLL
phase noise, a large CP current ICP reduces the phase noise
[10]. In [8] a very low phase noise was achieved by using a
CP current as high as 8 mA. Note that for a CP duty cycle of
10%, the DC current of the CP is below 1 mA, keeping CP
power consumption at a reasonable level. Resulting from these
observations, the following design procedure for integrated
PLLs is suggested:
• use a relatively large filter capacitance C limited by the
available chip area only;
• use a large CP current;
• use a proper loop resistance R such that the settling time
according to (25) is short enough.
Note that the use of a large CP current may conflict with the
linear model used here, which requires small changes of the
VCO control voltage in the steady state. In reality, this can
be achieved by using small R, large C and a small bypass
capacitor C2 from the CP output to ground. The latter was
not included in our second-order PLL model to facilitate the
analysis of the phase error. In a well-designed PLL C2 would
reduce the reference spurs, but it would hardly change the
in-band phase noise discussed in this paper.
V. M ODELING R ESULTS
In this section, we investigate the steady-state phase-noise
spectrum as a function of the ramp slope. The analysis is based
on the linear phase noise model described in [19]. This model
includes the noise of the CP, the VCO, the reference input,
reference buffer, and the loop filter. It is based on an analytical
description of the noise sources and transfer functions, where
the model parameters are to be determined from measurements
or simulations. The model has been verified for the 24 GHz
PLL in [19] by comparing modeled and measured phase noise
spectra. In this paper, we are targeting higher frequencies of
80 GHz and above, where experimental results are not yet
available. However, since CP, PFD and reference input buffer
will not be changed, the corresponding noise parameters are
the same and will be used for noise prediction. The incorporation of quantization noise generated in the sigma-delta
modulator (SDM) of a fractional-N PLL has been described
in [10]. This also includes noise folding in the nonlinear PD.
Here we assume that a DDFS drives an integer-N PLL, where
quantization noise within the PLL is not an issue.
As an example, we investigate a 78 GHz integer-N PLL
driven by a ≈100 MHz reference using a CP current of
2 mA. The filter parameters are C=1 nF and R=10 kΩ. The
white
charge pump noise parameters SCP
and fc were extracted
from measurements on a previous design [19], where a low
CP current was used to maximize CP induced phase noise.
The reference buffer noise parameters were deduced from
phase noise measurements with very small input amplitudes
to maximize buffer-induced phase noise. The VCO phase
noise parameters were extracted from a recently published
61 GHz VCO [20] manufactured in a 130 nm SiGe BiCMOS
technology. Fig. 2 shows the measured phase-noise spectrum
of this VCO. The phase noise measurement was performed
Phase Noise (dBc/Hz)
should not be lower than 5 µs to keep the static phase error
below 36◦ . As shown in Section V, for a 36◦ phase error the
phase noise spectrum is more than 10 dB higher than for the
case without FM. In order to reduce the phase noise to the
vicinity of the achievable limit, a phase error of about 3.6◦
is needed, corresponding to a CP duty cycle of 1%. In this
case, the sweep time should not be lower than 50 µs for our
example.
For the PLL settling time we find from (25) the values
ts =780 ns for R=10 kΩ, and ts = 7.8 µs for R=1 kΩ. Here
we assumed a divider ratio of N =78 GHz / 100 MHz=780.
4
-70
-90
-110
-130
-150
ϭϬ4
10
ϭϬϬ
105
ϭϬϬϬ
106
ϭϬϬϬϬ
107
ϭϬϬϬϬϬ
108
Frequency Offset (Hz)
Fig. 2.
output.
Measured phase-noise spectrum of 61 GHz VCO at 1:16 divider
after 1:16 division at 3.8 GHz output frequency. In our model,
ACCEPTED ON JAN. 12, 2013 BY IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, DOI: 10.1109/TCSII.2013.2240852
an estimate for the VCO phase noise is obtained by adding
20 log10 (78GHz/3.8GHz)=26.2 dB to the measured values.
As discussed at the end of Section III, a sweep duration
of Ts = 5 µs corresponds to a static phase error at the PD
input of ϕ0e = 36◦ . Similarly, the sweep durations Ts = 50 µs
and Ts = 1 µs correspond to ϕ0e = 3.6◦ and ϕ0e = 180◦ ,
respectively. By using (26) we obtain an equivalent CP duty
cycle αCP = ϕ0e /360◦ , where the phase error is given in
degrees. The parameter αCP serves as an input to the phase
noise model in [19]. In this way, we can approximately
deduce the phase-noise spectrum under FM from the wellknown steady-state case. Fig. 3 shows the modeled phase noise
spectra for the three different static phase errors. Here we
Phase Noise (dBc/Hz)
-50
φ0e = 180o
36o
3.6o
-60
-70
-80
-90
-100
φ 0e = 0
-110
-120
-130
104
105
106
107
108
109
1,0E+04 1,0E+05 1,0E+06 1,0E+07 1,0E+08 1,0E+09
Frequency Offset (Hz)
Fig. 3. Modeled phase noise spectra of a 78 GHz PLL for different static
phase errors at the PD input.
used the following parameters: R=10 kΩ, C=1 nF, ICP =2 mA,
KVCO =1 GHz/V, and N =780. Using (21), we obtain the loop
bandwidth fL in units of Hz given by
2γ
ICP KVCO R
=
≈ 4 MHz ,
(32)
2π
2πN
consistent with Fig. 3. If the settling time of ts =780 ns must
be further reduced, the CP current ICP should be increased
rather than KVCO or R. This will keep static phase error
and phase noise low, as discussed in Sections II and III. The
ideal case ϕ0e = 0 is also depicted in Fig. 3 for comparison.
According to (27), this corresponds to a noise-less CP in
our model. For ϕ0e = 3.6◦ , the phase noise spectrum is a
few dB higher in the kHz range, showing that the CP noise
contribution is similar to the other phase noise contributions.
By contrast, for ϕ0e = 36◦ the phase noise spectrum is more
than 10 dB higher than for the ideal case. This demonstrates
that the FM-induced CP noise dominates the phase-noise
spectrum in this case. The effect of FM is most pronounced
at low frequencies, where 1/f noise dominates the spectrum.
This is due to the quadratic dependence of the 1/f current noise
PSD on the CP duty cycle according to (27).
fL =
VI. C ONCLUSIONS
We have calculated the static and dynamic phase error
at the phase detector input for a PLL driven by a linear
frequency ramp. The effect of the static phase error on phase
noise spectrum and linearity was discussed. We have presented
5
design guidelines for integrated PLLs to be used in FMCW
radar. Finally, we have calculated the steady-state phase noise
spectra for different ramp slopes corresponding to different
static phase errors. In summary, we believe the major impact
of our work will be to reduce the number of design cycles
when developing FMCW radar systems.
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