A Gain-Boosted 90-dB Dynamic Range Fast Settling OTA
with 7.8-mW Power Consumption
Yun Chiu, Ken Wojciechowski
Electrical Engineering and Computer Science Department
University of California, Berkeley
Berkeley, CA 94720
Abstract - A fully differential high-dynamic range operational transconductance amplifier (OTA) to be used in switchedcapacitor filters and/or over-sampled A/D converters is presented. The architecture chosen for this design is folded cascode
with fully differential gain boosting. It is demonstrated through the design analysis and HSPICE simulation that such a structure realizes the best trade-off between power consumption, speed, and dynamic range performances for this design. The OTA
achieves a constant large signal DC gain (ADC) of > 84 dB over process and temperature variations. It is designed in a 0.35-µm
2
CMOS process and draws a DC power of 7.8 mW from a 3-V supply. The achieved rms output noise voltage ( V o, n ) is 50.1
µV for the worst case scenario. With a peak-to-peak output voltage swing (Vo,pp) of 4.5 V, the achieved output dynamic range
(DR) is 90 dB. The OTA also demonstrates excellent settling behavior with a single-pole roll-off frequency response and no
over-shoot or ringing is observed at the output when the required maximum 4-V transient is applied at the input. The settling
time to < 0.05% accuracy for the worst case is ~ 19.5 ns.
1. INTRODUCTION TO GAIN-BOOSTING TECHNIQUE
As CMOS design scales into low-power low-voltage regime, designing analog functional blocks under limited
supply voltage becomes more and more difficult. One typical example is the basic gain stage. Cascoding is the
mostly used technique to achieve high gain compared to 2-stage designs because of its superior frequency
response. However, we quickly run into headroom problems while trying to cascode more transistors in a stack
Vbp
Vbp
M1
Vcp
In+
M2
In-
Vcp
Out+
OutVcn
Diff. Pair
Out-
Out+
Vcn
Vbn
Vbn
Single-ended gain boosting
Fully-differential gain boosting
Figure 1 CMOS gain-boosting techniques
under limited supply voltage. Gain-boosting technique [1] was introduced to remedy this problem. It allows
increasing the DC gain of the operational amplifier (op amp) without sacrificing the output swing of a regular cascode structure. Furthermore, it has been pointed out [2] that the gain-boosting technique decouples the DC gain and
the frequency response of the amplifier. It is therefore possible to achieve high speed and high gain at the same
time. These features are especially desirable in high-speed, high-dynamic range applications like switched-capacitor filters and A/D converters.
EE240, Spring 2000
Final Project Report
Typical gain-boosting structures are shown in Fig. 1. The single-ended boosting architecture uses four auxiliary op amps to regulate the transconductance (gm) of the cascode transistors and enhances the gain realized by the
original cascoding effect. It is first reported by K. Bult and G. Geelen [1]. However, the single-ended version of the
boosters are associated with some undesired effects, mainly,
• Signal usually travels a longer path inside the booster and see an extra pole from an internal current mirror.
Therefore, frequency response of the booster suffers, especially when optimizing the pole-zero doublet effect.
• Noises generated by the biasing circuitry inside the boosters are not correlated. This means the noise overhead associated with gain boosting is higher.
The problems are addressed by using a fully differential gain-boosting scheme. This improves the settling
behavior and reduces noise as well. But fully differential amplifier requires common-mode feedback. In this
design, an input common-mode voltage control circuit is adopted and will be illustrated in details later.
2. AMPLIFIER DESIGN
2.1. Optimum Architecture
Three candidates are available, i.e., telescopic differential OTA with gain boosting, folded-cascode OTA with
gain boosting, and 2-stage OTA with class-A output stage. The folded-cascode architecture with gain boosting is
chosen for the following reasons,
• Compared to the folded-cascode structure, a telescopic amplifier has a lower output swing range but twice the
power efficiency. Its output has to accommodate a minimum of 5 Vdsat’s and 1 Vth (not taking into account that tail
current source may need to be cascoded as well) while the folded-cascode structure has an overhead of only 4
Vdsat’s. Given the required DR of 90 dB, let’s do a quick calculation to see if the telescopic structure offers advantage. Assume Vdsat = 250 mV and Vth = 650 mV. For a 3-V supply, this indicates that the telescopic structure yields
a maximum output swing Vo,max = 3-5*0.25-0.65 = 1.1 V while the folded-cascode architecture achieves Vo,max =
3-4*0.25 = 2 V. This means we need to knock down the noise in the telescopic amplifier by about 4 times! Taking
into account that a telescopic amplifier has mainly 4 transistors contributing to the output noise while a folded-cascode one has 6, the later will show a noise factor (N) of about 5/3 times larger. Combining the two effects, we conclude that, although telescopic structure features a higher power efficiency and a lower noise factor, the dynamic
range constraint well offsets these advantages. But in a situation where less dynamic range is demanded or enough
supply room is available, the telescopic architecture will yield a better design.
• 2-stage OTA, on the other hand, offers even larger output swing where only 2 Vdsat’s have to be roomed for. If
a telescopic amplifier is used for the 1st stage, the architecture also offers a lower noise factor (ignoring noise contribution from the 2nd stage). But, unlike cascoding, cascading gain stages has negative impact on the frequency
response of the amplifier, and thus frequency compensation (Miller/cascode compensation) techniques have to be
employed to trade bandwidth for phase margin/stability. The 2nd stage usually has to burn a substantial amount of
power in order to push the non-dominant pole (ωp2 = gm2/CL) far away from the unity-gain frequency (ωu = gm1/
Cc). It is therefore usually used in interfacing applications where an output stage for driving external resistive loads
is indispensable. To drive on-chip capacitive loads, the superior frequency response and power efficiency of single
stage amplifiers generally offer better performance.
• Folded-cascode architecture with gain boosting is chosen as the optimum structure for this design. It offers
relatively large output swing and good single-pole roll-off frequency response. For applications that require both
high speed and high dynamic range, the folded-cascode structure offers the best trade-off compared to the afore
mentioned two architectures. It also achieves a much larger input common-mode voltage range. A properly
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EE240, Spring 2000
Final Project Report
designed gain-boosting amplifier offers plenty of gain (usually ~ (gmro)4) for a regular cascode structure yet still
preserves its frequency response characteristics.
Lastly, it needs to be pointed out that it is well known that a pole-zero doublet is often associated with gain
boosting. Later in this report, we will present the result from a small-signal analysis of the gain-boosting technique.
It will become clear that the pole-zero doublet and its consequence (slow settling) can be very well suppressed.
2.2. Dynamic Range
2
P signal
1 V o, pp
9
The dynamic range is defined as, DR = ---------------- = --- ⋅ -------------- = 10 . We assume a maximum output swing Vo,pp =
P noise
8
2
V o, n
4V based on the above analysis. So, V 2o, n = 1--- ⋅ 10 –9 ⋅ V 2o, pp ≈ 45µV . Assuming single pole frequency response, the
8
closed-loop output noise variance is
2
V o, n
2 1 kT
= N ⋅ --- ⋅ --- ⋅ ------- ,
3 β CL
where N is the noise factor, β is the feedback factor, and
CL is the load capacitance. We ignore the Flicker noise for the time being and only count the thermal noise because
settling time
gmp
slope = -8.7dB/τ
2
V n, p
gmi
gain (dB)
2
2
V n, n
time (s)
0
V n, i
gmn
Input-referred noise calculation
DC gain
Settling time calculation
Figure 2 Diagrams for noise, settling time calculation
of the large bandwidth requirement for fast settling. Flicker noise has an upper cut-off frequency which is ~ 100
KHz. For broadband systems it only contributes a negligible output noise power.
For a folded-cascode amplifier, 4 current sources and 2 input diff. pair transistors contribute most of the output
noise (Fig. 2). To calculate the noise, we refer Vn,p2 and Vn,n2 to the gate of the input transistor. Since 2 PMOS curg
g mi
4I
2I
V dsat, p V dsat, i
2V
V dsat, p
b
b
mp
dsat, i
rent sources drain double the current of the input transistor, the noise factor is N p = -------- = ------------------ ⁄ ---------------- = -------------------
g
g mi
2I
2I
V dsat, n V dsat, i
V
V dsat, n
b
b
mn
dsat, i
- = ----------------- ⁄ ---------------- = ----------------for these PMOS’ and is N n = -------for the NMOS’. So the total noise factor is
N = 2 ⋅ (N p + N n + 1) = 4
if we assume the gate overdrive voltage of the input diff. pair is 1/3 of that of the current
sources. Since we assumed 250-mV Vdsat for current source transistors, this really means that we need to reduce
the gate overdrive of the diff. pair in order to minimize N. This means the input transistors are relatively large. Let’s
C
Cs + C f + Ci
2
f
- ≈ --- . Thus we obtain CL,min =
assume Ci of the input transistor is about the same as Cs. Therefore, β = ------------------------------
8.1 pF, the minimum load capacitance required to achieve a 90-dB dynamic range.
3
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EE240, Spring 2000
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We ignored the noise contribution from the gain boosters in the above calculation. The reason of this is that the
noise factor associated with “cascode” transistors is usually much smaller than the current sources calculated
above. However, gain boosters are usually much smaller (less gm) compared to the main amplifier in order to save
power (they only need to drive the gate of the cascode). This leads to the observation that gain boosters may contribute a considerable amount of output noise power in a real design. Noise breakdown will be shown later in the
simulation stage. In this design, about 20%-30% output noise power is generated by the gain boosting circuits.
2.3. Settling Speed and Small-Signal Bandwidth
Refer to Fig. 2, a single pole frequency response results in a single slope of -8.7 dB/τ for settling. Here we
assume slewing is not present. The settling accuracy is determined by the transient loop-gain achieved by the
amplifier. We need to settle to < 0.05% in 20 ns. With a feedback factor β = 2/3, we obtain,
– 8.7dB
------------------ ⋅ 20ns = 20 ⋅ LOG10 ( β ⋅ 0.05% ) ≈ – 70dB ⇒ τ = 2.5ns
τ
1
- ⇒ ω u = 95MHz , so we obtain the open-loop unity-gain frequency ωu = 95 MHz. From ωu = gm/CL, we
but τ = --------βω u
can calculate gm = 4.83 mA/V. Finally, use the square-law relationship gm = 2Id/Vdsat, we get to the biasing current
needed, Id = 200 µA. Where we used the previous assumption of Vdsat = (250/3) mV. This looks pretty good! But
with 200-µA maximum output current delivered into 8.1 pF load, we know immediately it is going to slew. So this
power budget is too optimistic.
2.4. Slew-rate Limit

t
– --


Assuming a single time constant settling, the output voltage can be expressed as V o ( t ) = V o  1 – e τ , for t ≥ 0 .
Thus the slew-rate SR = d V o ( t )
dt
t=0
V
I o, max
= -----o- = --------------.
τ
CL
For this design, the maximum differential output swing is
Acl*4V = 1 V (with Acl = 1/4). So SR = 200 MV/s. With Id = 200 µA, the SR is limited to 25 MV/s. Thus, to settle
to 0.05% accuracy within 20 ns without slewing, it requires 8 times more biasing current as calculated in section
2.3. This yields the minimum biasing current Id = 3.2 mA for the input diff. pair. The total biasing current for the
OTA (excluding biasing and gain boosters) is then 6.4 mA and the total power consumption is about 20 mW.
The above estimation is pessimistic in that the NO SLEWING presumption is totally unnecessary. Later in the
section “Low-Power, High-Speed Design Techniques”, we will recalculate settling with slewing present and it will
be seen that having slewing dominant in settling yields a low-power design.
2.5. DC Gain
As mentioned before, the settling accuracy is determined by the loop-gain achieved by the amplifier. With β =
2/3, the minimum open-loop DC gain needed is ADC = 70 dB to achieve 0.05% (-66dB) settling accuracy assuming
the OTA fully settles to this gain within 20 ns. Given process and temperature variations, some margin should be
left for this figure. Also, it is generally known that BSIM models tend to overestimate the intrinsic output resistance
(ro) of devices when they are biased on the edge of saturation. For low-voltage designs, output transistors very
often fall into this biasing range. In summary, a rule of thumb is to give 10-20 dB margin for ADC in real designs.
We set ADC,min to > 80 dB. With the fully differential cascoded gain-boosting technique, even with minimum chan-
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EE240, Spring 2000
Final Project Report
nel length transistors used in the main amplifier, we are able to achieve over 84 dB constant ADC over process and
temperature variations.
3. HIGH-DYNAMIC RANGE, HIGH-SPEED, AND LOW-POWER DESIGN TECHNIQUES
In this section, we will present the design techniques and analysis on how to achieve low-power consumption
for high-speed, high-accuracy analog designs. These concepts are the core of this design that have been verified
through theoretical analysis and HSPICE simulations. It is what enables us to achieve a 7.8-mW power consumption for the stringent design specs of this project.
3.1. Minimum Channel Length for Analog Design
Short channel devices are often shunned by analog designers for considerations of mismatch, lower output
resistance, lower intrinsic gain, hot carrier stress, and lifetime, etc. By using longer channel devices than minimum,
we give up the gains accumulated by generations of technology scaling advancement. A big price in speed, power,
and chip area is paid making this trade-off. So, after all, is this a wise choice of deep-submicron analog design
methodology? Before answering this question, we first clarify some common misconceptions.
• Long channel does not eliminate short-channel effects (SCE) of deep-submicron CMOS devices. It is
commonly believed that by using a channel length far larger than minimum will eliminate the short-channel effects,
such as mobility degradation, velocity saturation, drain-induced-barrier-lowering (DIBL), and hot electron effect.
However, if asking a device engineer what is the dominant device parameter in CMOS process scaling, the answer
will be the gate oxide thickness (Tox), not channel length. Without analog options, a deep-submicron process usually offers uniform thin oxide throughout the wafer. Therefore, simply by drawing the transistors longer will not
help to reduce vertical field which directly impacts the channel carrier mobility.
• Matching is a function of active gate area, NOT only the channel length. Conventionally, matching is
believed to be a strong function of channel length only. This is a common misconception. What actually determines
the matching is the active gate area, not just length [3]. Pelgrom [3] and Razavi [4] have pointed out the spatial
averaging effect of large width but minimum length devices that improves matching. Therefore, using wide minimum length devices does not undermine matching property as long as the gate area is large. At the meantime, minimum channel length is also in favor of high-speed design. After all, a good design is a design that eliminates
matching requirement at the architecture/algorithm level, not at the device level.
• Scaling channel length to reduce hot carrier effect is ineffective for low-voltage design. High performance analog circuits usually conduct a DC biasing current at all time (class-A type). This stresses the device more
than digital devices, which only turns on during transitions. Therefore it is often believed that minimum channel
length should not be used for analog circuits. But if we take a look at the device equations, we will find that using
long channel devices is not really effective to reduce hot carrier effect.
Hot carrier effect is directly related to the maximum horizontal channel electric field (Em), which is expressed
V
–V
l'
ds
dsat
as E m = --------------------------- , where l' = 3T ox X j . We note that l' is not a function of channel length at all. The only place L
1
1
1
does play a role is Vdsat, which is ------------ = ----------------------- + ------------------ . When devices are biased with small overdrive voltages
V dsat
V gs – V th
E sat ⋅ L
(as in the case of low-voltage design), very large L does not help reduce Em. Furthermore, we can always implement circuit techniques (such as cascoding) to reduce Vds, which is more direct and far more effective than indirectly resorting to longer channel length.
• Lower output resistance. A lot of circuit techniques can address this problem (gain boosting is one). It is
often fruitless and painful in using long channel devices to achieve high DC gain.
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EE240, Spring 2000
Final Project Report
To summarize, long channel devices should NOT be used abusively. If problems can be solved using circuit
techniques, one should not resort to long channel options because the speed of the device is reversely proportional
to L2 (square law model). Therefore, low-power, high-speed designs definitely do not favor long-channel devices.
In this project, the low power consumption achieved partly attributes to using minimum channel length devices
consistently throughout the signal path.
3.2. Slewing is Favorable in High-Speed, Low-Power Design
A common misconception is slewing hurts settling. It is true in the sense that the so-called “linear settling” or
“proportional settling” concept does not work under slewing. However, in a sampled-data system, what actually
interests us is the final value of settling, not the settling process. As long as the amplifier achieves its final accuracy
within specified time, why do we need to impose an extra constraint that the settling process be absolutely exponential? On the contrary, a mostly slewing amplifier delivers all its current to the load more often than a non-slewing one, therefore yields higher power efficiency. Burning a lot of power to avoid slewing obviously is not the
optimum solution for low-power applications (“class-A dilemma”).
So how do we design for slewing? The answer is to use minimum allowable overdrive voltage for the input
diff. pair. On one hand, with fixed biasing current, this will introduce more slewing because the input transistor will
be easily cut off during large transients. On the other hand, the resulted larger gm of the input devices leads to a
faster exponential settling after slewing with a smaller time constant. Combine the two aspects and an optimum
low-power yet high-speed design yields.
Vi
Σ
+
−
Vx
Vi(t)
gmVx
Io
Io
Vx
A(s)
Vo
Vx(t)
VT
diff. pair limiting
β
Vo(t)
Linear feedback amplifier model with limiting
slewing
0 ts
time
Figure 3 A simple model of slewing behavior of op amp
To further illustrate this point, we present the following calculation.
As shown in Fig. 3, slewing is modeled by the limiting characteristic of the input differential pair of an amplifier [5]. Other than limiting, the feedback loop is linear with a constant feedback factor β which is frequency independent. A common method to calculate slewing time is to assume a limiting voltage of the diff. pair, VT, which is
I
defined as -----o- according to the simplified piece-wise linear model. Io is the maximum output current that can be
g
m
delivered to the load. By looking at the input of the diff. pair, we observe that the amplifier is slewing (f/b loop is
open) between time 0 and ts when Vx > VT. Settling time can be calculated following some simple algebra [5].
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EE240, Spring 2000
Final Project Report
Here, however, we propose a simpler method calculating the slewing time which observes the amplifier output
instead of the input. A slew-rate limited settling will not enter “linear region” until the output voltage reaches certain level where the instant slew-rate of a non-slewing settling with the same time constant (curve (1) in Fig. 4)
equals the actual slew-rate of the amplifier. t1 is the time for this to occur. This in turn indicates that t2 is the time
when the amplifier gets out of slewing (t2 is equivalent to ts in Fig. 3). If we express the exponential settling as
t
– --

τ
V o ( t ) = V o  1 – e  , for t ≥ 0 ,


we obtain,
V oC
CLV o
t 1 = τ ⋅ ln  -------------- ⇒ t 2 = -------------L- – τ ,
 I⋅τ 
I
[t – (t2 – t1)]
hence
– -------------------------------

τ
V o(t ) = 1 – e
 , for t ≥ t 2 .


To
settle to an accuracy of ---1 , the settling time with slewing present is,
A
V oCL
V oCL
t settle =  -------------- – τ – τ ⋅ ln  -------------- + τ ⋅ ln A
 I⋅τ 
 I

Using the square-law model, we can easily derive the minimum biasing current needed,
V oCL
V gt
2βV o
V gt
V gt 
- – ------------- ln  ------------- + ------------- ln A
I d, min = --------------  1 – -----------t settle 
2βV o 2βV o  V gt  2βV o
where, V gt = V gs – V th
Settling Time vs. Slewing
1600
Vo(t)
1400
(1)
curve saturates at low (Vgs-Vth)
due to gm saturation in weak
inversion region
1200
d
Min. Biasing Current I (uA)
(2)
t1
t2
1000
800
time
600
Curve (1): linear settling; Curve (2):
slewing followed by linear settling
400
200
0
100
200
300
400
500
600
700
V −V (mV)
gs
th
Figure 4 Minimum biasing current calculation with slewing present
The result is plotted in Fig. 4. The plot shows that, with the “help” of slewing, a much lower biasing current is
enough to achieve the settling speed (in contrast to a purely exponential settling that requires a minimum biasing
current of about 1.6 mA per transistor as calculated in section 2.4). Note that a few assumptions are made before
we reach this conclusion (square law, constant β). In reality, the curve tends to saturate at lower current end
because gm saturates when the device is pushed towards weak inversion region. Also, larger input capacitance associated with larger input device size reduces f/b factor, therefore reduces the loop bandwidth (and the loop-gain).
Lastly, we summarize by listing the pros and cons associated with using small Vdsat for input transistors,
• Using small overdrive hence large device size results in better matching and lower Flicker noise for the
input diff. pair, which is often advantageous. According to [3], we have the variance of the output current mismatch of the input diff. pair expressed as,
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EE240, Spring 2000
Final Project Report
2
2
2
2
σ (Id)
4σ ( V T 0 ) σ 2 ( β )
4 A VT 0 A β
- ≈ -------- ⋅ --------------------------- = ----------------------- + ------------- + -------2
2
2
2
β
V gt WL WL
Id
V gt
where AVT0 and Aβ are process related constants. For fixed tail current Id and device gate length L, the first term in
the expression is kept constant as we increase W. But the second term diminishes for large W. Therefore we achieve
better matching by using smaller overdrive for the diff. pair.
• Loop gain bandwidth product is βωu = βgm/CL. Small overdrive leads to larger bandwidth with fixed
biasing current. But excessive slewing usually results in the cascode transistors being cut off during large transients. Therefore it is one thing to watch out because this may lead to ringing (yet not observable in AC analysis).
• Noise factor N is a strong function of the Vdsat of the input devices. A smaller Vdsat of the diff. pair produces
a smaller N, therefore minimizes output noise with fixed CL.
• The 2nd pole frequency pushes in and the stability suffers as the diff. pair puts more cap. on current folding
nodes. Feedback factor β also decreases as a result of larger input parasitics, hence reduces speed and loop-gain.
Lack of analytical model of gm in the operation range close to weak inversion, the optimum sizing for the input
transistors is largely determined by HSPICE simulation.
3.3. Pole-Zero Doublet and Slow Settling
Settling time to certain accuracy is usually very critical to the performance of sampled data systems. The timedomain response of a single pole amplifier shows a single time constant exponential settling behavior without overshoot or ringing. Settling accuracy within specified time window is therefore easily identified and well predictable.
So, this is the ideal settling behavior a good designer is after (not the one with 60o phase margin, which is usually
not a robust design).
Although gain-boosting technique is able to achieve extremely large DC gain, it does not come in free. K. Bult
and G. Geelen [2] first analyzed the pole-zero doublet and the slow settling behavior inherent to the CMOS gainboosting architecture. They proposed the following heuristic for optimizing the settling behavior,
βω u < ω add < ω p2
where, βωu is the closed-loop dominant pole frequency, ωu is the open-loop unity-gain frequency, ωadd is the
unity-gain frequency of the boosting amplifier and ωp2 is the 2nd pole frequency of the main amplifier (also the
2nd pole of the local gain-boosting loop).
To better understand the pole-zero doublet and its effect on slow settling behavior, a small-signal frequency
domain analysis of the gain-boosting technique is performed. For the complexity of this analysis, the details are not
presented here. But some important conclusions drawn from the analysis are stated below,
1) As shown in Fig. 5, pole-zero doublet not only introduces slow settling component, it can also cause overshoot. The settling behavior is categorized into 3 cases depending on the pole/zero frequencies and their interaction
with the main amplifier.
2) For typical situations encountered in CMOS gain-boosting cases, slow settling component always starts
from the original gain Ao (not possible to obtain an “accurate” doublet). The time constant of the slow settling component, is determined by the doublet frequency. The solution proposed by K. Bult and G. Geelen essentially is to
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EE240, Spring 2000
Final Project Report
time (s)
0
(c)
Ao
Aadd
Atot
Out
Cc
(b)
Ref
(a)
gain (dB)
In
(a) critically damped, (b) under-damped,
and (c) over-damped (slow settling)
Cp
Figure 5 Settling behavior of pole-zero doublet and Cc compensation
push the doublet frequency beyond the close-loop dominant pole frequency of the amplifier (“fast” doublet).
Therefore, slow settling is not slow anymore!
In high-speed designs with deep feedback, βωu is often not much smaller than ωp2. Therefore, optimizing the
unity-gain bandwidth of the gain booster becomes difficult. A technique used by Bult and Geelen [2] is to place a
small capacitor (usually a MOS cap.) Cc at the output of the booster to fine-tune ωadd, as shown in Fig. 5. This
technique is implemented in this design. However, it needs to be pointed out that the final design should be insensitive to the value of Cc. This is an essential part of the verification process. In our design, large variations of Cc is
forced to monitor its impact on the settling behavior of the OTA.
3.4. Minimizing Feedforward Zero Effect
Capacitive f/b network provides a feedforward path for input signal to bypass the OTA. Since the f/b is negative, an instant input jump introduces a big spike at the output which is, unfortunately, to the opposite side of the
final output voltage. A straightforward calculation yields the following expression for this spike,
Cf
∆V o = V o ⋅ β ⋅ -------------------C f + CL
Since the f/b factor is largely fixed by the closed-loop gain, the only parameter we have control on to minimize
the initial spike is the ratio CL/Cf. Therefore, after the total load capacitance is determined by noise calculation, we
can partition this capacitance between Cs, Cf, and CL in favor of a smaller spike. But too small Cs and Cf will also
reduce the f/b factor hence reduce the settling speed. Since this expression does not offer a minimum, the optimum
value is determined through HSPICE simulation. It is found that with a > 4:1 ratio of CL/Cf, the feedforward zero
effect is negligible.
4. HSPICE SIMULATION AND VERIFICATION
In this section, we first summarize the performance achieved by the final design and then we will present the
implementation details, optimization procedures, and the verification of design for robustness.
4.1. Overall Performance Summary
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EE240, Spring 2000
Final Project Report
The following corner conditions are used in verification of the OTA design. For commercial products, usually
temperature varies from 0oC to 75oC. These are combined with process variations to derive the worst case scenarios. For example, highest temperature gives rise to the highest thermal noise figure. Combined with the slow process parameters (which runs into headroom problems due to large Vth), it places the toughest test on the dynamic
range performance. This is also the corner for lowest speed. On the contrary, the fast process corner combined with
low temperature will probably introduce stability problem.
Table I Corner conditions used for design verification
Process variation
Typical
Slow
Fast
Temperature variation
25oC
75oC
0oC
Table II summarizes the achieved performance of the fully differential gain-boosted OTA. Table III lists the
chosen component values. The design specs are met throughout the corner conditions. Worst case power consumption including bias is 7.81 mW. Table IV summarizes all device operating point conditions for the OTA. It is generated by HSPICE simulation.
Table II Fully diff. gain-boosted OTA performance summary
Performance Metric
Typical, 25oC
Diff. Output Voltage Swing (peak-to-peak)
Slow, 75oC
Fast, 0oC
4.5 V
RMS Output Noise (1 Hz to 100 GHz)
49.15 µV
50.14 µV
46.12 µV
RMS Output Noise (w/o gain-boosting)
40.43 µV
44.20 µV
39.26 µV
Output Dynamic Range
90.2 dB
90.0 dB
90.8 dB
Large-Signal ADC (Vo,pp = 0 V)
87.4 dB
87.7 dB
84.7 dB
Large-Signal ADC (Vo,pp = 4.5 V)
86.4 dB
85.8 dB
84.1 dB
Small-Signal AV (Vo,pp = 0 V)
87.4 dB
87.7 dB
84.7 dB
Small-Signal AV (Vo,pp = 4.5 V)
79.5 dB
72.8 dB
80.3 dB
Diff. Loop-Gain (Vo,pp = 0 V)
82.9 dB
83.7 dB
79.9 dB
80.0o
83.2o
80.6o
96.0 MHz
87.5 MHz
106.1 MHz
50.5 dB
50.6 dB
49.2 dB
88.2o
88.3o
88.8o
35.6 MHz
33.4 MHz
42.7 MHz
Settling Time (Vo = +1 V up to Vo,max)
19.4 ns
18.8 ns
16.3 ns
Settling Time (Vo = -1 V down from
18.0 ns
16.8 ns
15.4 ns
Diff. Loop Phase Margin (Vo,pp = 0 V)
Diff. Loop Unity-Gain BW (Vo,pp = 0 V)
C.M. Loop-Gain (Vo,pp = 0 V)
C.M. Loop Phase Margin (Vo,pp = 0 V)
C.M. Loop Unity-Gain BW (Vo,pp = 0 V)
Settling Accuracy
Total Power Consumption
< 0.05%
7.79 mW
10
7.81 mW
7.76 mW
EE240, Spring 2000
Final Project Report
Table III Component values
Cs
Cf
CL
Ccmfb
Ib,master
0.5 pF
2 pF
7 pF
0.6 pF
50 µA
Table IV Transistor biasing condition
Device Name
Id (A)
gm (A/V)
gm/Id (V-1)
Device Name
Id (A)
Main OTA
gm (A/V)
gm/Id (V-1)
P-side Booster
NIP
400u
8.18m
20.45
NIL, NIR
80u
1.74m
21.75
NIN
400u
8.18m
20.45
PBL, PBR
160u
737u
4.61
NBB
800u
4.62m
5.78
PCL, PCR
80u
892u
11.15
NBC
800u
13.09m
16.36
NBL, NBR
80u
622u
7.78
PBP
800u
5.38m
6.73
NCL, NCR
80u
638u
8.0
PBN
800u
5.38m
6.73
NCM
80u
1.69m
21.12
PCP
400u
5.72m
14.3
PCN
400u
5.72m
14.3
PIL, PIR
40u
618u
15.45
NBP
400u
2.20m
5.5
PBL, PBR
40u
315u
7.88
NBN
400u
2.20m
5.5
PCL, PCR
40u
323u
8.08
NCP
400u
6.38m
15.95
NBL, NBR
80u
365u
4.56
NCN
400u
6.38m
15.95
NCL, NCR
40u
444u
11.1
PCM
40u
598u
14.95
N-side Booster
Main OTA
In Table II, two types of DC gains are differentiated. One is called the
large-signal DC gain (ADC) and the other small-signal DC gain (AV). As shown
in Fig. 6, large-signal gain ADC refers to the slope of the straight line that runs
through an operating point on the voltage transfer curve (VTC) and the origin.
The small-signal gain AV is defined as the local derivative of the VTC curve.
ADC is usually larger than AV because the VTC generally exhibits limiting
characteristics. Both of these gains are simulated. We want to point out that,
the settling accuracy is dictated by ADC, not AV, as a straightforward calculation may prove this. It is this important observation that leads to the appropriate (not excessive) sizing of the cascode transistors.
AV
Vout
ADC
0
Vin
Figure 6 ADC vs. AV
Also, in simulating the common-mode f/b loop characteristics, we did not connect the OTA input to an AC
ground. Instead, we put the differential f/b network on and fully functional. It is believed that this is the most accurate representation of the loop behavior. First, common-mode loading due to capacitive f/b network is precisely
modeled. Secondly, due to finite output resistance of the cascode tail current source, the common-mode response of
the diff. f/b loop is not negligible and it degenerates the loop-gain of the common-mode f/b loop. The c.m. openloop gain shown in the table is about 50 dB instead of 70 dB, the number measured when diff. f/b loop is disabled.
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EE240, Spring 2000
Final Project Report
4.2. Biasing
High swing cascode biasing is used for the main amplifier and the gain boosters. A lot of effort is invested to
this part of the design in order to maximize the output swing yet to make the design robust over process variations.
Transistor sizes are kept strictly scaled in all biasing circuits. This minimizes the systematic mismatch error. Wide
transistor are broken into finger structures in order to make biasing circuit easily scalable and layout friendly.
The available about 0.4-V headroom on both the PMOS and NMOS sides are optimally partitioned between
the current source and the cascode transistors. The optimization involves the following thinking,
• Large Vdsat for current sources minimizes the noise factor because they are the dominant noise contributors
beside the input diff. pair. This is especially true for the P-side since two PMOS FETs conduct double current
therefore have doubled noise factor.
• A smaller Vdsat for cascode transistors increases their gm therefore increases the 2nd pole frequency. It can be
shown that the 2nd pole is optimized when the cascode contributes half of the total cap. at the cascoding node
(assuming square law).
• The optimization is guided with a reasonable headroom of about 100-300 mV per transistor. Excessive scaling in order to maximize output swing is not wise. Pushing too far into weak inversion will increase parasitic
capacitance therefore lose speed and phase margin.
In this design, all tail current sources are realized using cascode structures as well. This increases the ro of current sources therefore increases the common-mode rejection ratio. With a folded-cascode structure for both the
main amplifier and the boosters, tail current source biasing can be shared with the high-swing cascode biasing,
therefore saves design effort and improves matching.
Table V Power consumption breakdown
Total Power
Main OTA
P Gain-Booster
N Gain-Booster
Biasing
7.8 mW
4.8 mW
1.2 mW
0.6 mW
1.2 mW
Table V summarizes the power consumption breakdown of the OTA. A single 50-µA master biasing current is
assumed available and long channel cascode current mirrors (we do use long channel devices sometimes) are used
to distribute copies of this current into the amplifier and the boosters. It is essential that only current (not voltage)
are distributed to bias the amplifier. This improves the robustness of the biasing network. No effort is attempted in
order to excessively minimize the biasing circuitry power consumption. Under high-speed operation, due to capacitive coupling, biasing circuits also require enough bandwidth to settle. Therefore, it is not appropriate to shrink the
biasing circuit excessively in order to save power. A rule of thumb is not to use a ratio higher than 5:1 for highspeed design. Minimal times of copying of the master current is desired in order to reduce inaccuracy in mirroring
due to channel length modulation effect (actually, we only mirror it once).
4.3. Choice of Architecture
NMOS input folded-cascode structure is chosen in order to minimize the virtual ground parasitics that reduces
f/b factor. Since Flicker noise is negligible in this design, using PMOS input does not gain on noise performance.
The lower mobility of PMOS FETs leads to about 3 times larger parasitics at input and also 3 times larger miller
capacitance. Although NMOS diff. pair is susceptible to body effect in an N-well process therefore has worse common-mode rejection ratio, they are large and can be very carefully laid out to minimize the mismatch. It is concluded that NMOS input is preferable for high-speed applications.
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EE240, Spring 2000
Final Project Report
PMOS side gain booster has to accommodate high (close to VDD) input common-mode voltage. So it is chosen as an NMOS input folded-cascode structure as well. For the NMOS side booster, the situation is exactly the
other way around. So a PMOS input folded-cascode structure is chosen. Biasing boosters is much easier than the
main amplifier because they exhibits much smaller output swings. The available headroom is further exploited to
minimize the noise factor of the current source transistors inside the booster.
4.4. Common-Mode Control
Dynamic switched-capacitor output common-mode control circuit is implemented due to its simplicity, ease to
design, low power consumption, and linearity. The c.m. control point is set to the N-side for the following thinking,
• N-side is the only place to put c.m. f/b control so that the common-mode f/b loop has the minimum overlap
with the differential signal path, which goes through the PMOS side.
• N-side cascode structure has a higher 2nd pole frequency than that of the P-side, this improves the commonmode f/b loop stability.
By using the “UIC” option in transient and AC simulations, we are able to initialize the switched-cap c.m f/b
network. This is important because an ideal model for c.m. f/b control is simply inadequate to verify the actual performance of the circuit. Three cases, the ideal VCVS c.m. f/b, the switched-cap c.m. f/b, and the switched-cap c.m.
f/b with 1-pF loop-gain attenuation cap., are compared in transient simulation. C.m. f/b loop is very stable (almost
90o phase margin) and no effect on diff. signal settling is observed.
Fully differential gain boosters are ideal for improving noise performance. However, they need common-mode
control as well. Switched-capacitor c.m. f/b circuit used for the main amplifier is cumbersome to use here because
the boosters are a lot smaller and therefore only require tiny c.m. f/b caps. What is more troublesome is switches
are not infinitesimal. The charge injection introduced by the switch for small capacitors will dominate the error of
common-mode control accuracy. So, we use an input controlled c.m. f/b circuit instead. It is continuous time hence
not prone to switching errors. Since the power consumption of the boosters is much less than the main OTA, burning an extra DC current for the c.m. f/b transistor does not add much to the power budget. The c.m. f/b loop bandwidth can be easily controlled by sizing the c.m. f/b transistor. The same size as the input diff. pair yields a c.m. f/b
loop bandwidth 1/3 of that of the differential loop.
4.5. Optimizing Performance of Gain-Boosting
The pole-zero doublet can introduce slow settling. It is therefore important to optimize the bandwidth of the
booster to obtain optimum performance. The unity-gain frequency of the booster can not be less than βωu. But it
can not be too higher than it as well for the stability consideration of the gain-boosting loop (the 2nd pole of the
main amplifier is also the 2nd pole of the gain-boosting loop). MOS cap. is implemented as Cc, the fine tuning cap.,
in order to track process variation. If even higher settling speed is required, it will be harder to design with gainboosting technique. A pole isolation technique was proposed by Y. Chiu [6] which can be used in such situations to
improve the performance and robustness of the conventional gain-boosting technique.
For the noise perspective, large bandwidth of the booster (with small load capacitance) will increase its excessive noise contribution. Furthermore, since gain boosters are usually small (they only need to drive the cascode gate
cap.), noise contribution from them is enhanced. Therefore, to design for low-power consumption, optimizing the
bandwidth of the booster is essential. Fortunately, the Cc technique introduced by K. Bult is useful here. Thanks to
the use of minimal channel length for the cascode transistors, the optimization process is not challenging since the
2nd pole is far out in the giga-hertz range.
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EE240, Spring 2000
Final Project Report
It is also observed (Fig. 9) that low-frequency noise of the cascode transistor is suppressed by the gain-boosting
loop. At higher frequencies, the loop-gain drops and the suppression diminishes gradually. This is the main reason
that the noise floor of the cascode device shows a “hump” at high frequency. The total integrated noise of cascode,
however, remains largely the same.
In summary, we achieved relatively low output noise (about 20%-30% of the total output noise power) of the
gain boosters without burning a lot of power for them. The slow settling component is pushed beyond the dominant
pole frequency of the main OTA. With 100% variation of the absolute value of Cc, the settling speed remains the
same, and the slow settling component is consistently suppressed.
4.6. Noise Breakdown
In Fig. 8, the output noise floor and the integrated output noise power are plotted using HSPICE. The major
noise contribution arises from the input diff. pair, the PMOS current sources, and the NMOS current sources. Cascode devices and gain boosters contribute less but not negligible output noise power.
5. CONCLUSION
A fully differential gain-boosted CMOS operational transconductance amplifier is designed and simulated
using HSPICE. The low-power, low-voltage, high-speed analog design techniques introduced in this report greatly
facilitates in optimizing the design of this OTA, both for performance and for robustness. All design specs have
been achieved with a low power consumption of 7.8 mW. Gain-boosting technique is analyzed and improvement
on performance is observed with a better understanding of pole-zero doublet effects. The design is verified
throughout process corners and temperature variations and constant performance is observed. We conclude that
this architecture is suitable for high-speed, high-performance OTA’s used in on-chip switched capacitor applications.
6. REFERENCES
[1]
K. Bult and G. Geelen. "A fast-settling CMOS op amp with 90-dB DC gain and 116 MHz unity-gain
frequency," ISSCC Dig. Tech. Papers, Feb. 1990. pp. 108-109.
[2]
K. Bult and G. Geelen. "The CMOS gain-boosting technique," Analog Integrated Circuits and Signal
Processing, vol.1, (no.2), Oct. 1991. pp. 119-35.
[3]
Pelgrom, M.J.M.; Duinmaijer, A.C.J.; Welbers, A.P.G. "Matching properties of MOS transistors," IEEE
Journal of Solid-State Circuits, vol.24, (no.5), Oct. 1989. p.1433-9.
[4]
Razavi, Behzad. "Design of analog CMOS integrated circuits," [Preview ed.]. McGraw-Hill, c2000.
[5]
Kamath, B.Y.T.; Meyer, R.G.; Gray, P.R. "Relationship between frequency response and settling time of
operational amplifiers," IEEE Journal of Solid-State Circuits, vol.SC-9, (no.6), Dec. 1974. p.347-52.
[6]
Y. Chiu, "Improved CMOS Gain-Boosting Scheme using Pole Isolation Technique," US patent pending,
application serial No. 09/200,180.
14
Figure 9 Low-freq. noise of cascode transistors is
suppressed by gain-boosting loop
cascode xtor noise
gain-boosting f/b
loop has large b/w
Figure 7 ADC (bottom) vs. AV (top)
max. output swing = 4.5V
7. APPENDIX. SIMULATION RESULTS
gain-boosting f/b
loop has small b/w
EE240, Spring 2000
15
Wave
Symbol
Symbol
0
100x
1g
Frequency (log) (HERTZ)
0
2u
gain-boosting f/b
loop has large b/w
10g
100g
100g
Effect of gain-boosting loop b/w on noise
gain-boosting f/b
loop has small b/w
Figure 10
pmos cascode
pboost noise
nmos current source
pmos current source
input diff. pair
10g
nboost noise
100x
1g
Frequency (log) (HERTZ)
integrated output noise breakdown
nmos cascode
10x
10x
p/nmos cascode
4u
1x
1x
nboost noise floor
pboost noise floor
nmos current source
most of output noises
come from input diff.
pair and P/N current
sources
output noise spectrum density breakdown
pmos current source
input diff. pair
Final Project Report
6u
8u
10u
12u
14u
16u
18u
20u
22u
500e-21
1e-18
1.5e-18
2e-18
2.5e-18
3e-18
Figure 8 Output noise breakdown
gain-boosting amps
contribute about
20-30% total output
noise power
D0:A0:nboo
D0:A0:pboo
D0:A0:nnc
D0:A0:npc
D0:A0:nn
D0:A0:np
D0:A0:nin
Wave
D0:A0:onoise(5:mnir)
D0:A0:onoise(4:mpil)
D0:A0:onoise(3:mncp)
D0:A0:onoise(3:mpcp)
D0:A0:onoise(3:mnbp)
D0:A0:onoise(3:mpbp)
D0:A0:onoise(3:mnip)
Noise Sq-V/Hz (lin)
Result (lin)
unity-gain freq.
20-ns time limit
linear settling
Figure 13 Transient gain (top) and diff. output
voltage (down) of up-going settling
error
bound
slewing
Figure 11 Differential loop-gain and phase margin
EE240, Spring 2000
16
Figure 14 Voltage waveforms at output and
virtual ground of up-going settling
Figure 12 Switched-cap. common-mode f/b
loop-gain and phase margin
unity-gain freq.
Final Project Report
linear settling
20-ns time limit
slewing
switched-cap. cmfb
w/ 1-pF attenuation
Figure 17 Common-mode (down) settling of up-going transition
ideal VCVS cmfb
switched-cap. cmfb
c.m. settling has no
observable effect on
diff. mode settling
Figure 15 Transient gain (top) and diff. output
voltage (down) of down-going settling
error
bound
EE240, Spring 2000
17
switched-cap. cmfb
w/ 1-pF attenuation
Figure 18 Common-mode (down) settling of down-going transition
ideal VCVS cmfb
switched-cap. cmfb
c.m. settling has no
observable effect on
diff. mode settling
Figure 16 Voltage waveforms at output and
virtual ground of down-going settling
Final Project Report