J
®
Power ISA™ Version 3.0
Programming Model
Bulletin
May 10, 2016
IBM Hardware Support Documentation
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Printed in the United States of America May, 2016
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ii
Power ISA v3.0 Programming Model Bulletin
IBM Hardware Support Documentation
The following changes are made to the Power ISA v3.0 (November 30, 2015) specification.
1.
The following three instructions are withdrawn from the architecture, and the opcodes assigned to these instructions are returned to the available pool of opcodes.
VSX Scalar Compare Not Equal Double-Precision (xscmpnedp)
VSX Vector Compare Not Equal Double-Precision (xvcmpnedp)
VSX Vector Compare Not Equal Single-Precision (xvcmpnesp)
Instruction sequences using these instructions can be replaced with equivalent or near-equivalent sequences. For
example, the C conditional operator (x!=y)?a:b can be implemented using xscmpeqdp-xxsel in the form,
(x==y)?b:a, by reversing the order of the a and b operands in the xxsel instruction.
2.
The Vector Shift Left (vsl) and Vector Shift Right (vsr) instructions require the shift count to be replicated in every
byte of the Vector Register providing the shift count. Therefore, a Vector Splat Byte (vspltb) instruction should be
inserted prior to the vsl and vsr instructions in the instruction sequence in the Programming Note on page 264, as
follows,
vslo
vspltb
vsl
Vz,Vx,Vy
Vy,Vy,15
Vz,Vz,Vy
and in the instruction sequence in the Programming Note on page 267, as follows.
vslo
vspltb
vsl
vsububm
vsro
vspltb
vsr
vor
3.
Vt1,Vw,Vy
Vy,Vy,15
Vt1,Vt1,Vy
Vt3,V0,Vy
Vt2,Vx,Vt3
Vt3,Vt3,15
Vt2,Vt2,Vt3
Vz,Vt1,Vt2
# shift high-order reg left
# adjust shift count ((V0)=0)
# shift low-order reg right
# merge to get final result
The number of bytes (nb) to be loaded/stored by the Load VSX Vector with Length (lxvl) (page 490), Load VSX
Vector Left-justified with Length (lxvll) (page 492), Store VSX Vector with Length (stxvl) (page 508) and Store
VSX Vector Left-justified with Length (stxvll) (page 510) instructions is clamped to 16 if the value in byte 0 of
GPR[RB] is greater than 16. The RTL for the instructions should also include this clamping function by adding the
new statement
if nb>16 then nb ← 16
after the existing statement
nb ← EXTZ(GPR[RB].bit[0:7])
in each of these instructions’ RTL description.
Power ISA v3.0 Programming Model Bulletin