EMI Modeling and Characterization for Ultra-Fast Switching
Power Circuit Based on SiC and GaN Devices
DISSERTATION
Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy
in the Graduate School of The Ohio State University
By
Kaichien Tsai
Graduate Program in Electrical and Computer Science
The Ohio State University
2013
Dissertation Committee:
Dr. Longya Xu, Advisor
Dr. Jin Wang
Dr. Mahesh S. Illindala
© Copyright by
Kaichien Tsai
2013
Abstract
Electromagnetic interference (EMI) has been a well known problem ever since
the introduction of Silicon (Si) based BJT, MOSFET, and IGBT.
EMI noise is
unavoidable due to breaks in the current and voltage generated by the switching actions
of semiconductor devices. The noise is transmitted in the form of conducted and radiated
emission through conductors and radiation. The advancement of Wide Band-gap (WBG)
devices such as Gallium Nitride (GaN) transistors and Silicon Carbide (SiC) BJT and
MOSFET have allowed designers to achieve higher power density and efficiency of
circuits by utilizing the ultra-fast switching frequency, speed, and the ability to operate at
a larger range of temperatures. As the result of the more compact design, EMI control in
electronic circuits has become more challenging with regard to functional issues,
operational robustness, increased cost, thermal, and space constraints.
Due to the superior switching abilities of WBG devices, inductor-less circuit
topologies, such as switched-capacitor circuits are drawing quite a bit of attention. The
Common Mode (CM) noise inherent in these types of circuits is severe due to the rapid
change of node voltages. The CM noise current is created by combining the parasitic
impedance between the node and the common reference plane. The CM choke in EMI
filters is used to suppress CM noise while preserving the differential signals.
The
PSPICE model is proposed to evaluate and predict the performance of the CM choke the
ii
accuracy of which is verified up to 100MHz. In addition, we analyzed the grounding of
the Y-capacitor's ability to effectively muffle CM noise.
Many researchers have identified the fast transients of dv/dt and di/dt with various
parasitic components which contribute to major conducted noise in pulse width
modulation (PWM) controlled converters and inverters. To predict the conducted noise
emission level, it is essential to identify the electronic circuit at the initial design stage. A
circuit modeling procedure and transient analysis in PSPICE are demonstrated using a
GaN based switched-capacitor circuit to predict and identify the noise generated by the
CM and transmission paths. We proposed improvements to reduce the CM noise based
on the derived CM noise equivalent circuits, which were verified in both the computer
simulation and experimental testing.
In addition to the conducted noise emission in the power line, we also investigated
the noise problem due to electromagnetic field coupling within the SiC BJT based three
phase inverter system. We also identified the known and potential problems in power
circuits, gate drive, and control board during high power operation in the experiment.
Some practical noise mitigation techniques for each sub-system are proposed and verified
in both computer simulation and experimental testing.
iii
Dedication
This document is dedicated to my family and all the people that I love.
iv
Acknowledgments
I would like to express my deepest gratitude to my PhD advisor, Dr. Longya Xu,
who has consistently provided academic guidance and funding support throughout my
graduate study career. His immense knowledge, insightful research, and great patience
have inspired and helped me to develop independent and creative thinking skills, which
will benefit me throughout my entire life. I also want to thank my advisor for providing
me with many wonderful projects and opportunities to explore the area of motor drive
control, power electronic applications, and EMI. Without his unwavering guidance,
encouragement, and precision, this dissertation would not have been possible.
I also want to thank Dr. Jin Wang, Dr. Donald Kasten, Dr. Steven Sebo, Dr.
Vadim Utkin, and Dr. Mahesh S. Illindala for their numerous useful discussions, advice,
and ideas, which were all very beneficial to my graduate career over the past few years. I
would like to give my special thanks to Dr. Chingchi Chen from Ford for his guidance
and suggestions for my EMI study.
In addition, I would like to thank Dr. Minghua Fu, Dr. Xiaolin Lu, and Smart Grid
team from Texas Instruments for providing thought provoking and challenging research
projects and the opportunity to gain industry experience while working as an intern.
I want to thank Dr. Julia Zhang, who is currently an Assistant Professor at Oregon
State University as well as a senior fellow student, Mr. Bo Guan, for their help to my
v
course work, research, and numerous discussions. I will always remember the days and
nights we spend together in the lab. I also want to thank my junior group members Mr.
Mark Scott, Mr. Zhendong Zhang, Mr. Yu Liu, Mr. Haiwei Cai, Mr. Dakai Hu, Mr. Feng
Qi, Mr. Ernest Davidson, Dr. Ke Zou, Mr. Feng Guo, Mr. Cong Li, Mr. Lixing Fu, Mr.
Jinzhu Li, Ms. Xiu Yao, Mr. Luis Herrera, Mr. Xuan Zhang, Mr. Chengcheng Yao, Mr.
Da Jiao, and Ms. Pu Xu for their friendship, help and support during the happy and
challenging days over the past six years.
vi
Vita
July 2007 ........................................................B.S Electrical and Computer Engineering,
The Ohio State University
Sept. 2007 to present ......................................Ph.D student, The Ohio State University
Publications
[1]
Kaichien Tsai; Longya Xu; Feng Qi; Ernest Davidson; , "Common Mode EMI
Noise Characterization and Improvement of a Gallium-Nitride SwitchedCapacitor Circuit," Energy Conversion Congress and Exposition (ECCE), 2013
IEEE
[2]
Longya Xu; Bo Guan; Huijuan Liu; Le Gao; Kaichien Tsai; , "Design and control
of a high-efficiency Doubly-Fed Brushless machine for wind power generator
application," Energy Conversion Congress and Exposition (ECCE), 2010 IEEE ,
vol., no., pp.2409-2416, 12-16 Sept. 2010
Fields of Study
Major Field: Electrical and Computer Engineering
vii
Table of Contents
Abstract ............................................................................................................................... ii
Acknowledgments............................................................................................................... v
Vita.................................................................................................................................... vii
Publications ....................................................................................................................... vii
List of Tables ..................................................................................................................... xi
List of Figures ................................................................................................................... xii
Chapter 1: Introduction ...................................................................................................... 1
1.1
Introduction to EMC and EMI ............................................................................. 1
1.2
Literature Review ................................................................................................. 6
1.3
Motivation of The Work .................................................................................... 10
1.4
Chapter Preview ................................................................................................. 11
Chapter 2: Passive Device High Frequency Modeling .................................................... 13
2.1
Introduction ........................................................................................................ 13
2.2
Methods of Impedance Measurement and Limitations ...................................... 14
2.3
CM Choke Modeling.......................................................................................... 15
2.3.1
CM Inductance LCM Extraction................................................................... 17
2.3.2
Leakage Inductance Lleakage Extraction ....................................................... 19
2.3.3
Impedance Z1 Determination ...................................................................... 22
2.4
CM Choke PSPICE Implementation and Verification ....................................... 26
2.5
Capacitor and DM Inductor Modeling ............................................................... 30
2.6
Study of the EMI Filter Grounding Effectiveness for CM Noise ...................... 31
viii
2.6.1
Effects of a Common Grounding Path ........................................................ 33
2.6.2
Effects of Mutual Coupling Between Two Grounding Paths ..................... 35
2.7
Computer Simulation and Experimental Testing ............................................... 37
2.7.1
Simulation Result ........................................................................................ 37
2.7.2
Experimental Results .................................................................................. 40
2.8
Summary ............................................................................................................ 43
Chapter 3: Active Device High Frequency Circuit Modeling ......................................... 44
3.1
Introduction ........................................................................................................ 44
3.2
CM Noise Circuit Modeling of Voltage Doubler Converter.............................. 45
3.2.1
Operating Principle ..................................................................................... 45
3.2.2
High Frequency CM Noise Circuit Modeling ............................................ 47
3.2.3
Circuit Model Verification .......................................................................... 50
3.3
Common Mode Noise Analysis ......................................................................... 52
3.3.1
Equivalent Circuits...................................................................................... 52
3.3.2
The Concept of Circuit Balance .................................................................. 54
3.4
Computer Simulation and Experimental Testing ............................................... 57
3.4.1
Simulation Results ...................................................................................... 57
3.4.2
Experimental Results .................................................................................. 61
3.5
Summary ............................................................................................................ 65
Chapter 4: Electromagnetic Interference in Power Electronics ....................................... 67
4.1
Introduction ........................................................................................................ 67
4.2
Power Circuits .................................................................................................... 69
4.2.1
Power Device Test Setup ............................................................................ 69
4.2.2
PCB Layout Considerations ........................................................................ 71
ix
4.3
Gate Drive Circuits............................................................................................. 77
4.4
Control Circuits .................................................................................................. 92
4.5
Summary .......................................................................................................... 108
Chapter 5: Conclusion and Future Work ....................................................................... 109
5.1
Conclusion........................................................................................................ 109
5.2
Future Work ..................................................................................................... 112
Appendices ...................................................................................................................... 114
Appendix A:
Impedance of Capacitors ................................................................... 114
Appendix B:
Transmission Line Effect................................................................... 116
Appendix C:
Capacitive Coupling Mechanism....................................................... 120
Appendix D:
Magnetic Coupling Mechanism......................................................... 123
Appendix E:
Selecting Dielectric Material for IMS ............................................... 125
Appendix F:
List of Principle Symbols .................................................................. 128
References ....................................................................................................................... 130
x
List of Tables
TABLE 1.1 PROPERTIES OF SI, GAN, AND SIC DEVICE.......................................................... 9
TABLE 2.1 FIVE CASES FOR EMI FILTER GROUNDING ANALYSIS ........................................ 38
TABLE 3.1 Q3D SIMULATION OF EACH TRACE.................................................................... 49
TABLE 3.2 STRAY INDUCTANCE IN THE VOLTAGE DOUBLER CIRCUIT ................................. 49
TABLE 4.1 EXTRACTED SELF AND MUTUAL INDUCTANCE OF TEST SETUP IN FIGURE 4.34 105
xi
List of Figures
FIGURE 1.1 BLOCK DIAGRAM OF NOISE PROPAGATION PATH ................................................ 2
FIGURE 1.2 TEST SETUP FOR CONDUCTIVE NOISE MEASUREMENT ........................................ 3
FIGURE 1.3 IMPEDANCE BETWEEN EUT PORT AND REFERENCE GROUND ............................. 4
FIGURE 1.4 SIMPLIFIED HIGH FREQUENCY MODEL OF CONDUCTIVE NOISE MEASUREMENT .. 4
FIGURE 1.5 COMPLETE CONDUCTED NOISE TEST SETUP........................................................ 5
FIGURE 2.1 ONE STAGE EMI FILTER .................................................................................. 14
FIGURE 2.2 (A) STRUCTURE OF CM CHOKE, (B) HIGH FREQUENCY CIRCUIT MODEL OF CM
CHOKE ........................................................................................................................ 16
FIGURE 2.3 EQUIVALENT CIRCUIT OF ZCM MEASUREMENT ................................................. 18
FIGURE 2.4 IMPEDANCE FOR LCM, EPC, AND EPR EXTRACTION ........................................ 18
FIGURE 2.6 EQUIVALENT CIRCUIT FOR LLEAKAGE EXTRACTION ............................................ 21
FIGURE 2.7 IMPEDANCE FOR LLEAKAGE EXTRACTION ............................................................ 21
FIGURE 2.8 EQUIVALENT CIRCUIT FOR Z1 MEASUREMENT ................................................. 22
FIGURE 2.9 IMPEDANCE FOR Z1 EXTRACTION ..................................................................... 23
FIGURE 2.10 EQUIVALENT CIRCUIT FOR Z1 EXTRACTION WITH SHORTED CM CHOKE ........ 24
FIGURE 2.11 IMPEDANCE OF Z1 WITH SHORTED CM CHOKE ............................................... 25
FIGURE 2.12 LUMPED CIRCUIT MODEL FOR Z1/2 ................................................................ 25
FIGURE 2.13 CM CHOKE SPICE IMPLEMENTATION ........................................................... 27
FIGURE 2.14 CM
CHOKE SIMULATION RESULT IN
SPICE (A) ZCM, (B) ZDM, (C) Z1, (D) Z1
WITH WINDINGS SHORTED .......................................................................................... 28
FIGURE 2.15 INSERTION
LOSS OF
CM
VARIOUS SHUNT CAPACITANCES,
CHOKE WITH (A) FIXED
(B)
3.9MH CM
CHOKE AND
FIXED SHUNT CAPACITANCE AND VARIOUS
INDUCTANCES ............................................................................................................ 30
xii
FIGURE 2.16 CIRCUIT
MODELS FOR (A)
LDM=47µH, (B) CY2=100NF, (C) CY1=56NF, (D)
CX1=10µF .................................................................................................................. 31
FIGURE 2.17 CIRCUIT CONFIGURATION FOR CM NOISE GROUNDING ANALYSIS.................. 32
FIGURE 2.18 EQUIVALENT CIRCUIT OF ONE STAGE EMI FILTER FOR CM NOISE ANALYSIS. 32
FIGURE 2.19 EQUIVALENT CIRCUIT WITH A WIRE CONNECTING TO A REFERENCE FRAME ... 34
FIGURE 2.21 SIMULATION RESULT OF GROUNDING FOR (A) ORIGINAL EMISSION, (B) CASE 1,
(C) CASE 3, (D) CASE 2, (E) CASE 4, AND (F) CASE 5 .................................................... 39
FIGURE 2.22 DIAGRAM OF THE TEST SETUP FOR CM NOISE GROUNDING INVESTIGATION .. 41
FIGURE 2.23 CONDUCTIVE CM
NOISE EMISSION (A) WITHOUT
EMI
FILTER, (B) COMMON
GROUND WITH A SINGLE WIRE CONNECTION TO REFERENCE PLANE, (C) SEPARATE
GROUNDING PATHS WITH TWISTED WIRES, (D) ONLY
CY2 IS APPLIED IN THE FILTER, (E)
SEPARATE GROUNDING WITH LONG WIRES, (F) SEPARATE GROUNDING WITH SHORT
WIRE
.......................................................................................................................... 42
FIGURE 3.4 MODEL OF THE CERAMIC CAPACITOR FOR CIN, C1, AND C2 .............................. 48
FIGURE 3.5 COPPER TRACES OF THE VOLTAGE DOUBLER CONVERTER................................ 49
FIGURE 3.6 GAN
SOFT-SWITCHING VOLTAGE AND CURRENT WAVEFORMS FROM
(A)
SIMULATION AND (B) EXPERIMENT ............................................................................. 51
FIGURE 3.7 NOISE MODEL OF THE VOLTAGE DOUBLER ....................................................... 52
FIGURE 3.8 EQUIVALENT CIRCUIT OF NOISE V1 .................................................................. 53
FIGURE 3.9 EQUIVALENT CIRCUIT OF NOISE V2 .................................................................. 53
FIGURE 3.10 EQUIVALENT CIRCUIT OF NOISE V3 ................................................................ 53
FIGURE 3.11 EQUIVALENT CIRCUIT OF NOISE V7 ................................................................ 54
FIGURE 3.12 EQUIVALENT CIRCUIT OF NOISE V9 ................................................................ 54
FIGURE 3.13 WHEATSTONE BRIDGE CIRCUIT...................................................................... 55
FIGURE 3.14 TOTAL CM
NOISE IN TIME DOMAIN FOR (A) ORIGINAL CIRCUITRY, (B)
200PF
ADDED AT CA AND CN, (C) 10NF ADDED AT CL AND CE ............................................... 60
FIGURE 3.15 TOTAL CM NOISE IN FREQUENCY DOMAIN FOR (A) ORIGINAL CIRCUITRY, (B)
200PF ADDED AT CA AND CN, (C) 10NF ADDED AT CL AND CE .................................... 61
xiii
FIGURE 3.16 EXPERIMENTAL RESULT OF CM NOISE FOR (A) ORIGINAL CIRCUITRY, (B) 200PF
ADDED AT CA AND CN, (C) 10NF ADDED AT CL AND CE ............................................... 63
FIGURE 3.17 ORIGINAL CM NOISE FROM 100KHZ TO 30MHZ ........................................... 64
FIGURE 3.18 CM NOISE WHEN 200PF IS ADDED TO CA AND CN .......................................... 64
FIGURE 3.19 CM NOISE WHEN 10NF IS ADDED TO CL AND CE ............................................ 65
FIGURE 4.1 BLOCK
DIAGRAM OF A TYPICAL THREE PHASE INVERTER IN MOTOR DRIVE
APPLICATION .............................................................................................................. 68
FIGURE 4.3 T-CLAD CIRCUIT BOARD .................................................................................. 70
FIGURE 4.4 AN EXAMPLE OF LAMINATED DC BUS BAR ...................................................... 72
FIGURE 4.5 RELATIONSHIP OF MAGNETIC FLUX IN LAMINATED BUS BAR ........................... 72
FIGURE 4.7 REDUCING LOOP INDUCTANCE IN POWER CIRCUITS ......................................... 74
FIGURE 4.9 SIC BJT AND JBS DIODE BASED THREE PHASE INVERTER DESIGN ................... 76
FIGURE 4.10 EXPERIMENTAL RESULT OF IBASE (PINK, 2A/DIV) VS. IBJT (GREEN, 10A/DIV) VS.
VCE (BLUE, 100V/DIV) ............................................................................................... 76
FIGURE 4.11 BUCK CIRCUIT SCHEMATIC ............................................................................ 78
FIGURE 4.12 BOOST CIRCUIT SCHEMATIC........................................................................... 78
FIGURE 4.13 CIRCUIT CONFIGURATION FOR DC BUS SHORT CIRCUIT INVESTIGATION ........ 79
FIGURE 4.14 EXPERIMENTAL
SWITCHING TRANSIENTS.
WAVEFORM OF CURRENT MEASURED AT
CH1: DC
BUS VOLTAGE
DC
BUS DURING
25V/DIV, CH2: IBASE_TOP 2A/DIV,
CH4: VRLIM1=5Ω 25V/DIV ............................................................................................ 80
FIGURE 4.15 SIMPLIFIED
CIRCUIT
SCHEMATIC
FOR
ABNORMAL
BUS
CURRENT
INVESTIGATION .......................................................................................................... 81
FIGURE 4.16 SIMULATION RESULT OF SWITCHING TRANSIENT AT (A) 50V DC BUS, (B) 300V
DC BUS ...................................................................................................................... 82
FIGURE 4.17 CIRCUIT SCHEMATIC OF
TOP SWITCH WITH CURRENT FLOW DIRECTION WHEN
BOTTOM SWITCH TURNS ON ........................................................................................ 83
FIGURE 4.18 BLOCK DIAGRAM OF THE ENHANCED GATE DRIVE BOARD ............................. 84
FIGURE 4.19 SIMULATION RESULT OF SWITCHING
TRANSIENT AT
300V DC
BUS WITH THE
PROPOSED GATE DRIVE ............................................................................................... 85
xiv
FIGURE 4.20 SWITCHING TRANSIENT OF THE TOP BJT GATE DRIVE. CH1: DC BUS VOLTAGE
100V/DIV, CH2: ILIM1 5A/DIV, CH3: VRLIM1=5Ω 25V/DIV, CH4: IBASE_TOP 2A/DIV ....... 86
FIGURE 4.21 EXPERIMENTAL
RESULT OF
VBE
AT
100V DC
BUS WHEN (A) BOTTOM
BJT
TURNS ON, (B) TOP BJT TURNS ON ............................................................................. 87
FIGURE 4.22 CIRCUIT SCHEMATIC OF SHORT CIRCUIT PROTECTION .................................... 87
FIGURE 4.23 EXPERIMENTAL RESULT OF DESATURATION PROTECTION CIRCUITRY. CH1: VBE
10V/DIV, CH2: VCE 5V/DIV, CH3: VDESAT 5V/DIV ..................................................... 89
FIGURE 4.24 LOGIC DIAGRAM OF HEX INVERTING SCHMITT TRIGGER ................................ 90
FIGURE 4.25 CHARACTERISTIC OF HYSTERESIS LOOP ......................................................... 91
FIGURE 4.26 HEX SCHMITT TRIGGER INPUT AND OUTPUT WAVEFORMS ............................. 91
FIGURE 4.27 A SIMPLE CIRCUIT TO MINIMIZE ..................................................................... 91
FIGURE 4.28 TRANSIENT CURRENTS OF DIGITAL IC ........................................................... 93
FIGURE 4.29 MEASURED IMPEDANCE FOR 2.2µF, 0.1µF, 10NF, AND 1NF ........................... 94
FIGURE 4.30 IMPEDANCE OF MULTIPLE CAPACITORS CONNECTED IN PARALLEL (A) 0.1µF //
0.1µF // 0.1µF, (B) 0.1µF // 10NF // 1NF, (C) 2.2µF // 2.2µF // 2.2µF, (D) 0.1µF // 10NF //
2.2µF ......................................................................................................................... 95
FIGURE 4.31 EQUIVALENT CIRCUIT OF (A) 0.1µF, 10NF, AND 1NF CONNECTED IN PARALLEL,
(B) RESONANT AT P4, (C) RESONANT AT P6 ................................................................ 96
FIGURE 4.32 AD
CONDITIONING CIRCUIT WITH
CM
AND
DM
NOISE CONSIDERATION AT
SIGNAL INPUT ............................................................................................................. 98
FIGURE 4.33 OUTPUT VOLTAGE SIMULATION RESULT OF (A) UNBALANCED, (B) BALANCED
INPUT IMPEDANCE. (C) FFT RESULT OF UNBALANCED INPUT IMPEDANCE ................ 100
FIGURE 4.34 ELECTROMAGNETIC EFFECTS OF SHIELDED CABLE ...................................... 102
FIGURE 4.35 EQUIVALENT CIRCUIT OF SHIELDED CONDUCTORS ...................................... 102
TABLE 4.1 EXTRACTED SELF AND MUTUAL INDUCTANCE OF TEST SETUP IN FIGURE 4.34 105
FIGURE 4.36 EQUIVALENT CIRCUIT OF THE SHIELDED CABLE ........................................... 105
FIGURE 4.37 SIMULATION
RESULT OF MAGNETIC COUPLING WITH SHIELD
(A)
UN-
GROUNDED, (B) SINGLE END GROUNDED, (C) BOTH END GROUNDED ........................ 106
xv
FIGURE 4.38 EXPERIMENTAL
RESULT OF MAGNETIC COUPLING WITH SHIELD
(A)
UN-
GROUNDED, (B) SINGLE END GROUNDED, (C) BOTH END GROUNDED ........................ 107
FIGURE A.1 1µF CERAMIC CAPACITOR USED FOR CIN, C1, AND C2.................................... 114
FIGURE A.2 IMPEDANCE OF A 2000UF ELECTROLYTIC CAPACITOR .................................. 114
FIGURE A.3 IMPEDANCE OF A 200UF FILM CAPACITOR .................................................... 115
FIGURE B.1 SCHEMATIC OF A VOLTAGE MEASUREMENT SETUP........................................ 116
FIGURE B.2 CHARACTERISTIC IMPEDANCE, Z0 OF THE 12 INCH RG-58 CABLE ................. 119
FIGURE B.3 TIME DELAY, TD OF THE 12 INCH RG-58 CABLE ........................................... 119
FIGURE C.1 (A) CAPACITIVE COUPLING CIRCUIT; (B) NOISE COUPLED ON CONDUCTOR 2. 120
FIGURE D.1 (A) INDUCTIVE COUPLING CIRCUIT; (B) NOISE COUPLED ON CONDUCTOR 2 .. 123
FIGURE E.1 LIFESPAN PREDICTION AT DIFFERENT OPERATING TEMPERATURE ................. 126
xvi
Chapter 1: Introduction
1.1
Introduction to EMC and EMI
Electronic equipment is said to have electromagnetic compatibility (EMC) if it
does not cause interference with other systems, interfere with its own processes, and is
not susceptible to noise generated from other systems. The electromagnetic environment
includes both conducted and radiated energy; therefore, EMC requires both emission and
susceptibility [1].
On the other hand, electromagnetic interference (EMI) stands for the level of
interference generated from electronic equipments. In power electronic applications, the
major EMI issues are coming from the high rated dv/dt and di/dt of the switching devices
such as IGBT, MOSFET. The dv/dt and di/dt are caused by the pulse-width modulation
technique which is often found in modern controls to meet the design requirements in
dynamic response, size, and weight. As a result, high slew rates of dv/dt and di/dt
containing noise in a wide frequency spectrum are generated.
The typical noise propagation path is illustrated in Figure 1.1. In general, the
major noise sources within electronics are generated from dv/dt and di/dt of the switching
devices. In lower voltage items, high speed digital circuits, such as DSP, communication
circuits, and various clock sources would also contribute substantial amounts of noise to
1
the power supply ground. The receptor is defined as the circuits that are susceptible to
the noise, which normally are the low voltage control circuits, such as pulse width
modulation (PWM) signals, digital signals from position sensors, and analog signals.
The coupling paths provide the channel to transmit noise from source to receptor.
Noise
sources
Coupling
paths
Receptor
Figure 1.1 Block diagram of noise propagation path
Methods of noise coupling can be categorized into two types: conductive and
radiative. Conductive noise coupling is defined as the noise that is transmitted through
wires from the noise source to another circuit. The typical bandwidth of conductive noise
falls below 30MHz. Noise above 30MHz contains both conductive and radioactive
noises. Radiatively coupled noise includes electric (capacitive) field coupling, magnetic
(inductive) field coupling, and a combination of both, known as electromagnetic field
coupling. When the receiver is close to the source (near field), the two types of coupling
are considered separately. When the receiver is far from the source (far field), the
radiation is considered to be a combination of electric and magnetic field [2].
The total emission for conductive noise is measured across AC or DC power
lines. The noise can be separated into two types: Differential Mode (DM) and Common
Mode (CM) noise. For a single phase AC and DC power supply, two identical Line
Impedance Stabilization Networks (LISN) were connected at the input sides to reduce the
DM and CM noise, as shown in Figure 1.2. LISN is used to ensure that the noise can be
measured consistently. The parameters in LISN can vary depending on the current
2
ratings. The LISN, shown in Figure 1.2, was employed to measure the conducted noise
in the present study. The 5µH inductor in the LISN was used to block noise generated
from the converter returning to the power supply. It also prevents external disturbances
from entering the converter. Two capacitors, 0.22µF and 4µF with a 5Ω current limiting
resistor were used to divert the external noise to a ground. The 0.1µF capacitor provided
a low impedance path to measure high frequency noise across the 1kΩ resistor. The 1kΩ
discharges 0.1µF capacitor when it is removed from a power line.
Spectrum
Analyzer
LISN1
0.22µF
AC
Attenuator
Power splitter
or combiner
5µH
4µF
0.1µF
5Ω
1kΩ
or DC
5Ω
1kΩ
4µF
0.1µF
DC or
AC bus
input
Electronic
equipment
0.22µF
5µH
LISN2
Figure 1.2 Test setup for conductive noise measurement
The outputs of two LISNs are usually connected through an attenuator before
being connecting to a Spectrum Analyzer (SA). Because the terminal impedance of the
spectrum analyzer (SA) is 50Ω, the input impedance is limited under test conditions
(EUT) to slightly less than 50Ω, as shown in Figure 1.3.
3
Figure 1.3 Impedance between EUT port and reference ground
The equivalent circuit for high frequency noise is illustrated in Figure 1.4 where
the impedance of LISN on the EUT side is modeled as a 50Ω resistor.
Converter
ZS
iCM
50Ω V1
iDM
50Ω V2
VS1
ZS
iCM
2iCM
ZC
Figure 1.4 Simplified high frequency model of conductive noise measurement
In Figure 1.4, the DM and CM noise currents are represented by the blue and red
lines, respectively. CM noise current is generated if there is an equivalent coupling
impedance, ZC, between the ground and the converter. The total noise level is measured
by connecting one of the LISNs to the SA while terminating the other with 50Ω
impedance. However, total noise can be separated into DM and CM noise based on the
4
voltage drop across the two LISN, V1 and V2 using the paths shown in Figures (1.1) and
(1.2).
(1.1)
(1.2)
In the experiment, V1 and V2 were connected through a power splitter or a
combiner to obtain a phase shift of 180°or 0°for DM and CM noise extraction. The time
domain noise was converted to frequency spectrum by using an SA. The final conducted
noise test setup is explained in Figure 1.5.
Bulk
capacitor
LISN
Power circuit, gate
drive, heatsink
Combiner
/ Splitter
DSP
controller
Ground plane
Wall
Computer
Spectrum
Analyzer
Resistive
load box
Power
supply
Figure 1.5 Complete conducted noise test setup
Conductive noise emission is defined as the level of total noise transmitted
through conductors back to the power sources. However, it does not explain how the
noise source is coupled into the system. Therefore, it is crucial to be able to identify the
5
hidden coupling paths in order to effectively reduce the conducted noise emission. Based
on this information, the optimal solution can be provided to effectively reduce the total
noise emission. Ultimately, the electronic equipment must be able to pass the EMC
regulations in order to be sold around the world.
1.2
Literature Review
The EMI problem was first identified in radio receivers as early as the 1900's;
however, at this time the problems were easily fixed by reassigning the transmitting
frequencies onto a less crowded spectrum or repositioning the cable further away from
the noise source. [1].
However, the invention of the Integrated Circuit (IC) and
semiconductor devices brought more severe interference which was widely spread over
the frequency spectrum.
Due to this phenomenon, the Federal Communications
Commission (FCC) in the United States published various EMC regulations to control the
levels of noise emissions for various applications. In addition to emission control, the
FCC also requires that the electronic equipment be able to resist a certain level of noise
generated from surrounding equipment or from electrical surges to ensure greater
reliability.
Ever since the introduction of the Bipolar Junction Transistor (BJT) in the 1950's
[3], power converters have become much more popular due to their high efficiency,
power density, and dynamic performance.
As the switching frequency and speed
increases, conducted noise begins to get louder due to the impulse current generated from
switching devices, such as rectifier and DC to AC inverters [4]-[7]. The distorted input
6
current waveform mainly contributes to DM noise, which would increase the chances of
power converter malfunction during high torque and speed operation if no proper steps
are taken to avoid this problem. In addition to the high levels of DM noise, other serious
problems, such as premature winding failures, shaft voltage, and bearing currents due to
dv/dt and parasitic impedance between EUT and the ground were also discovered [13][14]. Proper design and placement of the LC filters on the AC input or output or the
common reference plane or any combinations of the above for a three phase rectifier and
inverter were implemented to suppress total noise emission and improve system stability
[12]-[16]. However, not all the coupling paths and levels of the parasitic capacitance
have been identified.
In order to effectively bypass and suppress conductive noise emission, it is
necessary to identify the major parasitic coupling paths. One approach is to insert
switching transients into key spots and monitor the noise on various locations [17]. The
method does not require EUT to be functional or the system to be powered up; therefore,
this test can be conducted in the early stages of development. Another approach is to
identify the equivalent noise source and use the dominant distribution paths to estimate
the location of the conductive noise emission [18]. Although there are many other ways
to identify the coupling paths for various applications, most methods only focus on a
specific operation mode to predict total noise emission. The coupling mechanism due to
high frequency components, such as voltage and current oscillations across power
devices during normal operation, remains unclear. Another limiting factor for direct
noise measurement is the small amount of space between traces.
7
To further understand and be able to reproduce EMI issues, a high frequency
circuit model of EUT is necessary. We attempted to study the conducted EMI emission
on a three phase inverter [19]-[20]. The power devices were created using a physicsbased modeling technique. Only the major parasitic components of the device modules,
passive components, cables, leads, and interconnections were constructed using Time
Domain Reflectometry (TDR).
The high frequency circuit model with extracted
inductances and capacitances were simulated in the PSPICE program. It provided well
matched result from 10kHz to 30MHz. Furthermore, EMI emission was lower if zero
voltage soft (ZVS) switching was implemented compared to hard switching [19]. The
circuit model was very helpful for component layout optimization and noise estimation.
However, it was difficult to determine the coupling effects between traces within a
complex structure using the TDR method.
This could limit the effect of parasitic
components as well as the accuracy of noise prediction with increased frequency.
Upon completion of the PCB layout of the initial design, it will be possible to
extract parasitic components, including the stray inductance, parasitic capacitance, and
the mutual coupling effects between wires, using Finite Element Analysis (FEA) tools,
such as an Ansys Q3D extractor. Ideally, when all the boundary conditions, material
properties, and excitation sources have been identified, the electric and magnetic field
distribution within the boundaries can be determined. The accuracy of the simulation
was determined by the quality of mesh, which is a tradeoff between quality and
performance. Ref. [21]-[23] found that the conducted EMI simulation using the extracted
8
parameter from FEA was relatively accurate as long as the noise source and propagation
paths were properly modeled.
The EMI issues discussed above focus on Si based power electronic applications,
such as IGBT and MOSFET.
The noise problem became more severe when wide
bandgap devices (WBG), such as Gallium Nitride (GaN) and Silicon Carbide (SiC) began
to be widely used for power converters for greater efficiency [24]-[28]. One reason for
their popularity was their ability to switch at higher speeds (smaller dt) due to higher
saturation velocities [29].
Another reason was that WBG devices have lower on-
resistance (larger di) compared to Si devices with similar voltage ratings and higher
breakdown voltage (larger dv) with similar drift region spacing (gate-to-drain spacing)
due to higher critical electric fields [29]-[30]. The actual parameters are summarized in
Table 1.1. Another advantage of the WBD devices are the high bandgaps (Eg) which
allow the device to operate at higher temperatures compared to Si devices [30].
Si
GaN
SiC
Saturation velocity (cm/s)
Critical electric fields (MV/cm)
Bandgaps (eV)
Table 1.1 Properties of Si, GaN, and SiC device
In sum, WBG devices allow for designs with higher efficiency and power density.
Ref [31] and [32] demonstrate that a 760W boost converter and a 900W three phase
inverter has 99% efficiency. A 5kW SiC photovoltaic inverter with four times greater
power density than a Si inverter and peak efficiency of 99% is illustrated in reference
[33].
9
Another important aspect of EMC is the EMI filter which is used to effectively
reduce noise emission at the input and/or output of electrical equipment. With the trend
toward higher switching frequencies, it is essential that the EMI filter perform well at
high frequencies. EMI filters using scattering parameters (S-parameters) were proposed
to extract the parasitic components which affect performance at high frequencies [34].
The Equivalent Parallel Capacitance (EPC) has been shown to be one of the limiting
factors for excellent performance at high frequencies [35]. Based on the equivalent
circuit, two small capacitors were added at the end of each winding to cancel out the EPC
effect. Another solution is to insert and ground an embedded conductive layer into the
CM winding to establish a parasitic cancellation [36]-[37].
Many previous EMI studies have focused on simply reducing the total noise
emission. However, EMI not only transmits through conductors but also interferes with
nearby circuits.
1.3
Motivation of The Work
Because WBG semiconductor devices, such as GaN transistor and SiC MOSFET,
allow for much higher switching speeds (GaN dt<3ns at 480V, SiC dt<24ns at 800V) and
frequencies at the same voltage range as traditional IGBT or MOSFET, they will benefit
from smaller circuit footprints and higher efficiency. However, their more compact
design also means more vulnerable control signals due to stronger noise sources and
larger parasitic components. Since PWM is often applied to turn the switches on and off,
the induced dv/dt and di/dt act as excitation sources and provide high frequency voltage
10
and current oscillation across switching devices. This would further boost CM and DM
conducted noise emission levels, especially in high frequency ranges.
In order to fully utilize the superior switching capabilities of the GaN and SiC
power devices, identifying noise sources and their propagation paths is extremely
important. A PSPICE circuit modeling procedure for active devices was proposed and
demonstrated using a GaN based switched-capacitor circuit.
Conducted CM noise
generated by the circuit was analyzed, which verified the proposed improvement in both
computer simulation and experimental testing. An EMI filter is often added to the input
or output of power converters. We proposed a circuit model of CM choke to suppress
CM currents, which is applicable up to 100MHz. By combining both the active circuit
and the EMI filter circuit model, the total noise emission of the system can be predicted.
1.4
Chapter Preview
Chapter 2 presents a four step circuit modeling procedure for measuring CM
choke based on impedance measurements.
The PSPICE implementation method
simulation results correlate well with the low frequency test results up to 100MHz. We
were able to systematically evaluate grounding effectiveness by building an EMI filter
using the capacitor model.
Chapter 3 explains the circuit modeling procedures for GaN switched-capacitor
circuit in detail. Specifically, this chapter examines critical parameters such as the GaN
model, stray inductances of traces, mutual coupling inductances, and main bus capacitors.
The concept of circuit balance, based on the Wheatstone Bridge, is proposed to minimize
11
the conducted noise emission. Significant improvement is verified in both the computer
simulation and experimental testing.
Chapter 4 discusses the known and potential EMI issues within a SiC based three
phase inverter system. The noise source is generated from the power circuit and forced
into the low voltage circuits through parasitic capacitances and mutual coupling
inductances. Some layout improvements and circuit design considerations are proposed
to increase the noise immunity. The effectiveness of detail shielding is investigated in
this chapter as well.
Chapter 5 summarizes the research presented in this dissertation and suggests
topics for future research.
12
Chapter 2: Passive Device High Frequency Modeling
2.1
Introduction
The EMI filter has been widely used to suppress conducted EMI noise emission in
various electronic systems.
A typical one stage EMI filter includes inductors and
capacitors to filter DM and CM noise, as shown in Figure 2.1 [42]. The DM (CX1, CX2)
and CM capacitors (CY1, CY2) provide a low impedance path to bypass the noise currents.
Both CX1 and CX2 are only effective against DM noise, while CY1 and CY2 reduce the DM
noise by half. On the other hand, DM (LDM) and CM inductors (LCM) create a high
impedance path to block EMI noise currents. The total effective DM inductor includes
the leakage inductance of CM choke and 2X LDM. To control CM noise, the effective
inductance should include LCM and half of LDM. Depending on the size requirements,
more stages can be added by connecting multiple one stage filters in series. For a typical
two stage EMI filter, one stage would normally focus on filtering low frequency noise,
while the other would filter the high frequency noise. Due to the trend of increasing
switching speeds and frequencies, the effectiveness of an EMI filter at high frequencies
has become even more crucial. Therefore, modeling the components of an EMI filter is
critical to understanding how the parasitic components affect it. The derived model can
also be implemented in computer simulations to evaluate the filter performance and
13
predict noise distribution of a system by including the power converter or the noise
sources.
CM choke
1
3
LDM
CY2
CY1
CX1
CX2
CY1
CY2
2
4
LDM
Figure 2.1 One stage EMI filter
This chapter will first present the proposed modeling procedure for CM choke
based on the impedance. Then, the steps to construct the CM choke SPICE model using
the extracted parameters will be presented. Based on the model, the key parameter
affecting the performance of CM choke will be identified. In order to maximize the EMI
filter performance, a systematic analysis approach on the various grounding
configurations was studied. The grounding analysis was verified in both the computer
simulation and via experimental testing.
2.2
Methods of Impedance Measurement and Limitations
An impedance analyzer, Agilent 42941A and a test fixture, 16047E were used to
obtain the impedance of the CM choke and capacitors. Since the frequency range of
interest was from 10kHz to 100MHz, open and short calibrations were needed to
compensate for the transmission characteristics due to stray inductance and parasitic
capacitance of the test fixture leads. The induced errors were dependent upon test
14
frequencies, test fixtures, test leads, devices under test (DUT) connection configurations,
and surrounding conditions [38].
Hence, the key to obtaining accurate impedance
measurement is to compensate for the actual measurement setup.
If an impedance analyzer is not applicable, a function generator (10kHz to
100MHz) and oscilloscope for current measurement can be used to obtain impedance
versus frequency curve.
A BNC cable with 50Ω characteristic impedance is
recommended for measurement of the current because the transmission line effect can
only be removed by matching the impedance between the cable and the oscilloscope
terminal impedance (generally 50Ω).
A more detailed explanation of impedance
matching is provided in Appendix B.
One limitation of using this method is the
possibility of a distorted current waveform near resonance frequencies which could
degrade the accuracy of the measurements. When an impedance analyzer is used, the
data is averaged over a large number of sampling points to improve measurement
precision and consistency [38]. In addition to being highly accurate, both methods
provide intuitive understanding of the impedance curve at various frequencies.
2.3
CM Choke Modeling
CM choke is extensively used to suppress CM noise current, which is generated
by power circuits that are coupled to the ground. Figure 2.2 (a) shows the typical
structure of a CM choke in which the flux linkage, λCM (solid line) is doubled for CM
noise currents, and λDM (dashed line) is cancelled out for DM noise currents. Figure 2.2
(b) shows the proposed high frequency CM choke circuit model.
15
EPR
Winding 1
EPC
λCM
1
2
λDM
IDM
ICM
3
ICM
4
1
Lline
RDC
L1
Z1/2
IDM
2
Lline
RDC
RDC
Lline
3
Z1/2
L2
RDC
Lline
4
EPC
EPR
(a)
Winding 2
(b)
Figure 2.2 (a) Structure of CM choke, (b) high frequency circuit model of CM choke
where L1 and L2 are the self inductance of windings 1 and 2. EPC represents the
equivalent parallel capacitance of one set of windings. Since the wires are wound across
the magnetic core and stacked on top of each other, it makes sense that the winding
capacitance would dominate the impedance at high frequencies. Therefore, EPC is
connected across L1 and L2. EPR is the equivalent parallel resistance to identify core
loss. Lline represents stray inductance due to wire connections, which is generally very
small. RDC is the DC resistance of the winding, which is in the milliohm range for power
line filters. Z1 represents the coupling impedance between two sets of windings, which is
dominated by the capacitance.
The impedance is divided in half and connected
diagonally across pins 1 and 4 and pins 2 and 3 so the impedance from pins 1and 2 is the
same as from pins 3 and 4. Z1 is essential because it will interact with leakage inductance
and change impedance behavior at high frequencies.
16
2.3.1
CM Inductance LCM Extraction
The induced voltage in windings 1 and 2 due to CM noise current is given in Eqs.
(2.1) and (2.2).
Since the flux linkage is enhanced in this configuration, the CM
impedance, LCM is equal to the combination of self and mutual inductance. Because the
CM choke is generally symmetrical, windings 1 and 2 can be assumed to have identical
LCM for both windings, found in Eq. (2.3).
(2.1)
(2.2)
(2.3)
LCM was extracted by measuring the impedance between the shorted pins 1 and 2
and pins 3 and 4. The effects of the winding impedance Z1 was not taken in this case. As
a result, the equivalent circuit would be equal to two sets of parallel windings, as shown
in Figure 2.3. The measured (solid blue line) and estimated (red dashed line) impedance
are depicted in Figure 2.4.
17
EPR/2
2EPC
Impedance
Analyzer
1,2
Lline/2
LCM/2
RDC/2
3,4
VS1
Figure 2.3 Equivalent circuit of ZCM measurement
ZCM
5
10
ZCM measured
ZCM estimated
Impedance (ohm)
4
10
3
10
2
10
4
10
5
10
6
10
Frequency (Hz)
7
8
10
10
Figure 2.4 Impedance for LCM, EPC, and EPR extraction
A seen in Figure 2.4, the inductance is expected to dominate at low frequencies;
therefore, LCM can be calculated based on Eq. (2.4).
(2.4)
18
where ZCM is the CM impedance at low frequency fCM. For the choke under test, the
measured ZCM at 80.5kHz was equal to 2036Ω and the calculated LCM was approximately
8mH.
Other parameters, such as stray inductance of wires, Lline were estimated
proportionate to the length of wire, which was less than 10nH. This set RDC at less than
168mΩ. Both results would not affect the accuracy of the model because they are only
effective at extremely high or low frequencies. EPC was calculated at the resonance
point, according to Eq. (2.5).
(2.5)
where ZCM_OSC is the impedance at the resonance frequency fCM_OSC. Based on the
measured ZCM_OSC, which was equal to 15.8kΩ at the resonance frequency of 1.127MHz,
an EPC was calculated as 2.5pF. The round shape at the resonance point suggested that
the core had a high loss. EPR was used to represent the core loss, while this parameter
was obtained by trial-and-error to match the peak magnitude at the resonance point.
Since the permeability of magnetic material is highly nonlinear at high frequencies, the
estimated EPR was adjusted slightly in order to obtain more accurate results. The final
extracted circuit parameters will be presented in Section 2.4.
2.3.2
Leakage Inductance Lleakage Extraction
CM choke, explained in Figure 2.2 (a), is like a transformer if pins 2 and 4 are
considered the primary windings and pins 1 and 3 are the secondary windings or vise
versa. If pins 3 and 4 are connected, as shown in Figure 2.5 (a), then the terminal
19
voltages across pins 2 and 4 (winding 2) and pin 1 and 3 (winding 1) would satisfy Eqs.
(2.6) and (2.7). And the leakage inductance, Lleakage would be equal to the difference of
self and mutual inductance, as given in Eq. (2.8). The equivalent circuit of a transformer
is depicted in Figure 2.5 (b).
(2.6)
(2.7)
(2.8)
CM choke
L1
1
2
1
Lleakage = L2 - M
3
Lleakage= L1 - M
M
M
2
4
4
3
L2
(a)
(b)
Figure 2.5 (a) CM choke circuit schematic and (b) equivalent circuit for Lleakage extraction
where M is the mutual inductance. To obtain the leakage inductance, Lleakage for windings
1 and 2, pins 1, 3 and 4 were shorted. Because Lleakage is much less than M, the
impedance measured between pin 2 and pins 1,3 and 4 was dominated by the 2X leakage
inductances. With the assumption that the value of Lleakage for windings 1 and 2 are the
same, the final equivalent circuit for Lleakage extraction is revealed in Figure 2.6. The
measured (blue solid line) and estimated (red dashed line) impedance are given in Figure
2.7.
20
EPR
EPC
Impedance
Analyzer
2
Lline
2Lleakage
RDC
1,3,4
VS1
Figure 2.6 Equivalent circuit for Lleakage extraction
Zleakage
5
10
Zleak measured
4
Zleak estimated (no winding parasitics)
Impedance (ohm)
10
3
10
2
10
1
10
0
10
4
10
5
10
6
10
Frequency (Hz)
7
8
10
10
Figure 2.7 Impedance for Lleakage extraction
At low frequencies, the impedance is dominated by the 2Lleakage; therefore Lleakage
is calculated according to Eq. (2.9).
(3.9)
21
where Zleakage is the impedance at low frequencies (fleakage ). At 10kHz, the Zleakage is equal
to 2.836Ω and the calculated Lleakage is equal to 22.57µH. With the EPC and EPR,
obtained from Section 2.3.1, the estimated Lleakage (red dashed curve) shows a good
correlation with the measured impedance in Figure 2.7. The two extra resonance points
between 50 and 70MHz were due to winding parasitic effects, which will be discussed in
Section 2.3.3.
2.3.3
Impedance Z1 Determination
Z1 can be determined based on the measured impedance across pins 1and 2 when
pins 3 and 4 are open. Since the applied current was DM, only the leakage inductance
was involved. The equivalent circuit for Z1 extraction is given in Figure 2.8 and the
measured impedance (solid blue line) is shown in Figure 2.9.
EPR
EPC
Impedance
Analyzer
1
Lline
VS1
RDC
Z1/2
2
Lline
RDC
Lleakage
Lleakage
Z1/2
EPC
EPR
Figure 2.8 Equivalent circuit for Z1 measurement
22
Z1
7
10
Z1 measured
Z1 estimated (C1 only)
6
Impedance (ohm)
10
5
10
4
10
3
10
2
10
4
10
5
10
6
10
Frequency (Hz)
7
8
10
10
Figure 2.9 Impedance for Z1 extraction
We expected Z1 to be dominated by a capacitive load due to the physical layout of
the windings. This suggests that the value of the capacitor, C1 could be obtained in the
low frequency range, according to Eq. (2.10).
(2.10)
At very low frequencies, such as 10kHz, the measured impedance was 6.52MΩ,
which was too large to measure accurately. As a result, the equipment measurement
range was taken into account to approximate an accurate reading. At 40.85kHz, ZC1 was
equal to165.8kΩ, and the calculated C1 was 1.175pF.
Using the same parameters
discussed in previous sections, the estimated Z1 curve (red dashed line), where C1 was the
only parameter used to plot Figure 2.9. In the figure, the two resonance points at 16.69
23
and 20.83MHz correlate very well, but the equivalent circuit failed to show resonance at
51.45 and 55.4MHz.
To calculate these resonance points, the effects of CM choke were minimized by
shorting the first and second windings. A simplified version of the equivalent circuit is
shown in Figure 2.10 where Lline1 and Lline2 represent the stray inductances of wire
connections for the short circuits and CM choke windings impedance measurement.
Impedance
Analyzer
VS1
Lline1
1
Lline2≈0
Z1/2
Lline1
3
Z1/2
2
Lline2≈0
4
Figure 2.10 Equivalent circuit for Z1 extraction with shorted CM choke
The measured impedance (solid green line), represented in Figure 2.11, showed
that there was no resonance at 16.69 and 20.83MHz.
This is because Lleakage was
minimized by Lline2. In the figure, the impedance at low frequency remains dominated by
C1 .
Since the stray inductance of Lline1 and Lline2 were only several nano henries,
resonance with C1 would not occur below 100MHz. Therefore, the resonance is likely
caused when C1 interacts with the distributed parasitic inductance and capacitance. The
lumped circuit model in Figure 2.12 was applied to describe the resonance points at 51.45
(fR1) and 55.4MHz (fR2).
24
Z1 windings shorted
7
10
Z1s measured
Z1s estimated
6
Impedance (ohm)
10
5
10
4
10
3
10
2
10
4
10
5
6
10
7
10
Frequency (Hz)
8
10
10
Figure 2.11 Impedance of Z1 with shorted CM choke
C1
L2
C2
R2
Figure 2.12 Lumped circuit model for Z1/2
According to the lumped circuit model, fR1 and fR2 will satisfy Eq. (2.11) and
(2.12). The final fitted curve result is represented as the black dotted line in Figure 2.11.
(2.11)
(2.12)
25
Insertion of the derived Z1 into the equivalent CM choke model in Figure 2.2 (b)
caused “glitches” to occur between 50 and 70MHz, as illustrated in Figure 2.7 and Figure
2.9, which can be accurately reproduced. The final CM choke model is shown in the next
section.
2.4
CM Choke PSPICE Implementation and Verification
One simple way to model CM choke in PSPICE is to use two mutually coupled
inductors. Each inductor represents the self-inductance, L1 or L2 of the winding, which
can be derived based on Eqs. (2.3) and (2.8). The mutual inductance between two
windings, M, can also be obtained by utilizing these two equations. The coefficient of
coupling, k, will represent the mutual coupling effects. Eq. (2.13), (2.14), and (2.15) are
the derived equations used to determine L1, M, and k.
(2.13)
(2.14)
(2.15)
Since LCM and Lleakage were equal to 7.7mH and 22.57µH, the corresponding L1
and M were calculated to be 3.861mH and 3.839mH. Based on L1 and M, the k of this
choke was equal to 0.9943. In some cases, Lleakage is purposely designed to be larger
(with a lower k value) in order to provide sufficient filtering against DM noises without
additional DM inductors.
26
The circuit parameters and schematic are given in Figure 2.13. By connecting the
choke to the four configurations, as discussed in previous sections, the impedances for
ZCM, ZDM, Z1, and Z1 with shorted windings are shown in Figure 2.14.
Figure 2.13 CM choke SPICE implementation
27
Impedance (Ω)
(c)
Impedance (Ω)
(d)
(a)
(b)
Frequency (Hz)
Figure 2.14 CM choke simulation result in SPICE (a) ZCM, (b) ZDM, (c) Z1, (d) Z1 with
windings shorted
Compared to the measured impedances in Figure 2.4, Figure 2.7, Figure 2.9,
andFigure 2.11, the proposed circuit model with calculated parameters was able to
accurately reproduce the characteristics of CM choke from 10kHz to 100MHz. Since the
magnetic core model was linear in this simulation, the mismatch of resonance could be
slightly higher than the measurement. Despite this limitation, the proposed parameter
extraction method and PSPICE implementation are useful when evaluating CM choke
performance via a computer simulation.
28
Insertion loss (IL) is one way to measure the performance of CM choke [1]. It is
defined as the ratio of CM current without the choke compared to the CM noise current
with the choke, as shown in Eq. (2.16). Based on this definition, larger IL is desirable in
a wide frequency range.
(2.16)
Figure 2.15 (a) and (b) depict the insertion loss of the CM choke in two scenarios:
1) fixed CM inductance with various shunt capacitances, 2) fixed shunt capacitance with
various CM inductances. It is clear from the figure that filter performance at high
frequencies (1 to 100MHz) is not benefited by increased inductances; instead it is
reduced considerably as a function of EPC. Therefore, the most important parameter that
determines the high frequency performance of CM choke is the parasitic capacitance,
EPC.
29
Insertion loss
(dB)
EPC x1
EPC x5
EPC x10
EPC x20
(a)
Insertion loss
(dB)
L1 x20
L1 x1
L1 x5
L1 x10
(b)
Frequency (Hz)
Figure 2.15 Insertion loss of CM choke with (a) fixed 3.9mH CM choke and various
shunt capacitances, (b) fixed shunt capacitance and various inductances
2.5
Capacitor and DM Inductor Modeling
In addition to CM choke, the EMI filter also includes X and Y-capacitors and a
DM inductor [1], [2], [42]. The modeling procedures for capacitors 56nF, 100nF and
10µF of the one stage EMI filter in Figure 2.1 are explained in Section 3.2.2. The two
additional 47µH DM inductors, LDM, were modeled following similar procedures for
LCM, discussed in Section 2.3.1. Since two of the LDM were not mutually coupled, the
effectiveness of CM inductance from the two DM inductors was reduced to 1/2LDM;
30
however, the effectiveness of DM inductance was actually doubled. Circuit parameters
for the capacitors and DM inductors are given in Figure 2.16.
2.5pF
48.7µF
(a)
38kΩ
13.6nF
13.4nF
28.3nF
42mΩ
65mΩ
60mΩ
100.5n
55.7n
(b)
9.95µF
(c)
(d)
Figure 2.16 Circuit models for (a) LDM=47µH, (b) CY2=100nF, (c) CY1=56nF, (d)
CX1=10µF
2.6
Study of the EMI Filter Grounding Effectiveness for CM Noise
The one stage EMI filter, shown in Figure 2.1, with focus on major parasitic
components as shown in Figure 2.17. Based on the Thevenin theorem, the equivalent
CM noise source and coupling impedance of the reference plane are represented by VCM
and ZCM. Since the positive and negative DC bus were connected for more efficient CM
noise analysis, the circuit can be further simplified, as shown in Figure 2.18, by
combining the two sets of windings. The total CM noise current measured on LISN was
equal to Eq. (2.17). This study was conducted based on reference [43] where the author
investigated the EMI filter’s performance in a motor drive system.
31
EPR1
EPC1
Lline
CLISN
50Ω
ESL1
CY1
50Ω
CLISN
CY1
ESL1
L1
LDM ESL2
CY2
C
L1
LDM
EPC1
EPR1
Lline
ICM3
EPR2
EPC2
CY2
ESL2
VCM
ZCM
EPC2
EPR2
ICM1
ICM2 ICM
Figure 2.17 Circuit configuration for CM noise grounding analysis
LISN
Lline/2
EPR1/2
EPR2/2
2EPC1
2EPC2
LCM/2
LDM/2
M1
2CLISN
ESL1/2
25Ω
ESR1/2
ESR2/2
2CY1
ICM1
2CY2
ICM2
ICM3
ESL2/2
C
M2
VCM
ZCM
ICM
Figure 2.18 Equivalent circuit of one stage EMI filter for CM noise analysis
(2.17)
In Figure 2.18, the voltage drop across LISN is approximately equal to VCM1 if the
stray inductance of the line is very small or negligible within the range of the frequency
of interest. As a result, to minimize noise detected by LISN, VCM1 must be kept small.
Based on the definition of VCM1, given in Eq. (2.18), ESL1 would dominate at high
frequencies since the CY1 will be close to zero. Therefore, ESL1 would become the key
32
factor for maintaining a low voltage drop across VCM1 in order to reduce noise detected
by LISN.
(2.18)
2.6.1
Effects of a Common Grounding Path
In many power electronic circuit designs, there is usually a large piece of copper
which is grounded underneath the EMI filter to provide a low impedance return path.
The mid-point of the Y-capacitors, CY1 and CY2, shown in Figure 2.17, was connected to
this grounding plane to bypass the CM noise current. A short wire was used to connect
the grounded board to a common reference frame, such as the metal case of electronic
equipment. The equivalent circuit of this configuration is illustrated in Figure 2.19 where
C and B represent the ground layer and common reference plane, respectively. The
additional wire connecting C and B is represented by a stray inductance, Lwire.
33
LISN
Lline/2
EPR1/2
EPR2/2
2EPC1
2EPC2
LCM/2
LDM/2
M1
2CLISN
ESL1/2
25Ω
ESR1/2
ESR2/2
2CY1
ICM1
2CY2
ICM2
ICM3
ESL2/2
C
M2
VCM
ZCM
ICM
Lwire
B
Figure 2.19 Equivalent circuit with a wire connecting to a reference frame
Since the added wire carried both ICM1 and ICM2, there was an additional voltage
drop on Lwire . The total voltage between point B and M1 is given in Eq. (2.19).
(2.19)
At low frequencies, ICM1 and ICM2 are lessened due to the large impedance of CY1
and CY2. The total CM noise current was determined by inductance of the CM choke and
DM inductor. As frequency increases, ICM2 would increase and would be expected to be
much higher than ICM1 because ICM1 is limited by the CM inductance on the return path.
CM noise measured on LISN would be much higher since VBM1 would be added across
VLISN. The number of noise increases can be calculated by placing Eq. (2.19) over Eq.
(2.18).
If ICM2 = n1∙ICM1, Lwire = n2∙ESL1, and CY1 would be negligible at high
frequencies, then the ratio of noise increment, m1 could be found by using Eq. (2.20).
34
(2.20)
If n1 = 10 and n2 = 2, then the CM noise would increase by 44X or be degraded by
33dB compared to the scenario without additional wire connections.
One way to
minimize the noise increment is by using a shorter wire or copper strips to reduce the
stray inductance of Lwire. Another way is to reduce the variance in current between ICM1
and ICM2 by adding more Y-capacitors across CY1. Unless n2 is equal to zero, there will
always be degradation in this configuration. Therefore, the most effective way to reduce
CM noise in a one stage EMI filter is to ground CY1 and CY2 separately. If this is not
possible, then CY1 should be removed in order to maintain the high output impedance for
CM noise at high frequencies.
2.6.2
Effects of Mutual Coupling Between Two Grounding Paths
With separate grounding, the additional voltage drop on a single wire due to the
large difference in current between ICM1 and ICM2 was removed. However, at high
frequencies filter performance could still be limited by the mutual coupling effect
between the two wires.
The equivalent circuit of separate grounding with mutual
coupling effect is given in Figure 2.20. Since the two wires, Lwire1 and Lwire2 were
connected to the same reference plane, T-equivalent circuit could be used for circuit
analysis.
35
LISN
Lline/2
EPR1/2
EPR2/2
EPR1/2
EPR2/2
2EPC1
2EPC2
2EPC1
2EPC2
LCM/2
LDM/2
LCM/2
LDM/2
M1
2CLISN
ESL1/2
25Ω
ESR1/2
ESR2/2
2CY1
ICM1
2CY2
ICM2
ICM3
Lwire1
ESL2/2
M
C
LISN
M2
Lline/2
M1
M2
VCM
2CLISN
ESL1/2
ESL2/2
ZCM
25Ω
ESR1/2
ESR2/2
2CY1
ICM1
2CY2
ICM2
ICM3
ZCM
Lwire2-M
Lwire1-M
Lwire2
VCM
M
C
Figure 2.20 Equivalent circuit of mutual coupling effect between two separate grounding
The new voltage drop between C and M1 is equal to Eq. (2.21). Although the
effective inductance in the CY1 branch was reduced, additional voltage drop due to
ICM2∙M was added.
(2.21)
The ratio of increased noise can be analyzed by following a similar analysis
procedure, given in section 2.5.1. If ICM2 = n1∙ICM1, Lwire1 = n2∙ESL1, and M = k∙Lwire1 =
n2k∙ESL1, then the noise ratio, m2 can be determined from Eq. (2.22).
(2.22)
Eq. (2.22) is quite similar to m1 with the difference of k multiplied by n1. Since k
is the coefficient of coupling, its value varies from 0 to 1. If n1 = 10, n2 = 2, and k = 0.1
(M is 10% of Lwire1), then there would be an 18dB noise degradation. Compared to m1,
m2 is likely to be lower since the coupling coefficient between the two wires is normally
less than 1. As the frequency increases, the differences between ICM1 and ICM2 or n1
36
should increase and become the major limiting factor to the filter’s high frequency
performance. If the length of the wire is fixed, according to Eq. (2.22), k must be
reduced in order to minimize m2. One simple way to reduce k is by further separating the
two grounding paths. Another way is to place the two wires perpendicularly in order to
reduce the magnetic flux coupling effect.
This section provides a systematic approach for analyzing the grounding in a one
stage EMI filter. Based on the analysis, the grounding of the Y-capacitor for each stage
should be separated and kept far away from the other. The wires connecting to the
reference plane and ESL of the Y-capacitors need to be small in order to maximize the
effectiveness of the filter. The contact resistance between wire and reference plane must
be minimized as well to reduce the voltage drop.
The grounding analysis is also
applicable to EMI filter with multiple stages.
2.7
Computer Simulation and Experimental Testing
2.7.1
Simulation Result
The purpose of the computer simulation was to verify the one stage EMI filter
performance based on different grounding configurations, as discussed in Section 2.6.
The simulation is setup according to Figure 2.17. CM noise was generated via a square
wave which mimics the VDS waveform across switching devices.
The switching
frequency was 500kHz with raising and falling speed of 10ns. Since the CM noise
current was formed mainly through capacitive coupling between power device and the
37
reference plane, 300pF capacitor and a small equivalent series resistor of 10mΩ was used
to represent the CM coupling impedance, ZCM. The models for CM choke and capacitors,
CX1, CY1, and CY2 in the EMI filter were built based on the actual components derived in
Sections 2.4 and 2.5. Two LISNs were connected at the positive and negative rail for
CM noise extraction. The stray inductance of the wire was Lwire = 30nH.
We created five scenarios, listed in Table 2, that were based on the grounding
analysis. The simulation results, including the five scenarios and original noise emission
levels, are given in Figure 2.21.
(1)
CY1 and CY2 are connected to a common ground and a single wire is used to
connect to the reference plane
(2)
Only CY2 are connected to reference plane
(3)
Separate grounding with k = 0.1 (simulate two wires close to each other)
(4)
Separate grounding with k = 0.01 (simulate two wires far from each other)
(5)
Ideal grounding
Table 2.1 Five cases for EMI filter grounding analysis
38
(a)
(b)
(c)
(d)
(e)
(f)
Frequency (Hz)
Figure 2.21 Simulation result of grounding for (a) original emission, (b) case 1, (c) case
3, (d) case 2, (e) case 4, and (f) case 5
The frequency spectrum of the original noise emission is shown in Figure 2.21
(a). Compared to Scenario 1, which is given in Figure 2.21 (b), CM noise had only
5dBµV or approximately 5% improvement from 1 to 10MHz. The filter became more
effective as frequency increased from 10 to 100MHz due to the Y-capacitors. If CY1 and
CY2 were connected to a reference plane separately with two twisted wires (coupled,
k=0.1), as shown in Figure 2.21 (c), CM noise would be reduced by another 10 to
39
20dBµV compared to Scenario 1. If the two wires were significantly separated (k =
0.01), as shown in Figure 2.21 (e), then another 20 to 40dBµV improvement would be
observed compared to Scenario 3. If separate grounding is not possible, then only a CY2
would be used. The simulation result for this scenario is given in Figure 2.21 (d) in
which the noise level was 10dBµV lower compared to Scenario 3. The performance of
the ideal filter with zero stray inductance is depicted in Figure 2.21 (e). CM noise can be
further reduced by an additional 10 to 20dBµV from Scenario 4 if the stray inductance of
the wire could be reduced. This simulation verified the grounding analysis in Section
2.6. Furthermore, it showed that the performance of the EMI filter can be greatly
affected by different grounding configurations.
2.7.2
Experimental Results
This experiment was performed to verify that different configurations of
grounding have a real impact on filter effectiveness. The test setup is given in Figure
2.22 in which the voltage source was generated from the voltage doubler circuit
switching at 304kHz. The EMI filter was connected in series to the DC bus, while the Ycapacitors were connected to a common reference plane. Two LISNs and a combiner
were used to reduce the conductive CM noise.
40
LISN1
0.22µF
5µH
4µF
0.1µF
5Ω
1kΩ
CM choke
1
CX1
3
CY1
1kΩ
4µF
0.1µF
DC+
CY2
Source
5Ω
LDM
Voltage
doubler
circuit
CY2
CY1
0.22µF
2
4
5µH
LDM
DCZCM
LISN2
Reference plane
Figure 2.22 Diagram of the test setup for CM noise grounding investigation
The original conductive CM noise emission, ranged from 100kHz to 50MHz,
without EMI filter is shown in Figure 2.23 (a). The measured high emission was due to
the high switching speed and frequencies of the six GaN devices in the voltage doubler.
The peaks of 30 and 45MHz were caused by the voltage ringing across VDS during turnoff transients.
Therefore, an EMI filter was applied to reduce conductive noise
emissions. Figure 2.23 (b) shows the experimental result when two Y-capacitors were
first connected to a common ground on PCB and to a reference plane with a single wire.
This resulted in most of the CM noise being reduced from 90 to 80dBµV or lower. By
separately grounding to the reference plane with twisted wires, the test results, illustrated
in Figure 2.23 (c), show that the improvement compared to Figure 2.23 (b) was less than
5dBµV. In the scenario with only a CY2 attached, shown in Figure 2.23 (d), the noise at
1, 10, 30 and 45MHz was still higher than 60dBµV, which was better than separate
grounding paths using a high coupling coefficient. However, if the two grounding paths
were placed far away from each other, even with a 2X wire length, the noise would be
reduced by 12 to 25%, as shown in Figure 2.23 (e). Another 8 to 12% improvement in
41
the high frequency range was achieved by reducing the length of the wire, as illustrated in
Figure 2.23 (f).
(a)
(b)
(c)
(d)
(e)
(f)
80dBµV
60dBµV
80dBµV
60dBµV
80dBµV
60dBµV
Figure 2.23 Conductive CM noise emission (a) without EMI filter, (b) common ground
with a single wire connection to reference plane, (c) separate grounding paths with
twisted wires, (d) only CY2 is applied in the filter, (e) separate grounding with long wires,
(f) separate grounding with short wire
42
2.8
Summary
We studied the parasitic effects of the key components, CM choke, DM inductor,
and capacitors on a one stage passive EMI filter. Open and short compensation was
performed in order to remove the parasitic effects due to the leads in the test fixture. If
an impedance analyzer is not applicable, an oscilloscope and function generator may be
used to obtain the impedance measurement. However, the typical impedance of the cable
must correlate well with the terminal impedance in the scope in order to prevent the
transmission line effect at high frequencies. We proposed procedures for measuring the
impedance and calculating the parameters for CM choke. The corresponding PSPICE
model was built based on the proposed circuit model. The simulation results of CM
choke had good agreement with measurements from 10kHz to 100MHz. The winding
capacitance was identified as the major limit to high frequency filtering performance.
Other components including the DM inductor and capacitors were also extracted for EMI
filter grounding analysis. The analysis showed that CM noise performance of EMI filter
can be greatly affected due to improper grounding configurations. Due to the large
current difference between the two Y-capacitors at high frequencies, the Y-capacitor near
LISN should be grounded separately in order to reduce the additional voltage drop caused
by the other Y-capacitor. Even with separate grounding, mutual coupling still occurs
between the two wires which must be minimized by keeping both wires far away from
each other. To further improve the high frequency performance, the length of the wire
should be kept as short as possible. Both computer simulation and experimental testing
have confirmed the results of the grounding analysis.
43
Chapter 3: Active Device High Frequency Circuit Modeling
3.1
Introduction
Converters based on switched-capacitor circuits utilizing WBG devices, such as
GaN, benefit from the high switching speed (<10ns) and operating temperature
capabilities. However, the sharp rising and falling edge of the drain-to-source voltage
acts as an excitation source to the parasitic inductance and capacitance, which results in
EMI and over voltage due to voltage oscillation. Because of the parasitic capacitance
between GaN and the heatsink, hidden paths are formed for dv/dt to flow into the ground
and generate CM noise. This kind of parasitic capacitance is normally inherit in the
circuit structure and is difficult to minimize.
To fully utilize the high switching speed of the GaN transistors in the switchedcapacitor circuit based converter, characterizing EMI, especially the CM noise, becomes
critical. We built a PSPICE circuit model focusing on the major parasitic components to
try to eliminate CM noise.
Parameter extractions for the critical components were
implemented using Q3D FEA and an impedance analyzer. We were able to verify the
accuracy of the circuit model through experimental testing.
Based on the balance concept theory, this paper also proposes the third way to
reduce the CM noise emission. One common way to reduce the noise emission is to
44
suppress and/or bypass CM noise by using a CM choke and Y-capacitors. Another way
is to increase dt by reducing the switching speed, changing the control strategy or altering
the circuit structure at the expense of higher switching rates and system complexity.
Improvement and minimization of CM noise by the proposed way is presented. As a
counter example, a case which could lead to higher CM noise based on this analysis is
also discussed. All cases were verified by both computer simulation and experimental
testing.
3.2
CM Noise Circuit Modeling of Voltage Doubler Converter
3.2.1
Operating Principle
Figure 3.1 shows the switch capacitor circuit we studied for CM noise
investigation. The circuit has two modes of operation, as shown in Figure 3.2. During
the first mode, Figure 3.2 (a), C2 was connected in series with CIN through S6 to form the
output voltage. At the same time, C1 was being recharged by the DC bus CIN through S1
and S2. In the second mode, in Figure 3.2 (b), the output voltage was established by
connecting C1 and CIN through S3 while C2 was being recharged through S4 and S5. At
this time all the switches were operating at 50% duty cycle. The total output voltage of
the circuit was doubled without the use of any magnetic components. In this paper, this
switched-capacitor circuit will henceforth be referred to as the voltage doubler converter.
In Figure 3.1, each GaN device, S1, S2, S3, S4, S5 and S6 was attached to a heatsink
with a thin layer of insulation material in between. If the heatsink was connected to
45
ground, this creates parasitic capacitances. The proposed high frequency voltage doubler
circuit model including the major parasitic capacitance and stray inductance is shown in
Figure 3.3.
L11
S1
S4
ZLISN
S3
C1
ZLISN
S6
CIN
C2 RL
L22 S5
S2
Figure 3.1 Dc-dc voltage doubler circuit
L1
S1
S4
IR
+
C1
-
IC1
S2
+
IC1 CIN
IR
DC
S6
DC
+
C1
-
+
C2
-
IC2
CIN
S3
IR
RL
IC2
+
C2
-
S5
L2
IR
(a)
RL
IR
(b)
Figure 3.2 The equivalent circuit (a) when C1 is charging (b) C2 is charging
Cb
Ca
L13
L15
ESR1
Cc
Cd
L11
S1
ESRIN
Cg
Cf
Ce
L21
L23
S4
L25
ESR2
ESLIN
ESL1
ESL2
S3
S6
L16
C1
L14
Cn
S2
Cm
CIN
L12
L26
L22
Ck
Cl
S5
Cj
C2
L24
Ci
Ch
Figure 3.3 The equivalent circuit with the stray inductances
46
3.2.2
High Frequency CM Noise Circuit Modeling
To study and predict the high frequency CM noise caused in the voltage doubler
converter, a CM noise equivalent circuit model was derived to investigate and reproduce
the switching characteristic of the circuit. The components modeled included the EPC1010 GaN device, the passive components, such as capacitor, stray inductance of the
PCB traces, LISN, the cables for power supply, the resistive loads, and the LISN
connections.
The PSPICE model for EPC-1010 was obtained from the device supplier, EPC.
The model is a hybrid of physics-based and phenomenological functions to create a
compact PSPICE model with acceptable simulation and convergence characteristics. The
accuracy of the model has been extensively studied in the literature [24].
The model of the 1µF ceramic capacitor used in CIN, C1 and C2 is relatively
simple but proved to be essential to our study. Both the impedance of the capacitor and
stray inductance of the PCB traces affected the resonance frequency and switching
behavior. The capacitor impedance was measured with Agilent 42941A from 10kHz to
30MHz. Low frequency range capacitance was obtained by using Eq. (3.1) in the low
frequencies.
The Equivalent Series Inductance (ESL) was then calculated at the
resonance point via Eq. (3.2). The Equivalent Series Resistor (ESR) was obtained by
trial-and-error to match the magnitude of the resonance point. The model of the 1µF
capacitor is shown in Figure 3.4. Other capacitors, including the electrolytic and film
47
capacitor used to stabilize and filter at the DC bus side, were measured and curve fitted in
the similar way. The measured and curve fitted results are given in Appendix A.
(3.1)
(3.2)
C=1µF ESL=4nH ESR=7mΩ
Figure 3.4 Model of the ceramic capacitor for CIN, C1, and C2
The stray inductances, shown in Figure 3.3, are the other critical components
which were extracted from the field analysis results using a Maxwell Q3D Extractor.
Figure 3.5 shows the Printed Circuit Board (PCB) of the voltage doubler converter
imported to the Q3D for parameter extraction. Stray inductance L11 was found to be
equal to the sum of inductance in traces 1, 2 and the externally added 67mm wire in
between traces 1 and 2. Stray inductance L12, L13 and L14 were equal to the inductance in
traces 3, 4, and 5. Since the circuit was symmetrical at the DC bus, inductance for traces
6, 7, 8, 9, and 10 were equal to traces 1, 2, 3, 4, and 5. In Q3D, the source and sink nodes
for each conductor were defined according to the actual current flow, given in Figure 3.2.
The current path for each of the two charging loops, IC1 and IC2 is highlighted by black
and green dotted lines in Figure 3.5.
48
2
IC2
1
9
3
10
4
C1
5
IC1
CIN
6
8
C2
7
Figure 3.5 Copper traces of the voltage doubler converter
Table 3.1 contains the simulation results for each trace. The highlighted values in
Table 3.1 are the self-inductance, and the other values represent the mutual inductance.
The final values for L11, L12, L13, and L14 were obtained by adding each column, as
shown in Table 3.2. For L11, an additional 43nH was added to compensate for the extra
wire inserted in between traces 1 and 2.
units: nH
Trace 1&2 Trace 3 Trace 4
1.2
-0.3
Trace 1&2 15.5
1.2
8.8
-1.1
Trace 3
-0.3
-1.1
20.7
Trace 4
-0.3
-1.9
1.7
Trace 5
Table 3.1 Q3D simulation of each trace
Trace 5
-0.3
-1.9
1.7
6.1
units: nH
L11
L12
L13
L14
Inductance 59.1
5.7
7.0
21.1
Table 3.2 Stray inductance in the voltage doubler circuit
49
3.2.3
Circuit Model Verification
To validate the CM noise circuit model, the simulation results of the circuit model
was compared with the experiment, as shown in Figure 3.6 (a) and (b). The simulation
results correlated very well with those from the experiment, including details such as the
small dip of the output voltage during dead time. The initial current dip and high
frequency oscillation components or a charging current IC1 were also accurately
reproduced in the circuit model simulation. The oscillation patterns of the simulated VDS
waveforms S1 and S3 were also very close to those in the experiment. The turn-on and off time from 10% to 90% or approximately 10ns which was also verified by the
experiment. The slight VDS1 decrease and VDS3 increase, observed during experimental
testing, were also replicated in the simulation.
Since only the major parasitic
capacitances were considered in the simulation, the mismatches were expected to
increase at higher frequencies.
50
VOUT
25V/div
VDS_S1
VDS_S3
2A/div
TIME
1µs/div
ID_S1
(a)
VOUT
TIME
400ns/div
20V/div
VDS_S3
10V/div
VDS_S1
10V/div
ID_S1
2A/div
(b)
Figure 3.6 GaN soft-switching voltage and current waveforms from (a) simulation and
(b) experiment
51
3.3
Common Mode Noise Analysis
3.3.1
Equivalent Circuits
According to the substitution theorem, the switching waveform of a branch can be
replaced by a voltage source with the same pattern and the circuit operation will remain
the same. So, the voltage waveforms across S1, S2, S3, S4, S5, S6, C1, C2, and CIN were
replaced with the voltage sources V1, V2, V3, V4, V5, V6, V7, V8 and V9. Superposition
was applied to decouple the noise propagation path of each source. The circuit model
used for noise analysis is shown in Figure 3.7. Since the circuit was symmetrical in terms
of the DC bus, the analysis of V1, V2, V3, and V7 would also be valid for V5, V4, V6, and
V8.
Cb
Ca
L13
L15
V7
L14
Cn
Cd
Cc
50Ω L25
V3
V2
Cm
L21
V4
L23
V6
V9
L16
V8
50Ω
L12
Cl
Cg
Cf
Ce
L11
V1
L22
Ck
V5
Cj
L26
L24
Ci
Ch
Figure 3.7 Noise model of the voltage doubler
To analyze V1, all other voltage sources can be shorted, and the equivalent circuit
obtained is shown in Figure 3.8. Since Cd and Ck were connected in parallel with LISN,
these parasitic capacitances helped to bypass some of the CM noise. Similarly, the
equivalent circuits for noise V2, V3, V7, and V9 are also found in Figure 3.9 - 3.12. The
52
total CM noise measured on LISN was equal to the sum of all the CM currents generated
by each source.
O
L12
L13
L16
Z
Cm Cl
Ca
½ ZLISN
Ck
V1
L15
L14
Cn
ICM1
L11
X
Y
Cb
GND
Cc
Cd
Figure 3.8 Equivalent circuit of noise V1
O
L11
ICM2
L12
½ ZLISN
L13
L15
Ck
Cd
V2
L16
X
Cl
Cb Cc
L14
Y
Cn
Cm
Ca
Figure 3.9 Equivalent circuit of noise V2
ICM3
L11
L13
Cn Ca
L12
L15
V3
½ ZLISN
L16
Cb Cc
L14
Cl Cm
Figure 3.10 Equivalent circuit of noise V3
53
Ck
Cd
L11
L15
L12
L16
ICM7
½ ZLISN
Ck
L13
Cb
Cc
Cd
L14
V7
Ca
Cn
Cl Cm
Figure 3.11 Equivalent circuit of noise V7
L13
L23
L24
L11
L25
L21
L15
L16
L26
L22
V9
ZLISN
L14
L12
ZLISN
Cg Cf Ce Ca Cb Cc Cd
Ck
Cl Cm Cn Ci Cj Ch
ICM9
Figure 3.12 Equivalent circuit of noise V9
3.3.2
The Concept of Circuit Balance
The equivalent circuits derived above, except for the noise generated by V 2, have
a Wheatstone Bridge type of structure, as shown in Figure 3.13. The relationship among
voltage measurements on LISN, VO and noise source VS can be calculated via Eq. (3.3).
Ideally, the noise can be eliminated if Eq. (3.4) is satisfied.
impedance relationship of a balanced circuit.
54
Eq. (3.5) shows the
VO
Z1
Z2
ZLISN
VS
V1
V2
Z3
Z4
Figure 3.13 Wheatstone bridge circuit
(3.3)
(3.4)
(3.5)
In Figure 3.8, the equivalent circuit due to V1 is balanced if Eq. (3.6) is satisfied.
(3.6)
where, ZXO and ZYO represent the total impedance between X, O and Y, O. ZXGND and
ZYGND are the impedance between X, GND and Y, GND. Since the physical trace length
between S1 and S3 was short, L15 and L16 were negligible compared to the other stray
inductance. L13 was connected in parallel with L14 and the equivalent inductance was
approximately 5nH. Because Ca and Cn were in the pico farad range, these capacitances
dominated the impedance between Z and GND. The final impedance of ZXO, ZYO,
ZYGND, and ZXGND are given in Eqs. (3.7) - (3.10).
(3.7)
(3.8)
55
(3.9)
(3.10)
As seen in Table 3.2, L11 was approximately 10 times larger than L12. Since Cc,
Cb, Cl, Cm, Ca, and Cn are approximately the same, adding the additional capacitor, CX1 at
ZXGND was necessary to achieve a balanced condition. After simplification, equivalent
circuit V1 was balanced when Eq. (3.11) was satisfied.
(3.11)
Similar assumptions to L13, L14, L15, and L16 were applied to noise V3. CM noise
generated by V3 was minimized by adding CX3 to the denominator in Eq. (3.12).
(3.12)
The balanced condition for V7 in Figure 3.11 was calculated using Eq. (3.13).
Since L14 was approximately 3 times larger than L13, CX7 was added to the denominator
to minimize noise emission.
(3.13)
For noise V2 in Figure 3.9, the impedance between Y and GND was infinity. As
the result, the noise could not be completely removed by using the balance circuit
structure.
Instead, V2 was minimized by adding CX2 at one of the locations in the
denominator in Eq. (3.14).
56
(3.14)
Based on Eqs. (3.11), (3.12), and (3.14), adding a capacitor to Cl would have
improved the noise due to V1, V2, and V3. Although CX7 would help to reduce CM noise
due to V7, it would have been worse for V2 and V3. Similarly, adding a capacitor at Ce
would have decreased the CM noise generated by V4, V5, and V6. Even though we were
unable to compensate for the unbalanced condition of V2, the overall CM noise emission
could have still been improved with the additional capacitors at Cl and Ce.
The CM noise generated by V9 in Figure 3.12 already had a balanced structure
because L11 and L12 are equal to L22 and L21. All the parasitic capacitances could have
been assumed to have been the same because there is an equal distance between the board
and reference plane. The circuit remained balance with an additional capacitor at Cl and
Ce. Moreover, CM noise could be further improved by adding a capacitor at Cd and Ck.
3.4
Computer Simulation and Experimental Testing
3.4.1
Simulation Results
Computer simulation on the proposed circuit model was setup to study CM noise
propagation and validate the proposed improvements. A scenario of improper capacitor
placement which could lead to higher CM noise emissions was also demonstrated in the
simulation.
57
The switching frequency of the circuit was set to 304kHz in order to achieve the
zero current switching for S1 and S5. The DC bus voltage and peak charge current were
25V and 3.2A, respectively. The parasitic capacitances were difficult to directly measure;
therefore, the values were obtained by trial-and-error to correlate with the experimental
results. Because the capacitances are not equally distributed in reality, only a small
portion of the noise magnitude and high frequency oscillation occurrence will be
inconsistent with the experimental results. However, this will not affect the major CM
noise distribution. The final parasitic capacitances were set to 20pF in the simulation.
Two LISNs were connected to the positive and negative DC bus inputs to measure
CM and DM noise. The total CM and DM noise collected by the LISNs were obtained
according to Eqs. (3.15) and (3.16).
(3.15)
(3.16)
The CM noise emission of the circuit is given in Figure 3.14 (a), which shows that
the noise had a peak value of ±3.1V during the switching transients.
If the parasitic capacitance at Ca and Cn were increased by 200pF, the CM noise
measured on LISN would also increase due to the unbalanced condition of V2, V3, and
V7. According to Eq. (3.14), the noise generated by V2 would be 1.7 times higher than in
the original scenario. Similarly, Eq. (3.17) was used to calculate the noise generated by
V3 which would be 1.4 times higher than the original emission. For V7, Eq. (3.18)
suggests that the noise collected by LISN would remain the same as in the original
58
scenario. Simulation results in Figure 3.14 (b) confirmed that the peaks of the noise
increased to ±10V, which was roughly three times higher than the original emission in
Figure 3.14 (a).
(3.17)
(3.18)
Since the switching speed and stray inductance of the board were fixed, CM noise
improvement was realized by reducing the magnitude of the transient spikes. Based on
the analysis in Section 3.3.2, two 10nF capacitors were added at Cl and Ce to test the
effectiveness of CM noise reduction. Figure 3.14 (c) confirms that the peaks of CM
noise were reduced from ±3.1V to ±1.2V.
The frequency spectrum of the CM noise is shown in Figure 3.15. Curve (a) in
Figure 3.15 represents the CM noise distribution of the original circuit. Compared to
curve (b) which corresponds to the scenario in which 200pF was added at Ca and Cn, the
noise underwent a 10dB or 10% increase across 100k - 10MHz. Curve (c) represents the
scenario in which 10nF was added at Cl and Ce. Compared to curve (a), there was a 10dB
to 25dB or 11% to 24% improvement from 1 - 30MHz. However, improvement in the
low frequency range was limited.
59
VDS_S3
(x15V)
VCM
(x1V)
1V/div
VDS_S1
(x15V)
(a)
VCM
(b)
VCM
(c)
Figure 3.14 Total CM noise in time domain for (a) original circuitry, (b) 200pF added at
Ca and Cn, (c) 10nF added at Cl and Ce
60
dBµV
(a)
80dBµV
dBµV
(b)
80dBµV
(c)
Figure 3.15 Total CM noise in frequency domain for (a) original circuitry, (b) 200pF
added at Ca and Cn, (c) 10nF added at Cl and Ce
3.4.2
Experimental Results
The voltage doubler converter was setup in the lab to verify the proposed circuit
model and CM noise analysis. The combiner and splitter were used to extract the CM
and DM noise measured by the two LISNs. Figure 3.16 (a), (b), and (c) show the
experimental results of CM noise corresponding to the three scenarios in Figure 3.14 (a),
(b), and (c). The measured negative and positive peaks of the original CM noise in
Figure 3.16 (a) were -3.8V and 4.5V, respectively. Compared to Figure 3.14 (a), the
peaks obtained in the experiment were approximately 1.0V higher. The magnitude
disparity was expected because not all the parasitic capacitances in the circuit and
measurement loop were considered. The peaks that occurred during switching transients
were also expected, as shown in Figure 3.14 (a).
61
Figure 3.16 (b) shows that CM noise increased when 200pF was added at Ca and
Cn. The measured negative and positive peaks of the CM noise are -10V and 15V
respectively, approximately 3.3 times higher than the original scenario in Figure 3.16 (a).
The test results correlated well with Figure 3.14 (b), which also estimated a 3X increase
in the peak noise.
Figure 3.16 (c) illustrates that total CM noise emission decreased when 10nF was
added at Cl and Ce. The CM noise peaks were reduced from -3.8V to -2V and 4.5V to
2.5V. The noise improvement matches Figure 3.14 (c). Figure 3.16 (c) also suggests that
the parasitic capacitance was not evenly distributed because the high frequency
oscillation components reacted differently depending on whether S1 was turned on or
off.
62
TIME
400ns/div
VDS_S3
10V/div
VCM
1V/div
VDS_S1
10V/div
(a)
VCM
5V/div
(b)
VCM
1V/div
(c)
Figure 3.16 Experimental result of CM noise for (a) original circuitry, (b) 200pF added at
Ca and Cn, (c) 10nF added at Cl and Ce
The frequency spectrum of CM noises in Figure 3.16 (a), (b), and (c) are given in
Figure 3.17 - 3.19. Compared to the original CM noise emission in Figure 3.17, Figure
3.18 shows that the CM noise increased by 5-25% across the range of 100k-30MHz when
200pF was added at Ca and Cn. Figure 3.19 shows that the CM noise was reduced by 524% across 1.5 - 15MHz when 10nF were inserted at Cl and Ce.
63
The experimental results verified that the proposed circuit model was able to
accurately predict the trend of CM noise. Figure 3.16 (c) and Figure 3.19 confirm that
the total CM noise was substantially reduced when 10nF were added at Cl and Ce.
80dBµV
Figure 3.17 Original CM noise from 100kHz to 30MHz
80dBµV
Figure 3.18 CM noise when 200pF is added to Ca and Cn
64
80dBµV
Figure 3.19 CM noise when 10nF is added to Cl and Ce
3.5
Summary
A detailed CM noise circuit model of the voltage doubler converter is developed.
The hidden CM noise coupling paths propagating CM noise originating from different
noise sources were identified. The key components such as the stray inductances and
capacitors that affect the switching behavior were obtained through a Q3D extractor and
impedance analyzer. The accuracy of the circuit model was verified through comparing
the output voltage, VDS waveforms, and charging the current in the computer simulation
with those from the experimental testing.
We utilized the circuit balance concept based on the Wheatstone Bridge structure
to reduce the overall CM noise. According to the CM noise equivalent circuit analysis,
total CM noise was reduced by adding capacitors at Cl and Ce. As an example, another
scenario which could lead to higher CM noise was also studied to validate the CM noise
65
equivalent circuit and the method of analysis. Experimental results confirmed that the
noise sources and CM noise propagation paths were properly modeled.
66
Chapter 4: Electromagnetic Interference in Power Electronics
4.1
Introduction
EMI issues in power electronic applications are generated due to the high dv/dt
and di/dt from switching devices. The problem is expected to become more severe with
the introduction of WBG devices since dt would become much smaller while maintaining
the same dv and di. The square wave PWM would provide an excitation source for trace
stray inductances to interact with the output capacitances of power devices and would
result in high frequency oscillation during switching transient. In addition to higher
conductive emissions, as discussed in previous chapters, the dv/dt and di/dt would also
interfere with nearby circuits inside the converter or inverter through electromagnetic
coupling. This chapter will focus on the EMI issues within a three phase inverter
designed for traction motor drive application. The inverter was constructed using a SiC
based BJT and junction barrier Schottky (JBS) diode. For this type of application, the
inverter normally consists of four parts: the power circuit, the gate drive circuit, the
control circuit and the on-board power supply, as shown in Figure 4.1.
67
Three phase inverter
Source
Power circuit
Contactor
Electric
Machine
Soft startup
resistor
Battery
DC Bus
VCE
PWMs
Bus voltage
Gate drive circuit
15V
Onboard
power
supply
Power supply
Gate drive circuit
Protection circuit
3V, 5V, 15V
PWMs
Faults
Control circuit
Analog-to-digital
conditioning circuit
Currents
Voltages
External
inputs
Thermistors
Rotor position
DSP
controller
Position sensor circuit
External peripherals
Communication circuit
Digital I/Os
Analog inputs
RS-232
CAN
Figure 4.1 Block diagram of a typical three phase inverter in motor drive application
The DC source of the inverter can come from the battery or AC inputs through a
rectifier or converter. Normally, a soft startup circuit is used to pre-charge the DC
capacitor when the system is powered up for the first time. The load on the inverter is
not limited to a single electric machine but can also be connected to a power grid. In a
motor drive application, it would have external inputs, including the rotor position
feedback, positive temperature coefficient (PTC) thermistor, digital and analog
inputs/outputs, RS-232 as well as CAN for communication. The DSP on the control
68
board would collect all the gathered information and execute corresponding commands,
such as motor field orientation control (FOC), acceleration, deceleration, shunt down, etc.
The gate drive circuit would amplify the PWMs received from the control circuit and
generate the proper voltage and current level to drive the power devices. Since the midpoint of each phase leg is floating, the gate drives’ input and output for both upper and
lower switches would need to be isolated using an isolation power supply or non-isolated
bootstrap topology. For greater safety, desaturation of the short circuit protection would
be implemented to quickly shut down the PWMs when a fault condition is detected. A
flyback converter is often used as the on-board power supply due to its ability to generate
multiple isolated output voltages. The input of the flyback converter can be obtained
from the DC bus or an external power supply, which would also introduce the conductive
noise generated by other power circuits.
This chapter will discuss the EMI issues identified in previous sections through
computer simulation and experimental testing.
Theoretical analysis and practical
solutions will be provided to mitigate the EMI issues.
4.2
Power Circuits
4.2.1
Power Device Test Setup
The SiC BJT and JBS diodes to be tested are discrete components, as shown in
Figure 4.2. We chose Thermal Clad Insulated Metal Substrate solution (T-Clad IMS) to
maintain good thermal dissipation during the three phase operation.
69
(a)
(b)
Figure 4.2 SiC (a) BJT and (b) JBS diode under test
The structure of a single layer IMS board was separated into three layers: circuit
layer, dielectric and base layer, as given in Figure 4.3. The top circuit layer contained
copper foil with a thickness of 4oz. The thickness of the dielectric layer was only 3mils,
which provided the required electrical isolation and thermal conductivity. The base layer,
made of aluminum or copper, was used to mount the IMS board onto a heatsink for heat
dissipation. The SiC BJTs and diodes were soldered onto the top layer, while the IMS
board was mounted to a fan forced cooling heatsink. See Appendix E for more detailed
information on the selected dielectric material.
Figure 4.3 T-Clad circuit board
The inherited parasitic capacitance was expected to be large due to the short gap
between the power device and the heatsink. If this was the case, then the level of CM
noise current could be high, as seen in Eq. (4.1).
70
(4.1)
Since the circuit topology and parasitic capacitance were fixed, the method to
minimize conductive noise was limited to reducing dv or increasing dt.
Normally,
reducing dv would not be possible due to the fixed DC bus voltage. Increasing dt would
result in additional undesired switching losses.
Despite the limited solution, one
important aspect of reducing the coupling effect would be to minimize the magnitude of
voltage overshoot and oscillation during turn-on and -off transients. In addition to the
benefits of higher reliability and power loss reduction,, removing oscillation components
would also result in lower noise magnitude at high frequencies, which would reduce the
conductive noise emission and near field coupling effects.
4.2.2
PCB Layout Considerations
Voltage oscillation occurs when an excitation source is connected to the stray
inductance and output capacitance, CCE of the device. If stray inductance is high, then
the initial peak turn-off voltage would also be large, as seen in Eq. (4.2).
(4.2)
One solution for reducing the stray inductance between the DC bus capacitor and
the power device is to implement the laminated DC bus bar structure, as the shown in
Figure 4.4.
71
Figure 4.4 An example of laminated DC bus bar
The two bus bars were connected to the positive and negative terminal of the
capacitor, and the currents through the two bus bars were equal but in the opposite
direction. The generated magnetic flux would cancel out if the two copper plates were
placed on top of each other, as shown in Figure 4.5. Only the leakage flux, stray
inductance of the screw and the un-laminated portion would contribute to the total stray
inductance.
Φ1
I1
I2
Φ2
Figure 4.5 Relationship of magnetic flux in laminated bus bar
Since the bus bar was connected to the capacitor, a copper jumper was used to
represent the capacitor’s ideal internal impedance.
Aluminum screws were used to
connect the jumper and bus bar. The experimental results of the laminated and non72
laminated bus bar are given in Figure 4.6 (a) and (b). The results show that the total stray
inductance was reduced from 31nH to 20nH when the laminated structure was utilized.
1.00E+02
Lest_laminated = 20.36nH
Impedance (Ω)
1.00E+01
1.00E+00
1.00E-01
ZL meas.
1.00E-02
ZL est.
1.00E-03
1.00E-04
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
Frequency (Hz)
(a)
Lest_separate = 31.07nH
Impedance (Ω)
1.00E+02
1.00E+01
1.00E+00
ZL meas.
1.00E-01
ZL est.
1.00E-02
1.00E-03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
Frequency (Hz)
(b)
Figure 4.6 Experimental result and the estimated stray inductance of (a) laminated, (b)
non-laminated DC bus bar
Normally, the DC bus capacitor would be constructed using an electrolytic
capacitor with a large capacitance but poor high frequency performance due to the large
ESL. A film capacitor with low ESL was added near each phase leg to provide a low
impedance path during switching, which reduced the peak voltage overshoot. In Figure
4.7, the total stray inductance in the film capacitor loop (red) is much smaller (ESL2 +
73
Lstray2 + Lstray3 + Lstray4) than the electrolytic capacitor loop (blue) (ESL1 + Lstray1 + Lstray2 +
Lstray3 + Lstray4).
Lstray1
ESR1
ESR2
ESL1
ESL2
DC
Bus
Film
Cap.
Lstray2
S1 D1
Lstray3
S2 D2
Lstray4
Figure 4.7 Reducing loop inductance in power circuits
Stray inductance Lstray3 can also be minimized by placing the upper and lower
switch close to each other. This is because when S1 turns off, the current through S1 will
flow freely through D2. During this transition, Lstray3 must be minimized in order to
reduce unwanted voltage, current overshoot and oscillation effects.
Since the design requirement included device evaluation, a shunt resistor with
very low inductance was used to measure the pulsating current through SiC BJT and a
diode, as illustrated in Figure 4.8 (a). For voltage measurement, a probe adaptor with a
short ground loop was used to minimize loop inductance and improve the high frequency
measurement, as shown in Figure 4.8 (b).
74
(a)
(b)
Figure 4.8 SDN series shunt resistor from T&M Research Product, (b) Probe adaptor,
Tek 013-0291-01 for high voltage probe P5120
The final three phase inverter design is shown in Figure 4.9. A laminated DC bus
bar was used to minimize Lstray1 in Figure 4.7. The snubber capacitors were placed very
close to the collector on the top SiC BJT and the emitter on the bottom SiC BJT to
achieve the smallest Lstray2 and Lstray4. Since both BJTs were placed very close to each
other, Lstray3 was also minimized. Figure 4.10 is an experimental result showing a 50V
overshoot when SiC BJT was turned off at 14.5A.
75
Laminated
DC bus bar
VCE
measurement
Snubber
capacitors
Lstray4
G
BJT
bot
C
E
Lstray3
Lstray2
E
BJT
top
Current
source gate
drive
G
C
Shunt resistor
A
B
C
AC output
terminals
Figure 4.9 SiC BJT and JBS diode based three phase inverter design
Figure 4.10 Experimental result of Ibase (pink, 2A/Div) vs. IBJT (green, 10A/Div) vs. VCE
(blue, 100V/Div)
76
4.3
Gate Drive Circuits
A gate drive is normally placed very close to power devices in order to minimize
the loop inductance between its output and the gate-source terminal. As a result, both
input and output of the gate drive would be susceptible to noise during switching
transients. If the parasitic capacitances, CBE, CBC, and CCE of power devices are large,
then the chance of gate mis-triggering during fast switching transients would increase,
especially when driving WBG devices. The noise generated by dv/dt and di/dt is coupled
to the gate drive input signal radiatively. If the magnitude of the induced noise is higher
than the input threshold, then gate mis-triggering could also occur. This section will
analyze the EMI issues observed as a result of gate drive and provide mitigation
techniques.
SiC BJT is a current driven device; therefore, the gate drive must provide the
required base current, Ibase in order to maintain low on-voltage during high current
operation. For this particular SiC BJT, the required Ibase to drive 100A was 4A. IXYS
RF MOSFET driver, DEIC421 was selected to obtain a 4A continuous output current.
Since the typical operating voltage for DEIC421 is 15V, we chose a 3Ω gate resistor. We
applied additional capacitors across the gate resistor to increase the switching speed of
the device.
Since the SiC BJTs and diodes were not commercial grade, they needed to be
tested individually with the corresponding gate drive by configuring the three phase
inverter into buck and boost, as shown in Figure 4.11 and Figure 4.12. In buck mode, the
top BJT and bottom diode were tested. While in boost mode, the top diode and bottom
77
BJT were evaluated. Once the quality of each device was verified, the inverter was ready
for three phase operation.
Top
BJT
Shunt
Resistor
Top
Diode
Shunt
Resistor
DC bus
Bottom
BJT
Bottom
Diode
Shunt
Resistor
Shunt
Resistor
Figure 4.11 Buck circuit schematic
Top
BJT
Top
Diode
Shunt
Resistor
Shunt
Resistor
DC bus
Bottom
BJT
Bottom
Diode
Shunt
Resistor
Shunt
Resistor
Figure 4.12 Boost circuit schematic
As the three phase output current and DC bus voltage increased, we observed a
DC bus short circuit. An experiment setup, shown in Figure 4.13, under current limiting
protection was carried out to reproduce and investigate the failure. Both switches were
operating in complementary mode with a 4µs deadtime at the 50V DC bus.
78
Rlim1
Top
BJT
Top
Diode
Shunt
Resistor
Bottom
BJT
Bottom
Diode
Shunt
Resistor
Figure 4.13 Circuit configuration for DC bus short circuit Investigation
Despite the fact that no load was added at the phase output, a 6.75A current spike
across Rlim1 (5Ω, green) was observed and measured during switching transients, as
shown in Figure 4.14. The blue line in the figure is the top BJT base current. At point a,
the top BJT was turning off and the bottom BJT was turning on after 4µs at point b. The
current spike at the DC bus was observed during a transient caused by another switch
turning on.
79
a
b
Figure 4.14 Experimental waveform of current measured at DC bus during switching
transients. Ch1: DC bus voltage 25V/Div, Ch2: Ibase_top 2A/Div, Ch4: VRlim1=5Ω 25V/Div
A simplified circuit model, given in Figure 4.15, was setup in PSIM to bolster the
analysis. The model only considered the static parasitic capacitances across BJT, gate
resistors and capacitors in the gate drive circuit and trace stray inductance in the test
setup. The provided capacitances of BJT, CBC, CCE, and CBE were 1.86nF, 1.75nF, and
1.0nF, respectively. Since the given bias voltage across VBE was approximately 5V, the
gate resistor was set to 5Ω to match the 2A base current in the experiment. An ideal
20nF capacitor was added across the gate resistor to increase the switching speed. The
PWM was switching at 10kHz with a 4µs deadtime, which was similar to the
experimental setup. The current limiting resistor at the DC bus was reduced to 1Ω in
order to enhance the effect of the current spike and also provide a dampening effect to the
circuit simulation. In the actual experiment, this resistor represented the trace resistance
which was very close to zero.
80
Figure 4.15 Simplified circuit schematic for abnormal bus current investigation
The simulation result at the 50V DC bus is given in Figure 4.16 (a) where Ibase_top
and Ibase_bot represented the gate drive current for the top and bottom switch, Ig_top was the
current flowing into the base terminal of the top switch, and Ilim1 was the current through
the limiting resistor. A peak current of 12A was observed at Ilim1 when one of the
switches was turned on, shown in Figure 4.16. If the DC bus voltage were increased to
300V, Ilim1 peak would increase to 35A, as shown in Figure 4.16 (b). Compared to Figure
4.16 (a), the Ig_top peak was also higher when it was turned off. Since BJT is a current
driven device, the additional base current would result in the device remaining partially
turned-on even in the off state, which would result in higher Ilim1. If Rlim1 were reduced
to zero, Ilim1 would be very large.
81
I9
I9
15
Ilim1
10
Ilim1
40
5A/Div
20A/Div
20
5
0
0
-5
I4
I4
3
3
Ig_top
Ig_top
2
2
1A/Div
1A/Div
1
1
0
0
I2
I7
I2
6
I7
6
Ibase_bot
4
Ibase_bot
4
2A/Div
2
2A/Div
2
0
0
Ibase_top
-2
(a)
-4
0.00036
0.00038
Time (s)
Ibase_top
-2
(b)
-4
0.0004
0.00026
0.00028
Time (s)
0.0003
Figure 4.16 Simulation result of switching transient at (a) 50V DC bus, (b) 300V DC bus
When the bottom switch was turned on, voltage across the Cbc and Cce of the top
switch increased and therefore induced Ibc and Ice, as shown in Figure 4.17. If the top
gate drive does not provide enough sinking capability, then the additional current would
flow into the base terminal, which would cause the device to be turned on. Therefore,
Ilim1 would be higher due to extra current in Ic.
82
Ilim1
Ibc
Cbc
Ic
Ice
Cce
Cbe
Ig_top
Ibe
Ibase_top
Figure 4.17 Circuit schematic of top switch with current flow direction when bottom
switch turns on
One method to prevent this from happening was to apply negative bias voltage
during the off state to increase the safety margin. This would provide a low impedance
path between the base and emitter and eliminate Ig_top.
The block diagram of the
proposed new gate drive board is shown in Figure 4.18 where -10V were applied. A
push-pull current boost circuitry was built to generate the required 4A base current.
Short circuit protection was implemented to shut down PWM during fault situations and
prevent further damage to the device.
83
Source
Short circuit protection
1. Vce monitoring
+15 V
Integrated Gate Drive
Chip
Out
( TD350 )
D44H
-10 V
Fiber Optic
1. PWM inputs
2. Fault outputs
Current boost
circuitry
Figure 4.18 Block diagram of the enhanced gate drive board
The simulation result of the proposed gate drive under the 300V DC bus voltage
is given in Figure 4.19. The Ig_top current spike was removed when another switch was
turned on. The value of Ilim1 did not increase compared to the scenario presented in
Figure 4.16, which implies no additional Ic was generated.
84
I19
10
Ilim1
5A/Div
5
0
I14
3
Ig_top
1A/Div
2
1
0
I4
I10
Ibase_bot
4
2
0
Ibase_top
-2
2A/Div
-4
-6
0.00036
0.00038
Time (s)
0.0004
Figure 4.19 Simulation result of switching transient at 300V DC bus with the proposed
gate drive
The experimental results, shown in Figure 4.20, indicate that the current sink
capability increased and the peak current measured at the DC bus was reduced to 5.7A at
a 100V DC bus. The value was even smaller compared to the scenario in Figure 4.14,
which was conducted at the 50V DC bus.
85
Figure 4.20 Switching transient of the top BJT gate drive. Ch1: DC bus voltage
100V/Div, Ch2: Ilim1 5A/Div, Ch3: VRlim1=5Ω 25V/Div, Ch4: Ibase_top 2A/Div
Since the extra current flowing into base terminal is difficult to measure directly,
another way to check for gate mis-triggering is by measuring VBE. For the SiC BJT, the
typical turn on DC bias for VBE was between 4.5V to 5V. Therefore, if VBE were kept
below 4.5V during the off state, then the device would remain off. Figure 4.21 shows
that the new gate drive was able to keep VBE below 0V when another BJT was turned on.
86
0V
Vbe_top
0V
Vbe_bot
VRlim=5Ω
Ishunt
(a)
(b)
Figure 4.21 Experimental result of Vbe at 100V DC bus when (a) bottom BJT turns on,
(b) top BJT turns on
Short circuit protection was implemented by detecting VCE when the switch was
turned on. The simplified circuit schematic of desaturation of short circuit protection is
given in Figure 4.19.
Vref
Iref
R
D2
D1
Desat
C
BJT C
B
PWM
input
PWM
output
Figure 4.22 Circuit schematic of short circuit protection
87
E
The proposed internal circuit was just one way to incorporate PWM and
protection circuitry. The protection circuit did not include a short period latch-up, which
can be implemented using a D flip flop. The latch-up would be cleared at the next rising
edge; therefore the final latch-up was implemented on the control board. When BJT was
turned on, a constant current source was applied from the Desat pin to BJT. The voltage
across capacitor C slowly increased and created a blank time for VCE to settle down. The
blank time reduced the chance of mis-triggering before VCE reached stabilization. After
the blank time, the voltage between Desat and the ground built up, according Eq. (4.3).
(4.3)
where VD1, VD2, VCE and VR were the voltage drops across D1, D2, BJT, and R. Vdesat
was compared to a reference voltage, Vref. If Vdesat were higher than Vref, then the
comparator would put out a low signal and shunt down the PWM. By replacing VCE with
Ic∙Ron, Vdesat with Vref and VR with Iref∙R in Eq. (4.3), the current-trip level can be
determined according to Eq. (4.4).
(4.4)
where Ron is the steady state on-resistance of BJT. Since Vref, VD1, VD2, and Iref are fixed
values, the short circuit or over current protection level could be adjusted by changing R.
In the SiC BJT based inverter, if R = 5.6kΩ, Iref = 250µA, and VD1 = VD2 = 0.6V, the
estimated Vce to trigger the protection would be equal to 7.6 – (5600 x 250e-6 + 0.6 +
0.6) = 5V. A Buck circuit test was conducted to verify the estimated Vce and the
experimental results of Vdesat versus Vce are given in Figure 4.23.
88
Figure 4.23 Experimental result of desaturation protection circuitry. Ch1: Vbe 10V/Div,
Ch2: Vce 5V/Div, Ch3: Vdesat 5V/Div
In the figure, protection is initiated when Vdesat (orange) reaches 7.2V. The
measured corresponding forward voltage drop of BJT (blue) was 5.2V which is slightly
higher than the estimated 5V. This is likely due to the overestimated VD1 and VD2.
Voltage blocking diodes, D1 and D2 were replaced with multiple resistors (to evenly
distribute voltage stress) in series to improve the accuracy.
PWM was turned off
immediately and a fault signal was transmitted back to the control board to perform a
proper PWM shut down.
Since the gate drive board is normally placed very close to the power circuits, the
input pin is usually quite susceptible to electromagnetic inference due to dv/dt and di/dt.
In most cases, dv/dt would not cause severe EMI issues during testing because of the
small distributed parasitic capacitances between the power device and the gate drive
board. However, as the load current increased, higher noise magnitude was observed due
89
to magnetic coupling. According to the analysis in Appendix D, the coupled noise
voltage can be described using Eq. (4.5).
(4.5)
in which the noise was caused by mutual inductance, M, frequency, ω and the current
level in the noise source winding, I1. The noise can be coupled to the gate drive input
signal and cause gate mis-triggering if the noise level is higher than threshold values. In
general, the gate drive input has a hysteresis loop to improve noise reduction. A hex
inverting Schmitt trigger, as shown in Figure 4.24, will have a hysteresis loop, as
depicted in Figure 4.25.
Figure 4.24 Logic diagram of hex inverting Schmitt trigger
When VIN falls below VTH-, the Schmitt trigger output will be high. If the noise
added to the low VIN signal is higher than VTH- + VH (or VTH+), then the circuit would
emit a low voltage. VH is the hysteresis voltage which increases the input voltage
threshold. Similarly, the output state will change to high if a noise spike is lower than
VTH+ - VH (or VTH-) during high input voltage. The switching mechanism described
above is also depicted in Figure 4.26.
90
Noise
1
Noise Noise
2
3
5V
VTH+
VOUT
VH
VH
VIN
VTH0V
5V
VTH- VTH+
VIN
VOUT
0V
Time (s)
Figure 4.25 Characteristic of hysteresis
loop
Figure 4.26 Hex Schmitt trigger input and
output waveforms
However, the Schmitt trigger could be limited by the noise fluctuation level, such
as noise 3 in Figure 4.26. The noise spike fell below VTH- and resulted in mis-triggering
during output. If the duration of the noise is short or at a very high frequency, a simple
RC filter can be installed, which causes a longer propagation delay and eliminates some
narrow PWM pulses. Since the magnitude of noise was fixed, according to Eq. (4.5), the
input signal could be amplified first by using a buffer or an open-collector type of circuit
followed by a voltage divider, as shown in Figure 4.27.
V1
R3
VIN
R2
V2
VOUT
V1
C1
R1
Figure 4.27 A simple circuit to minimize
91
As shown in Figure 4.27, the voltage divider reduced the original amplified
signal, V1 to an acceptable input voltage range (0-5V) to prevent the Schmitt trigger from
mis-triggering. At the same time, the noise magnitude, VN was also reduced, according
Eq. (4.6).
(4.6)
If V1 = 15V and the peak input voltage is V2 = 5V, then VN would also be reduced
to one third. A small capacitor C1 can be added close to the gate drive input to further
improve noise reduction. This would be an ideal solution if the noise is coupled through
V1. In order to reduce the noise coupled through traces, R1, R2, and C1 must be placed
close to the IC input.
4.4
Control Circuits
The PWM control signals were generated from the control board, which mainly
included the digital signal processor (DSP), digital circuits for PWM conditioning and
proper PWM shut down during a fault scenario, rotor position signal circuits, and analogto-digital (AD) conditioning circuits for current, voltage, and temperature measurement.
The control board typically operates at 5V, 3.3V or lower and is located within the same
set of power circuits. The major noise on-board in our experiment was generated from
the high switching frequency and the speed of the digital circuits, oscillators, and
communication circuits. The noise would affect the analog signal-to-noise ratio (SNR)
through the power supply. Another noise source was coming from the external inputs,
92
including the rotor position signals, current, voltage, and thermistor signals, which are
located deep inside the heatsink and motor windings. Since these sensors are typically
located near the noise sources, the unwanted noise could easily couple into the control
board through external cables radiatively during high power operation. This section will
first discuss effective noise decoupling within the digital circuit, which is followed by
considerations to achieve significant CM and DM noise deduction for AD conditioning
circuits.
Shielding effectiveness was also analyzed and verified via both computer
simulation and experimental testing.
Digital circuits, such as DSP and logic ICs, typically have higher transient
currents due to the totem pole like output structure, as shown in Figure 4.28. During the
switching transient, the two transistors were partially turned on for a short period of time,
which induced transient current, Id.
LP1
LP3
VCC
LP5
dI
DC
LP2
IL
dI1
C1
CP1
VIN
Id
LP4
RL
LP6
Figure 4.28 Transient currents of digital IC
If the DC source is far away from the digital circuit, the stray inductances, LP1,
LP2, LP3, LP4 will interact with di and induce voltage ripples (Ldi/dt) across the power
supply. The magnitude of the voltage ripple can be reduced by decreasing the switching
speed, dt and/or minimizing the loop inductances. Reducing dt is usually not desired;
93
therefore, minimizing loop inductance is a more practical approach which is implemented
by adding a decoupling capacitor near the IC’s power supply pin. The capacitance must
be large enough to supply transient current and prevent voltage dips during digital IC
switches.
It would also provide a low impedance path for transient currents and
minimize the noise injected back to the power supply. However, effective power supply
decoupling becomes more challenging with the increasing clock frequencies and faster
rise/fall times of digital ICs. The impedance curve for a typical 2.2µF, 0.1µF, 10nF, and
1nF ceramic capacitors used for noise filtering are shown in Figure 4.29, in which the
resonance point for 2.2µF capacitor occurs much earlier than in other smaller capacitors
due to larger C and ESL. The 2.2µF capacitor also has the highest ESL of the other three
capacitors, which is expected to be less effective in noise reduction in the high frequency
range in comparison to the other three capacitors.
Impedance of 2.2uF, 0.1uF, 10nF, and 1nF
5
10
2.2uF
0.1uF
10nF
1nF
4
10
3
Impedance (Ohm)
10
2
10
1
10
0
10
-1
10
-2
10
4
10
5
10
6
7
10
10
Frequency (Hz)
8
10
9
10
Figure 4.29 Measured impedance for 2.2µF, 0.1µF, 10nF, and 1nF
94
One way to create an effective noise filter is to connect multiple capacitors with a
small ESL in parallel. Figure 4.30 (a) shows the impedance when three 0.1µF capacitors
are connected in parallel. Only one resonance at P3 (12MHz) was observed since all
three 0.1µF capacitors have the same characteristics, as given in Figure 4.29.
Impedance of Parallel Capacitors
3
10
(a)
(b)
(c)
(d)
2
10
0.1uF
0.1uF
2.2uF
0.1uF
//
//
//
//
0.1uF // 0.1uF
10nF // 1nF
2.2uF // 2.2uF
10nF // 2.2uF
Impedance (Ohm)
1
10
(P6)
0
(P4)
10
(P2)
-1
10
(P5)
(P7)
(P3)
-2
10
(P1)
-3
10
4
10
5
10
6
7
10
10
Frequency (Hz)
8
10
9
10
Figure 4.30 Impedance of multiple capacitors connected in parallel (a) 0.1µF // 0.1µF //
0.1µF, (b) 0.1µF // 10nF // 1nF, (c) 2.2µF // 2.2µF // 2.2µF, (d) 0.1µF // 10nF // 2.2µF
If the three capacitors are changed to 0.1µF, 10nF, and 1nF, the new impedances
would have multiple resonances at P3-7, as shown in Figure 4.30 (b). P3, P5 and P7
correspond to the self resonances of 0.1µF, 10nF, and 1nF capacitors, respectively. The
resonance point at P4 was caused by the interaction between ESL1 in 0.1µF and 10nF
impedance, as shown in Figure 4.31 (b). Since the impedance of 1nF was relatively high
compared to 10nF and 0.1µF, the resonance frequency can be estimated by utilizing Eq.
95
(4.7). Similarly, the equivalent circuit for P6 is given in Figure 4.31 (c), where 1nF
would resonate with ESL1//ESL2 and ESL3.
0.1µF
ESL1
10nF
ESL2
1nF
ESL3
ESL2
ESL1
C1
C2
ESL3
ESL1//ESL2
C3
C2
(a)
(b)
C3
(c)
Figure 4.31 Equivalent circuit of (a) 0.1µF, 10nF, and 1nF connected in parallel, (b)
resonant at P4, (c) resonant at P6
(4.7)
According to Figure 4.31 (a) and (b), using 10nF and 1nF capacitors would
actually degrade the decoupling performance, especially at P4 and P6. However, the self
resonance at P7 due to 1nF would result in lower impedance compared to the other
scenario.
In some cases, larger capacitances are necessary to meet the high di/dt
requirement for microcontrollers or high speed buffer ICs. Multiple ceramic capacitors,
such as 2.2µF or higher, were used to reduce the voltage ripple and board size. When we
compare Figure 4.30 (c) and (d), the mix capacitor combination contained several
resonances at P2-5 as expected; however, it had lower impedance from 40 to 200MHz
due to lower ESL. Based on this analysis, multiple capacitors with the same value and
low ESL are preferred because they are more predictable and more efficient at
96
minimizing the resonance between ESL and other capacitors. The capacitors should be
placed near the supply voltage pins in order to minimize the loop inductances as well.
The current sensor output voltage span is not always within the analog-to-digital
converter (ADC) input voltage range. In this case, the dynamic range of ADC would not
be fully utilized. In addition, the sensor is located far away from the conditioning circuit
and the output signal is transmitted through wires where noise can be coupled through an
electromagnetic field generated by external noise sources or through the voltage supply.
This could lead to errors in the readings for the feedback control loop and also increase
the chance of damage being done to the ADC module if the noise spike is higher than the
absolute maximum rating. In order to preserve the SNR of the low-level signals, an AD
conditioning circuit using an operational amplifier (op amp) could be installed to achieve
the required ADC input voltage span and noise filtering. An AD conditioning circuit,
shown in Figure 4.32, was used to demonstrate the key elements affecting the SNR.
97
VCC
VCC
R1
1k
V1
3.3Vdc
VCC
U1A4
3
R2
1k
1
V_BIAS
op amp
V-
C2
0.1u
OUT
C1
0.1u
0
V+
+
2
- 11
0
0
0
0
V+
V-
V_BIAS
V2
R3
0.1
0
V4
R7
0
FREQ = 30e3
VAMPL = 0.5
VOFF = 0
C3
500p
V+
FREQ = 30e3
VAMPL = 0.5
VOFF = 0
V3
FREQ = 1000
VAMPL = 2
VOFF = 0
0.1
R5
R4
10k
VCC
U2A4
3
V+
+
15k
R6
V5
FREQ = 1e6
VAMPL = 0.2
VOFF = 0
15k
- 11
R8 10k
V-
1
OUT
2
op amp
V-
0
V_OUT
V+
V-
C4 500p
Figure 4.32 AD conditioning circuit with CM and DM noise consideration at signal input
In Figure 4.32, V3 represents the differential input signal from sensor. V2 and V4
are the CM noise voltage source, while V5 represents DM noise. Since the peak of V3
was pure AC and op amp was operating from a single power supply, the appropriate bias
voltage would be half of the supply voltage to prevent output voltage clipping. If the
ADC module were operating at 3.3V, then 1.65V bias voltage would maximize the ADC
input resolution for the AC signal. The input and output voltage relationship can be
derived using Eq. (4.8).
(4.8)
If R5 = n∙R4, R6 = m∙R8 and m = n, then Eq. (4.8) can be simplified into Eq. (4.9).
98
(4.9)
To satisfy Eq. (4.8), n must be equal to m; however, R5 and R4 do not necessarily
have to be equal to R6 and R8. The input terminal is said to be unbalanced if R5 and R4
are not equal to R6 and R8. To demonstrate CM noise immunity effectiveness for
unbalanced and balanced input impedance, the circuit in Figure 4.32 was setup in
PSPICE with CM noise injected from the input side. If R6 = 15kΩ and R8 = 10kΩ, the
resistors for an unbalanced condition would be defined as R5 = 1.5kΩ and R4 = 1kΩ. The
CM noise frequency and peak-to-peak voltage were set to 30kHz and 1V, respectively.
The AC input signal had a frequency of 1kHz and a peak-to-peak voltage of 4V. The
DM noise source, V5 was removed for this test. Based on Eq. (4.9), the calculated output
voltage for both cases was equal to 1.33V + 1.65V = 2.98V. The simulation result of
unbalanced and balanced input impedance is given in Figure 4.33 (a) and (b),
respectively. In Figure 4.33 (a), a noticeable high frequency AC ripple was observed at
VOUT, yet there was no significant high frequency noise in the balanced structure, as
shown in Figure 4.32 (b).
A Fast Fourier Transformation (FFT) of an unbalanced
structure, given in Figure 4.32 (c), shows that approximately 0.1V peak noise occurred at
30kHz in addition to the desired output signal. CM noise reduction performance would
be degraded if the positive and negative terminals of the op amp did not have the same
input impedance. At higher frequencies, the stray inductance between sensor signal
output and op amp terminal input would become not negligible. Therefore, the length of
99
the input traces must be kept as similar as possible for maximum CM noise rejection for
all frequencies.
VOUT (unbalanced)
Voltage (V)
VBIAS
VIN
(a)
Voltage (V)
VOUT (balanced)
(b)
Voltage (V)
VBIAS @ 0Hz
Time (s)
VOUT (unbalanced)
VAC @ 1kHz
VCM @ 30kHz
(c)
Figure 4.33 Output voltage simulation result of (a) unbalanced, (b) balanced input
impedance. (c) FFT result of unbalanced input impedance
In addition to CM noise, the analog signal is also very susceptible to DM noise
due to high frequency components in the power supply. Normally, DM noise occurs at
frequencies much higher than the sensor’s output signal, so a suitable C4 can be added
across R8 to form a first order active low pass filter, as shown in Figure 4.32. The size of
100
C4 is based on the selected cutoff frequency, according to Eq. (4.10). The same capacitor
also must be inserted across R4 in order to maintain the same input impedance for both
terminals.
(4.10)
A small RC low pass filter at the op amp output is recommended to remove any
DM noise coupled into the trace between the op amp and the ADC input. The filter
capacitor must be placed close to the ADC input to create a low impedance path for
effective noise filtering.
In addition to the noise generated by the digital circuits in the control board, more
disruptive noise could be joined to the external signals, such as in the rotor position
feedback, the thermistor enclosed in the windings for temperature measurement, and
other external digital input and output signals. Shielded cable is normally used to provide
noise reduction from the capacitive and magnetic effects.
However, the shielding
effectiveness can be greatly reduced with improper termination at both ends. A circuit
configuration, shown in Figure 4.34, was setup to investigate the near field coupling
effect of shielded cable. Conductor 1 carried the noise source, which could be the result
of the three phase AC output cables, high frequency communication cables or the
common reference frame. Conductors 2 and 3 carried low voltage signals, such as
encoders and hall-effect position signals, etc. The two conductor outputs were connected
to a high resistive load, which is equivalent to the IC input. An un-terminated shield was
placed across conductors 2 and 3.
101
Diameter of wire 1, 2, and 3 is 1mm
Conductor 1
I1
10mm
Shielding layer
Conductor 2
I2
Conductor 3
I2
RLoad
1.5mm
Diameter of inner shield 1.75mm
Diameter of outer shield 2mm
Figure 4.34 Electromagnetic effects of shielded cable
A lumped circuit network was employed to represent the noise coupling effect.
Parasitic capacitors were used to represent a time varying electric field between two
conductors.
If the magnetic field couples between two conductors, then a mutual
inductance can be used to characterize the coupling effect. By applying this concept, the
setup in Figure 4.34 can be transformed into an equivalent circuit in Figure 4.35.
L1
1a
M13 M12
M1sh
Rsh
+
Msh2 Msh3
M23
I2
_
V1sh
+
V2sh
_ _
V3sh
+ 2b
CP2
L2
I2
1b
CP1
Lsh
2a
3a
I1
+
_
CP3
_
+
Vsh2
+
V13
L3
_
V12
3b
_
+
Vsh3
Figure 4.35 Equivalent circuit of shielded conductors
102
In Figure 4.35, CP1 represents the parasitic capacitance between conductors 1 and
2. CP2 and CP3 represent the parasitic capacitances between the shield and the inner
conductors. L1, L2, L3, and Lsh are the self inductances of conductors 1, 2, 3, as well as
the shield. When there is current flowing through conductor 1, there will be mutual
inductances, M1sh, M12, and M13 coupling into the shield, conductor 2 and 3, respectively.
If both ends of the shield are not connected to the ground, then CP1, CP2, and CP3 will
provide a path to allow I1 to flow into the load. In addition to capacitive coupling, mutual
inductances, M1sh, M12 and M13 will also induce a voltage drop in the shielding,
conductors 2 and 3, according to Eq. (4.11).
where X = sh, 2 and 3
(4.11)
To minimize the capacitive coupling effect, one end of the shield was connected
to the ground to form a path to bypass the noise current instead of via signal conductors.
However, the induced voltages in conductors 2, 3 and the shield due to M12, M13, and
M1sh remained un-changed. If the other end of the shield was also connected to the
ground, then Ish would be induced due to V1sh, as given in Eq. (4.12).
(4.12)
In which Rs is the equivalent resistance, including the shielding layer and ground
connection. Lsh is the self inductance of the shield. Due to Ish and Msh2, Vsh2 was
generated in conductor 2 with the opposite polarity of V12 due to the opposite current
direction between I1 and Ish. The total noise on conductor 2 was changed, as seen in Eq.
(4.13).
103
(4.13)
The self inductance of the shield is defined in Eq. (4.14). If all the flux generated
by the shield, Φsh encircles the inner conductors, the mutual inductance between the
shield and inner conductors would be equal to Eq. (4.15). M1sh would also have similar
value to M12 and M13 since the distance between the shielded cable and conductor 1 is
approximately equal.
(4.14)
(4.15)
Ideally, noise V2N, in Eq. (4.13), could be reduced to 0V if Rs = 0Ω, Lsh = Msh2,
and M1sh = M12. Therefore, the noise generated by capacitive and inductive coupling can
be minimized when the cable is properly shielded. To verify the shielding analysis, the
PSPICE computer simulation based on the test setup in Figure 4.34 was performed. The
parameters of self and mutual inductances and wire resistances were obtained through
Q3D FEA, as shown in Table 4.1. The result confirmed that the mutual inductance, M1sh
(363nH) was approximately equal to M12 (363nH) and M13 (362nH). The self inductance
Lsh (527nH) also had a magnitude approximately equal to Msh2 (529nH) and Msh3 (529nH).
104
Wire 1
Wire 2
Wire 3
Shield
(Ω)
(nH)
(Ω)
(nH)
(Ω)
(nH)
(Ω)
(nH)
0.01
687
0
363
0
362
0
363
Wire 1
0
363
0.01
685
0
-550
0
529
Wire 2
0
362
0
-550 0.01
685
0
529
Wire 3
0
363
0
529
0
529
0.003
529
Shield
Table 4.1 Extracted self and mutual inductance of test setup in Figure 4.34
The coupling coefficient, k, between two conductors can be calculated using the
method given in Section 3.4. The desired input signal was represented with a 10kHz
square waveform switching from 0 to 5V. The introduced noise in conductor 1 was
switching at 100kHz at 50% duty cycle. The final PSPICE model is given in Figure 4.36.
Figure 4.36 Equivalent circuit of the shielded cable
Figure 4.37 shows the simulation result for three shielding configurations. When
the shield was not connected to the ground at both ends, the noise detected by the load
105
side resistor had a peak to peak voltage of VNPP = 1.2V, as shown in Figure 4.37 (a). ,
VNPP was reduced to 0.6V, as illustrated in Figure 4.37 (b), when one end of the shield
was grounded on the Rload side. When both ends of the shield were grounded, as in Figure
4.36, VNPP was further decreased to 0.03V, as depicted in Figure 4.37 (c). Each noise
spike occurred during the switching transient of the introduced noise. Since it was
switching at 100kHz at 50% duty cycle, the period between each spike was 5µs.
(a) Both end are not grounded
(b) Grounded at one end
(c) Grounded at both ends
Figure 4.37 Simulation result of magnetic coupling with shield (a) un-grounded, (b)
single end grounded, (c) both end grounded
An experiment was performed to verify the proposed shielding analysis. The low
voltage signal was generated using a function generator switching at 10kHz from 0 to 5V.
The signals, including the segment of interest and coupled noise, were measured across
the 10kΩ load resistor. The cable was placed near the GaN based switched-capacitor
circuit, which was switching at 304kHz at 50% duty cycle. The experimental results of
the three shielding configurations discussed above are given in Figure 4.38.
The
measured VNPP when both ends of the shield were not grounded, shown in Figure 4.38
(a), was 1.6V, which was the highest of the three scenarios. When one end of the shield
106
was connected to the load side ground, as shown in Figure 4.38 (b), VNPP was reduced to
0.7V. By connecting both ends of the shield to the source and load side ground, VNPP
was further reduced to 0.4V. Despite the fact that the noise could never be completely
removed due to the unshielded portion between the function generator output and the
cable input, this experiment confirmed that a high percentage of noise reduction is
possible when the cable is properly shielded.
The uncovered portion should be
minimized in order to achieve a maximum shielding effect.
4µs
VNPP = 1.6V
VNPP = 0.7V
1V/Div
(a)
(b)
VNPP = 0.4V
(c)
Figure 4.38 Experimental result of magnetic coupling with shield (a) un-grounded, (b)
single end grounded, (c) both end grounded
107
4.5
Summary
In this chapter, EMI issues within a three phase inverter system for traction motor
drive application were discussed. The major noise sources were generated from power
circuits due to the high dv/dt and di/dt. Voltage oscillation across power devices must be
minimized in order to reduce the capacitive coupling effects. Therefore, laminated DC
bus bar and snubber capacitors were incorporated to minimize the loop inductances
across the power devices. The input and output of the gate drive are susceptible to EMI
due to the effects of near field couplings as well as the large inherent capacitances of the
power devices. During switching transients, the chance of the gate mis-triggering would
increase if the gate drives were not able to maintain a low impedance path in the off state.
Despite the isolated power supply and gate drive designs, the noise coupled onto external
inputs such as current, voltage, thermister, and other external digital and analog input
signals could interfere with the control board. These types of noise can be mitigated by
connecting both ends of the shielding cable to the ground based on the shielding analysis.
Another noise source emanating from the control board is voltage ripple, Ldi/dt generated
by digital circuits. The use of multiple capacitors with equivalent values is recommended
because they allow for predictable impedance. This could reduce voltage ripple in the
power supply and improve the SNR of analog signal. AD conditioning circuits should be
installed to tune the sensor output signals to a suitable range for the ADC module. The
signals that are carried through cable or traces could pick up substantial amount of noise
during high power operation; therefore, the positive and negative inputs of op amps must
be balanced to achieve the best CM noise reduction.
108
Chapter 5: Conclusion and Future Work
5.1
Conclusion
The major goals of this work were to develop a systematic way to diagnose EMI
issues in power electronic circuits utilizing computer simulation and experimental testing.
Based on the identified issues, effective measures to improve the design were proposed
and verified through simulation and experimental testing. The major contributions of the
research presented in this dissertation are discussed below:

We proposed a high frequency circuit model of CM choke with a range of accuracy
of up to 100MHz.
In addition, we provided detailed procedures for parameter
extraction based on the measurements of four different circuit configurations. The
PSPICE implementation method was also demonstrated and correlated well with the
experimental results. Since the permeability of the magnetic core has a non-linear
effect as the frequency increases, the extracted LCM would result in a higher error rate
at the first resonance point. The resonance caused by LDM (leakage inductance of CM
choke) interacting with EPC was also well matched. The impedance between the two
windings is the key element which would interact with LCM and LDM above 50MHz
and induce additional resonance. In the derived model, EPC was identified as the key
parameter limiting the high frequency performance of CM choke. Combing with the
109
capacitor circuit model, the performance and effective grounding of the EMI filter
were also evaluated.

The PSPICE circuit model of a GaN based switch-capacitor circuit was used to
demonstrate the modeling procedures for conducted noise emission investigation in
an active device. The major components in the circuit included a GaN device, stray
inductances of PCB traces, mutual coupling effect among traces, capacitors in the
main loop, and the model of LISN. The IV characteristics and capacitances of a GaN
device model can be extracted using a curve tracer and can be curve fit to a PSPICE
model. An alternative method is to obtain these parameters from datasheet and
perform a curve fit process. The stray inductance and coupling effect of traces can be
extracted using a FEA tool, which does not require construction of an actual board.
The capacitor model is simple but has proven to be one of the key elements affecting
the soft switching characteristics and switching behavior of the device. The goal was
to accurately model the noise source and performance to predict the conducted noise
emission.

The switch capacitor was affected by CM noise due to the rapid voltage changes at
nodes and parasitic capacitances. In addition, the fast switching speed provided an
excitation source for stray inductance and output capacitance of the device, which
would induce undesired high frequency oscillation across VDS and ID. In order to
minimize conducted noise emission, particularly CM noise, we utilized the balance
circuit structure based on a Wheastone Bridge.
By analyzing the decoupled
equivalent circuit of each noise source, we were able to identify the common location
110
of a parallel capacitor which would result in maximum balance structure.
Additionally, the locations which might generate higher overall noise is identified and
minimized in the layout stage. The resulted improvement is very low cost yet offers
effective noise reduction to simply EMI filter design.

In addition to conducted noise, EMI issues within a SiC based three phase inverter
system designed for motor drive application were also examined. Due to the fixed
circuit topology, a laminated DC bus structure and a film capacitor were installed to
minimize the loop inductance in order to reduce voltage overshoot and oscillation.
The gate drive must provide sufficient margins to prevent partial turn on during
switching transients. Since the coupled noise level was fixed, increasing the PWM
voltage level at the input with a voltage divider would minimize the impact of gate
mis-triggering. Digital circuitries generally have a high slew rate and operate at high
frequencies; therefore, the power supply must be properly decoupled by paralleling
multiple capacitors with same value to prevent unpredictable resonance levels at high
frequencies. The AD conditioning circuit was installed to process external analog
signals, such as current, voltage, thermisters, etc which are carried through cables
normally.
In order to maximize the CM noise rejection ratio, the positive and
negative input impedance of the op amp must be balanced. Both ends of the shielding
layer of a cable must be tied to the board and the signal ground in order to produce
current which transforms into a voltage source within the signal conductor to cancel
out the noise source.
111
5.2

Future Work
Include the non-linear permeability property of magnetic components in the CM
choke model to better describe LCM in a high frequency range.
This can be
implemented by including a table of permeability versus frequency into the
simulation and using linear interpolation to obtain all the values of various
frequencies for inductance calculation. Accurate LCM would improve the estimated
resonance frequencies caused by interaction with filter capacitors.

Investigate capacitive and inductive coupling effects within the electrical components
of the EMI filter. Since WBG devices operate at higher frequencies, the accuracy of
the model should be extended up to 100MHz in order to identify the major coupling
paths and obtain the most effective type of filter.

Optimize stray inductance distribution within the switch capacitor circuit to achieve a
maximally balanced circuit structure.
This would minimize the size of parallel
capacitors and satisfy leakage current requirements in response to certain EMC
regulations.

Use experimental testing to determine that parasitic capacitances between the
switching device and the common reference plane, such as a heatsink, to improve the
accuracy of CM noise prediction.
Direct measurement of this parameter is a
challenging task due to the layout structure and limited range of accuracy of
commercial fixtures.
Therefore, an indirect method of extraction should be
investigated in the near future.
112

Investigate different control strategies for switched-capacitor circuit to reduce the
peak of the total conducted noise or evenly distribute noise frequency spectrum.
Explore the potential of utilizing extra switching states in the circuit to realize CM
noise cancellation.
113
Appendices
Appendix A:
Impedance of Capacitors
1µF Ceramic Capacitor
Impedance (Ω)
1.00E+01
1.00E+00
1.00E-01
Measured data
Estimated data
1.00E-02
1.00E-03
1.00E+05
1.00E+06
Frequency (Hz)
1.00E+07
Figure A.1 1µF ceramic capacitor used for CIN, C1, and C2
2000µF Electrolytic Capacitor
Impedance (Ω)
1.00E+02
1.00E+01
1.00E+00
Measured data
Estimated data
1.00E-01
1.00E-02
4.00E+01
4.00E+03
4.00E+05
Frequency (Hz)
4.00E+07
Figure A.2 Impedance of a 2000uF electrolytic capacitor
114
200µF Film Capacitor
1.00E+02
Impedance (Ω)
1.00E+01
1.00E+00
1.00E-01
Measured data
1.00E-02
Estimated data
1.00E-03
1.00E-04
1.00E+03
1.00E+04
1.00E+05
1.00E+06
Frequency (Hz)
1.00E+07
Figure A.3 Impedance of a 200uF film capacitor
115
Appendix B:
Transmission Line Effect
Extra care must be taken when directly measuring high frequency signals. A
typical passive probe, such as TPP1000, has a bandwidth of up to 1GHz, terminal
impedance of 10MΩ, and an equivalent parallel capacitance of 3.9pF. The equivalent
terminal impedance will be reduced to approximately 400Ω at 100MHz. This will affect
the port voltage measurement since it is no longer having high impedance. The measured
data would not be credible if there were an impedance mismatch in the setup. If a probe
is setup for voltage measurement, as shown in Figure B.1, the transmitted voltage
waveform can be expressed as Eq. (B.1) [1].
(B.1)
RS
Cable
VS
RL
ZC
V
-
V
+
z=0
z=L
Figure B.1 Schematic of a voltage measurement setup
Where V+ is the forward traveling wave in the +z direction, V- is the backward traveling
wave in the -z direction, t is the actual time of the incident wave, z is the position along
116
the cable, and v is the velocity of the wave. At position z=0, the initial forward traveling
wave is,
(B.2)
The one-way time delay for a wave to travel from position z=0 to z=L is defined
as,
(B.3)
And the reflection coefficients at the load and source side are defined as,
(B.4)
(B.5)
So the first reflected wave at position z=0 can be found based on Eq. (B.4).
(B.6)
Applying similar steps from above, the total voltage at position z=0 and z=L are
expressed as,
(B.7)
117
(B.8)
According to Eq. (B.8), measurement using an oscilloscope would be incorrect if
there were a slight mismatch to the load impedance, such as using TPP1000. The cable
impedance is usually a fixed value, while the terminal impedance fluctuates due to the
small parallel capacitance.
However, if the cable impedance matches the terminal
impedance, then ΓL would be 0 and Eq. (B.8) would be reduced to,
(B.9)
In Eq. (B.9), only time delay is to be compensated. In order to minimize the
parasitic effects in the measurement, a RG-58 cable is recommended because the cable
has stable 50Ω impedance at frequencies of up to a few gigahertz. A cable with an SMA
connector is recommended for the measurement of higher frequencies.
The characteristic impedance, Z0 and time delay, TD of the 12 inch RG-58 cable
can be obtained based on Eqs. (B.10) and (B.11). Figure B.2 and Figure B.3 are the
measured characteristic impedance and time delay of the 12 inch RG-58 cable used in the
experiment. If the load impedance matches the cable impedance, then there should be no
effect on the magnitude measurement except a time delay.
(B.10)
(B.11)
118
Impedance, Z0 (Ω)
51.00
50.50
50.00
Impedance, Z0 (Ω)
49.50
49.00
5.00E+05
5.00E+06
5.00E+07
Frequency (Hz)
Time Delay, TD (s)
Figure B.2 Characteristic impedance, Z0 of the 12 inch RG-58 cable
5.000E-09
4.500E-09
4.000E-09
3.500E-09
3.000E-09
2.500E-09
5.00E+05
Delay, T0 (s)
5.00E+06
5.00E+07
Frequency (Hz)
Figure B.3 Time delay, TD of the 12 inch RG-58 cable
Measuring equipment, such as a network and impedance analyzer have a limited
range of accuracy based on different fixtures or measurement methods. Use of the
network analyzer requires an estimation of the impedance range of the DUT.
119
Appendix C:
Capacitive Coupling Mechanism
Theoretical analysis was carried out to better understand the EMI coupling
methods. Generally, the noise couplings methods can be divided into three types: electric
(capacitive) field coupling, magnetic (inductive) field coupling, and a combination of
electric and magnetic field (electromagnetic field coupling). Electric field coupling is the
result of interaction between conductors through an electric field.
Magnetic field
coupling involves magnetic field interaction between two circuits.
The PWM technique is often applied to achieve variable voltage and frequency
control. Consequently, rapid voltage change across drain and source of the MOSFET is
created.
The parasitic capacitances between conductors will form a path for the
undesired high frequency component inductance to affect the susceptible conductors. A
simple circuit, shown in Figure C.1 (a), is used to explain the mechanism of capacitive
coupling.
Conductor 1
VS1
C12
CSG
Conductor 2
CRG
I1 = jωC12VS1
R2 VN
(a)
(b)
Figure C.1 (a) Capacitive coupling circuit; (b) noise coupled on Conductor 2
120
In the circuit, VS1 represents the source of the interference generated by dv/dt.
CSG is the total capacitance of Conductor 1 to the ground. Similarly, CRG represents the
total capacitance of Conductor 2 to the ground. R2 is the resistance of conductor 2 to the
ground. The noise voltage, VN is measured at R2 as,
(C.1)
If R2 has the following characteristics, the noise voltage can be simplified to,
(C.2)
(C.3)
The assumption made in Eq. (C.2) is usually applicable for the case when
conductor 2 is connected to the input side of logic ICs. This equation shows that the
induced voltage level is strongly related to the load resistance, coupling capacitance, and
the frequency and magnitude of the noise source. As frequency increases, it is possible to
reach the scenario shown in Eq. (C.3) in which the magnitude of the noise voltage is
fixed and independent from frequency. So the equilibrium circuit of the noise generated
by dv/dt or the electric field coupling is represented as a current source connected in
parallel to the receiving circuit, as shown in Figure C.1 (b). Since the magnitude and
frequency of a noise source are usually fixed, the two options to reduce the noise voltage
are to decrease the coupling capacitance C12 and create a lower resistance path for the
receiving circuit. With proper planning of the layout, increasing the physical distance
121
between conductor 1 and 2, or providing shielding to the conductors can lessen the
effectiveness of the coupling.
122
Appendix D:
Magnetic Coupling Mechanism
Another coupling method is caused by the magnetic field generated by current
flowing through a conductor or MOSFET. If magnetic flux generated in one circuit
induces a current in another, then this causes mutual inductance between the two circuits.
The circuit in Figure D.1 (a) is used to explain the magnetic coupling mechanism
between two conductors.
i1
i2
M
VN = ± jωMI1
VS1
L1
Circuit 1
L2
VN
Circuit 2
(a)
(b)
Figure D.1 (a) Inductive coupling circuit; (b) noise coupled on Conductor 2
The time domain voltage equations for circuit 1 and 2 in Fig. 3 are,
(D.1)
(D.2)
L1 and L2 are the self inductance in circuit 1 and 2. M is the mutual inductance
between the two circuits. i1 is the source of noise, which can be represented as a
123
sinusoidal component with various frequencies and magnitudes. If
and
, then,
(D.3)
The derived Eq. (D.3) shows that the noise voltage is inductively coupled with the
noise current generated in conductor 1. The induced noise due to the high di/dt magnetic
field coupling can be represented as a voltage source connected in series to the receiving
circuit, as shown in Figure D.1 (b). The voltage magnitude is related to the mutual
inductance, the magnitude and frequency of the current. In order to reduce the noise
voltage, the physical separation between the source and sensitive circuits must be
increased in order to reduce the mutual inductance. Twisted cable can be used to force
current flow in the twisted cable instead of the ground plane. Shielding is useful when
maximum noise blocking is required but would add cost and complexity to the overall
design.
124
Appendix E:
Selecting Dielectric Material for IMS
Selecting the correct dielectric material is one of the key elements for optimizing
the performance of T-Clad circuit board because it will ensure thermal performance of it.
T-Clad IMS dielectric material has polymer and ceramic blend properties which provides
excellent electrical isolation properties and low thermal impedance. The polymer layer
will provide electrical isolation with high bonding strength to prevent deterioration from
high temperatures. Ceramic filler will enhance thermal conductivity and maintain high
dielectric strength. Below is a summary table of dielectric characteristic of MP-06503
single layer board.
Single Layer
Thermal Performance
Dielectric Performance
Impedance
Permittivity
Conductivity Breakdown
2
[°C cm /W] /
[Dielectric
[W/m-K]
[kVAC]
[°C in2/W]
Constant]
MP - 06503
3 / 76
0.58 / 0.09
1.3
8.5
6
Table E.1 Summary of dielectric characteristic of MP-06503 single layer board
Part
Number
Material
MP
Thickness
[.000"/um]
U.L. Solder Limit Rating
U.L. RTI - Electro / Mechanical
300°C / 60 seconds
130°C / 140°C
Table E.2 Operating temperatures
The figure below shows the predicted lifetime for various operating temperatures.
This can be used as a reference guide if tests are conducted at higher temperatures.
125
Figure E.1 Lifespan prediction at different operating temperature
Current carrying capability is the key consideration when it comes to
interconnecting components. Higher currents are possible when using a T-Clad circuit
trace due to the fact that heat generated from i2R can dissipate quickly. The equation
below is used to determine the minimum trace width requirement:
(E.1)
WC
TS
I
RS
TC
KS
TRISE
Conductor width
Dielectric thickness
Current
Circuit sheet resistivity = 1.78x10-8 Ω∙m/TC
Foil thickness
Thermal conductivity of the Dielectric
Allowable temperature rise (Δ)
Meters
Meters
Amps
Ohms
Meters
W/m-K
K
The minimum trace width in the design is calculated as shown below. The circuit
is designed with 4 oz copper; the total thickness of the board is equal to 140 μm. In
addition, the allowable temperature rise is set to 10 K in the calculation.
126
127
Appendix F:
List of Principle Symbols
The list of principle symbols used in this dissertation are given below.
CX
X capacitors are connected across power line for DM noise filtering
CY
Y capacitors are connected across power line for CM noise filtering
LDM
Differential mode inductance
LCM
Common mode inductance
λCM
CM flux linkage
λDM
DM flux linkage
L1
Self inductance of winding 1
L2
Self inductance of winding 2
M
Mutual inductance
K
Coefficient of coupling
Lline
Stray inductance of wire
Z1
Coupling impedance between winding 1 and 2
fCM
Resonant frequency when CM choke is connected as CM configuration
RDC
DC resistance of CM choke
EPC
Equivalent parallel capacitance
EPR
Equivalent parallel resistance
ESL
Equivalent series inductance
ESR
Equivalent series resistance
Lleakage
Leakage inductance of CM choke
fleakage
Resonant frequency when CM choke is connected as DM configuration
IL
Insertion loss
VDS
Voltage across drain and source terminals of GaN device
128
ID
Drain current of GaN device
Ca…n
Parasitic capacitance between drain and common reference plane
L11…15
Self inductances of traces 1-5 for 1st half of the switched-capacitor circuit
L22…25
Self inductances of traces 1-5 for 2nd half of the switched-capacitor circuit
CBE
Capacitance between base and emitter
CBC
Capacitance between base and collector
CCE
Capacitance between collector and emitter
Ibase
Base current of SiC BJT
RON
On-resistance of SiC BJT
129
References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Ott, Henry W., “Electromagnetic compatibility engineering,” Wiley. com, 2011.
Paul, Clayton R., “Introduction to electromagnetic compatibility,” New York:
Wiley, 1992.
Shockley, W., “A Unipolar “Field-Effect” Transistor,” Proceedings of the IRE ,
vol.40, no.11, pp.1365,1376, Nov. 1952
Erkuan, Z.; Lipo, T.A., "Improvements in EMC performance of inverter-fed
motor drives," Industry Applications, IEEE Transactions on , vol.31, no.6,
pp.1247,1256, Nov/Dec 1995
Ogasawara, S.; Ayano, H.; Akagi, H., “Measurement and reduction of EMI
radiated by a PWM inverter-fed AC motor drive system,” Industry Applications,
IEEE Transactions on , vol.33, no.4, pp.1019,1026, Jul/Aug 1997
Ran, L.; Gokani, S.; Clare, J.; Bradley, K.J.; Christopoulos, C., “Conducted
electromagnetic emissions in induction motor drive systems. I. Time domain
analysis and identification of dominant modes,” Power Electronics, IEEE
Transactions on , vol.13, no.4, pp.757,767, Jul 1998
Revol, B.; Roudet, J.; Schanen, J.-L.; Loizelet, P., “EMI Study of Three-Phase
Inverter-Fed Motor Drives,” Industry Applications, IEEE Transactions on ,
vol.47, no.1, pp.223,231, Jan.-Feb. 2011
Von Jouanne, A.; Enjeti, P.; Gray, W., “The effect of long motor leads on PWM
inverter fed AC motor drive systems,” Applied Power Electronics Conference and
Exposition, 1995. APEC '95. Conference Proceedings 1995., Tenth Annual , vol.,
no.0, pp.592,597 vol.2, 5-9 Mar 1995
Erdman, J.M.; Kerkman, R.J.; Schlegel, D.W.; Skibinski, G.L., “Effect of PWM
inverters on AC motor bearing currents and shaft voltages,” Industry
Applications, IEEE Transactions on , vol.32, no.2, pp.250,259, Mar/Apr 1996
Chen, S.; Lipo, T.A.; Fitzgerald, D., “Modeling of motor bearing currents in
PWM inverter drives,” Industry Applications, IEEE Transactions on, vol.32, no.6,
pp.1365,1370, Nov/Dec 1996
Skibinski, G.; Pankau, J.; Sladky, R.; Campbell, J., “Generation, control and
regulation of EMI from AC drives,” Industry Applications Conference, 1997.
130
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
Thirty-Second IAS Annual Meeting, IAS '97., Conference Record of the 1997
IEEE , vol.2, no., pp.1571,1583 vol.2, 5-9 Oct 1997
Mutoh, N.; Ogata, M.; Gulez, K.; Harashima, F., “New methods to suppress EMI
noises in motor drive systems,” Industrial Electronics, IEEE Transactions on ,
vol.49, no.2, pp.474,485, Apr 2002
Gulez, K.; Adam, A.A., “High-Frequency Common-Mode Modeling of
Permanent Magnet Synchronous Motors,” Electromagnetic Compatibility, IEEE
Transactions on , vol.50, no.2, pp.423,426, May 2008
Maillet, Y.; Rixin, L.; Wang, S.; Wang, F.; Burgos, R.; Boroyevich, D., “HighDensity EMI Filter Design for DC-Fed Motor Drives,” Power Electronics, IEEE
Transactions on , vol.25, no.5, pp.1163,1172, May 2010
Akagi, H.; Doumoto, T., “A passive EMI filter for preventing high-frequency
leakage current from flowing through the grounded inverter heat sink of an
adjustable-speed motor drive system,” Industry Applications, IEEE Transactions
on , vol.41, no.5, pp.1215,1223, Sept.-Oct. 2005
Chen, H.; Iu, H.H.-C.; Zhao, Y., “Economic Integration Based Solution for EMI
Noise in Switched Reluctance Motor Drive,” Magnetics, IEEE Transactions on ,
vol.48, no.2, pp.859,862, Feb. 2012
Chen, C., “Novel EMC debugging methodologies for high-power
converters,” Electromagnetic Compatibility,
2000.
IEEE
International
Symposium on , vol.1, no., pp.385,390 vol.1, 2000
Chen, C.; Xu, X., “Modeling the conducted EMI emission of an electric vehicle
(EV) traction drive,” Electromagnetic Compatibility, 1998. 1998 IEEE
International Symposium on , vol.2, no., pp.796,801 vol.2, 24-28 Aug 1998
Zhu, H.; Lai, J.-S.; Hefner, A.R., Tang, Y.; Chen, C., “Modeling-based
examination of conducted EMI emissions from hard and soft-switching PWM
inverters,” Industry Applications, IEEE Transactions on , vol.37, no.5,
pp.1383,1393, Sep/Oct 2001
Zhu, H.; Hefner, A.R.; Lai, J.-S., “Characterization of power electronics system
interconnect parasitics using time domain reflectometry,” Power Electronics,
IEEE Transactions on , vol.14, no.4, pp.622,628, Jul 1999
Dixon, D.S.; Obara, M.D.; Schade, N., “Finite-element analysis (FEA) as an EMC
prediction tool,” Electromagnetic Compatibility, IEEE Transactions on , vol.35,
no.2, pp.241,248, May 1993
Lai, J.-S.; Huang, X.; Pepa, E.; Chen, S.; Nehl, T.W., “Inverter EMI modeling and
simulation methodologies,” Industrial Electronics, IEEE Transactions on , vol.53,
no.3, pp.736,744, June 2006
131
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
Chen, S.; Nehl, T.W.; Lai, J.-S.; Huang, X.; Pepa, E.; De Doncker, R.; Voss, I.,
“Towards EMI prediction of a PM motor drive for automotive
applications,” Applied Power Electronics Conference and Exposition, 2003.
APEC '03. Eighteenth Annual IEEE , vol.1, no., pp.14,22 vol.1, 9-13 Feb. 2003
Ikeda, N.; Niiyama, Y.; Kambayashi, H.; Sato, Y.; Nomura, T.; Kato, S.; Yoshida,
S., “GaN Power Transistors on Si Substrates for Switching
Applications,” Proceedings of the IEEE , vol.98, no.7, pp.1151,1161, July 2010
Funaki, T.; Matsushita, Masashi; Sasagawa, M.; Kimoto, T.; Hikihara, T., “A
Study on SiC Devices in Synchronous Rectification of DC-DC
Converter,” Applied Power Electronics Conference, APEC 2007 - Twenty Second
Annual IEEE , vol., no., pp.339,344, Feb. 25 2007-March 1 2007
Morita, T.; Tamura, S.; Anda, Y.; Ishida, M.; Uemoto, Y.; Ueda, T.; Tanaka, T.;
Ueda, D., “99.3% Efficiency of three-phase inverter for motor drive using GaNbased Gate Injection Transistors,” Applied Power Electronics Conference and
Exposition (APEC), 2011 Twenty-Sixth Annual IEEE , vol., no., pp.481,484, 611 March 2011
Ueda, D.; Hikita, M.; Nakazawa, S.; Nakazawa, K.; Ishida, H.; Yanagihara, M.;
Inoue, K.; Ueda, T.; Uemoto, Y.; Tanaka, T.; Egawa, T., “Present and future
prospects of gan-based power electronics,” Solid-State and Integrated-Circuit
Technology, 2008. ICSICT 2008. 9th International Conference on , vol., no.,
pp.1078,1081, 20-23 Oct. 2008
Tamura, S.; Anda, Y.; Ishida, M.; Uemoto, Y.; Ueda, T.; Tanaka, T.; Ueda, D.,
“Recent Advances in GaN Power Switching Devices,” Compound Semiconductor
Integrated Circuit Symposium (CSICS), 2010 IEEE , vol., no., pp.1,4, 3-6 Oct.
2010
Ishida, M.; Uemoto, Y.; Ueda, T.; Tanaka, T.; Ueda, D., “GaN power switching
devices,” Power Electronics Conference (IPEC), 2010 International , vol., no.,
pp.1014,1017, 21-24 June 2010
Lidow, A.; Strydom, J.; de Rooij, M.; Ma, Y., “GaN transistors for efficient
power conversion,” El Segundo, Ca, 2012.
Wu, Y.‐ F.; Coffie, R.; Fichtenbaum, N.; Dora, Y.; Suh, C.-S.; Shen, L.; Parikh,
P.; Mishra, U.K., “Total GaN solution to electrical power conversion,” Device
Research Conference (DRC), 2011 69th Annual , vol., no., pp.217,218, 20-22
June 2011
Morita, T.; Tamura, S.; Anda, Y.; Ishida, M.; Uemoto, Y.; Ueda, T.; Tanaka, T.;
Ueda, D., “99.3% Efficiency of three-phase inverter for motor drive using GaNbased Gate Injection Transistors,” Applied Power Electronics Conference and
132
[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
[43]
Exposition (APEC), 2011 Twenty-Sixth Annual IEEE , vol., no., pp.481,484, 611 March 2011
Wilhelm, C.; Kranzer, D.; Burger, B., “Development of a highly compact and
efficient solar inverter with Silicon Carbide transistors,” Integrated Power
Electronics Systems (CIPS), 2010 6th International Conference on , vol., no.,
pp.1,6, 16-18 March 2010
Wang, S.; Lee, F.C.; Odendaal, W.G., “Characterization and parasitic extraction
of EMI filters using scattering parameters,” Power Electronics, IEEE Transactions
on , vol.20, no.2, pp.502,510, March 2005
Wang, S.; Lee, F.C.; Van Wyk, J.D., “Design of Inductor Winding Capacitance
Cancellation for EMI Suppression,” Power Electronics, IEEE Transactions on ,
vol.21, no.6, pp.1825,1832, Nov. 2006
Chen, R.; Van Wyk, J.D.; Wang, S.; Odendaal, W.G., “Improving the
Characteristics of integrated EMI filters by embedded conductive Layers,” Power
Electronics, IEEE Transactions on , vol.20, no.3, pp.611,619, May 2005
Jiang, Y.; Wang, S.; Lee, F.C.; Van Wyk, J.D., “Equivalent parallel capacitance
cancellation for noise reduction application,” Applied Power Electronics
Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE , vol.,
no., pp.745,750, 24-28 Feb. 2008
Okada; Kazunari; Toshimasa; Sekino, “Impedance Measurement Handbook,”
Agilent Technologies 128 (2003): 5950-3000.
Scott, M.J.; Zou, K.; Wang, J.; Chen, C.; Su, M.; Chen, L.; , “A gallium-nitride
switched-capacitor circuit using synchronous rectification,” Energy Conversion
Congress and Exposition (ECCE), 2011 IEEE , vol., no., pp.2501-2505, 17-22
Sept. 2011.
Wang, S.; Kong, P.; Lee, F.C., “Common Mode Noise Reduction for Boost
Converters Using General Balance Technique,” Power Electronics, IEEE
Transactions on, vol.22, no.4, pp.1410-1416, July 2007.
Yeung, Y.P.B.; Cheng, K.W.E.; Ho, S.L.; Law, K.K.; Sutanto, D.;, “Unified
analysis of switched-capacitor resonant converters,” Industrial Electronics, IEEE
Transactions on , vol.51, no.4, pp. 864- 873, Aug. 2004.
Nave, M.J., “Power line filter design for switched-mode power supplies,: New
York: Van Nostrand Reinhold, 1991.
Wang, S.; Maillet, Y.Y.; Wang, F.; Lai, R.; Luo, F.; Boroyevich, D., “Parasitic
Effects of Grounding Paths on Common-Mode EMI Filter's Performance in
Power Electronics Systems,” Industrial Electronics, IEEE Transactions on ,
vol.57, no.9, pp.3050,3059, Sept. 2010
133