2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 – 9 December 2010, Kuala Lumpur, Malaysia
A 600MHz, 6th Order, Highly Linear Gm-C
Bandpass Filter Design
Saumen Mondal#1, Kumar Vaibhav Srivastava#2, A.Biswas#3
#
Department Of Electrical Engineering, Indian Institute of Technology, Kanpur, India
1
saumen.iitk@gmail.com
2
kvs@iitk.ac.in
3
abiswas@iitk.ac.in
Abstract— A highly linear 600 MHz centre frequency, 500 MHz
bandwidth 6th order Butterworth bandpass filter using a LeapFrog Gm-C topology is designed. Fully differential inverter
based Operational Transconductance Amplifier (OTA) with
common-mode feedback (CMFB) and common-mode feed
forward (CMFF) circuit is used in the design. Cadence tool has
been used on IHP SiGe BiCMOS 0.25 µm node. The filter
consumes power of 44.87 mW.
Keywords— ACTIVE-RC Filter, MOSFET-C Filter, OTA
I. INTRODUCTION
The continuous-time filters have been widely used in
various high speed applications, such as wireline and wireless
communications, digital video, RF/IF filter etc. High Q
bandpass filter are an integral part of the traditional RF
transceiver design. However, with the advancement of highly
integrated transceivers, architectures have been developed
which relaxes the essentiality of high Q filters. The Gm-C
topology with simplicity, modularity, open loop configuration,
and electronic tunability would be the obvious choice for high
frequency filter design over ACTIVE-RC and MOSFET-C
filter topologies [1].
The integrator is the main building block in the Gm-C filter
topology which can be realized by a transconductor element
loaded with a capacitor. The main function of the
transconductor is to convert the input voltage into the output
current maintaining accuracy and linearity at the same time.
Filter performance is dominated by the non-idealities of the
transconductor. The parasitic capacitors produce the deviation
of 3dB cutoff frequency of low-pass filters, the finite output
impedance affects the quality factor, and the voltage-tocurrent conversion affects the filter linearity. Although there
are a lot of work done earlier, but those highly linear circuits
are difficult to be used when high speed is required. One of
the major problems in high-frequency active filters is the
phase error of the integrators [2]. The quality factor Q of the
poles and zeros in the filter are highly sensitive to the phase of
the integrators at the pole and zero frequencies. To avoid
errors in the filter characteristics, a sufficiently high integrator
dc gain is required, while the parasitic poles should be located
at frequencies much higher than the cutoff frequency of the
filter, in order to keep the integrator phase close to -90⁰ [2].
Design techniques using negative resistance load to increase
the DC gain without any limitation in the bandwidth of the
transconductor circuit has been reported earlier [2]. This
results in an improved Gm-C integrator with theoretically
infinite dc gain and infinite bandwidth.
In this paper, first a transconductor circuit is described
(section II). Then, a sixth order leap-frog Gm-C filter with
CMFB and CMFF circuit design is demonstrated with the
simulated results (section III).
II. OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
In this section, first the voltage to current conversion of the
transconductor is described and then the common-mode
control system, DC-gain enhancement, and transconductor
tuning circuit are discussed.
A. The Voltage-to-Current Conversion
The class-AB transconductor circuit based on the well
known CMOS inverter is shown in Fig. 1. The V-I conversion
is done by the transistors M1 to M4, where the device
parameter of M1 is equal to M3 and M2 is equal to M4. These
transistors are operating in the saturation region with the
voltages Vi+ = Vcm + vd/2, and Vi- = Vcm - vd/2 (Vcm is the
input common-mode voltage and vd is the input differential
voltage). Considering the square law equation for the
saturated transistors, the transconductor of the circuit can be
given by the equation [3]

Gm  VDD  Vthn  Vthp

1,3  2,4
Fig. 1. The high speed transconductor circuit
(1)
2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 – 9 December 2010, Kuala Lumpur, Malaysia
where VDD is the supply voltage, Vthn is the threshold voltage
of the NMOS transistor, Vthp is the threshold voltage of the
PMOS transistor, and βi is the device parameter of transistor
Mi. Hence, the transconductance depends on the device
parameter, supply voltage, and threshold voltage. It should be
noted that when large device sizes are used, the
transconductor is linear even though β1,3 is not equal to β2,4.
It can be noticed that the simple V-I conversion achieved
by transistors M1 to M4 have no internal node. This is an
important criterion for the design of very high frequency
circuits and to avoid the effect caused by the parasitic
capacitances. Thus, the only parasitic capacitance existing in
the signal path is due to the transistor channel, and the pole
would locate at the tens of GHz range. If the length of the
MOS transistors is chosen to be minimum feature size under
nano-scale CMOS technology, the output drain current can be
modelled by
I D, sat 
 VGS  Vth 
2
2 1   VGS  Vth  
(2)
where θ is the mobility reduction coefficient. Assuming that
the β1,3 is equal to β2,4, we can define
Vov  Vcm  Vthn  VDD  Vcm  Vthp
Since in Gm-C topology the output nodes of one
transconductor would be the input node of the next
transconductor, hence it is necessary to fix the output common
mode voltage to the input common-mode voltage and thus the
linearity of the designed filter will be maintained. In the above
circuit the output common-mode voltage is maintained by an
adaptive CMFB circuit consisting of transistors MFB1 and
MFB2. Thus, the output common-mode information is
detected by the voltage, Vcnext, which is the Vc node of the
next transconductor stage. Then the signal produced by the
CMFF and CMFB circuit would be combined and the output
common-mode voltage is adjusted accordingly.
C. Gain-Enhancement and Transconductance Tuning Circuit
For the short-channel MOS transistor in high-frequency
application, the DC gain is normally very low (≈20). The
small feature size, chosen for small parasitic capacitances also
degrade the gain performance. With the use of negative
resistance the DC gain larger than 40 dB can be achieved. The
channel length modulation effect, which is a distortion
component contributed to the circuit, can also be minimized.
The negative resistance circuit for gain enhancement,
composed of transistor M15 to M18, is shown in Fig. 2. Note
that the implementation of DC gain enhancement of DC gain
enhancement technique does not require any internal node.
(3)
From the analysis of a Taylor series expansion, the third-order
harmonic distortion term would be the dominant component
of transconductor, and the HD3 is given by [4]
HD3 
2 vd2
vov  4  2 Vov (5  4 Vov   2Vov 2 ) 


(4)
From the above equation it is clear that the linearity can be
increased by applying a large overdrive voltage which can be
achieved by applying a large supply voltage or smaller
threshold voltage. Usually, Vcm is chosen equal to VDD/2. If
1,3   2,4 , and Vthn = -Vthp, then the output voltage
would be equal to half of the supply voltage and output
common-mode current would be zero [2].
B. The Common-Mode Control System
The transconductor behaves as a pseudo-differential
structure and hence it requires CMFF circuit to control the
effect caused by the variation in the input common-mode
signal. Transistor M9 and M14 have one half of the device
parameter of transistor M1, and transistor M10 and M13 have
one half of the device parameter of the transistor M2,
respectively. The variation in the input common-mode signal
is obtained by the transistors M9, M10, M13, M14 which is
then cancelled at the output nodes by transistors M11 and
M12.
Fig. 2. Negative output resistance circuit for gain enhancement
.
The absence of any internal node left us with the option of
supply voltage and bulk node for tuning purpose. In [2], the
transconductor was tuned by adjusting supply voltage. But
this tuning strategy degrades the linearity when a fixed
common-mode voltage is applied from the previous stage and
also increases the complexity of the regulator due to class ABoperation. Here, the tuning is achieved by adjusting both the
bulk voltage of PMOS and NMOS in the deep N-WELL
CMOS process. The bulk tuning circuit is shown in Fig. 3.
The voltages at node Vtn and Vtp would be adjusted to the
opposite value with the change in Vtune. The forward bias
scheme will increase the value of Vthn and decrease the value
of Vthp. This will increase the speed to higher value and also
decreases the variation of threshold voltage [4]. Hence the
short channel effect can be reduced and the linearity can also
be increased because of the large overdrive voltage.
The constraint of a 0.5 V forward bias in deep N-WELL
process needs to be maintained to keep the latch-up effect and
2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 – 9 December 2010, Kuala Lumpur, Malaysia
the leakage current under control. The device aspect ratio of
the MT7 and MT8 are given by the following constraint
 p  0.5  Vthn
W 


 
 L MT 7 n  VDD  Vthp

  0.5  Vthp
W 
 n
 
 L  MT 8  p  VDD  Vthn

circuit. The response is shown in Fig. 4. The total power
consumed by the transconductor is 3.162 mW.
2
 W
  
  L MT 4

2
 W
  
  L MT 5

TABLE I
TRANSIATOR SIZES
(5)
(6)
where µn and µp are the low-field mobilities of NMOS and
PMOS transistors. The transistors MT7 and MT8 would
Fig. 3. Transconductance tuning circuit
operate in the weak inversion region when a smaller forward
bias voltage is applied. Also, the value of negative resistance
for the gain enhancement can be tuned separately by applying
another bulk tuning circuitry, and thus Q tuning can also be
achieved.
Device
M1,M3
M4,M2
M5,M7
M6,M8
M9,M14
M13,M10
M11
M12
MFB1
MFB2
M18,M16
M17,M15
Width(µm)
6
22.4
50
75.8
3
11.2
12.9
10.2
4
6.9
5.8
3.3
III. FILTER DESIGN
A sixth order leap-frog filter has been realized using the
transconductor of the Fig 1. The filter is derived from the
passive LC ladder filter. The passive ladder filter is given in
Fig. 5.(a). Active implementation is shown in Fig. 5.(b). The
circuit can be divided into capacitively-loaded gyrator (Gm
3,4,7,8,11,12), and inter-resonator “coupling OTAs (Gm
5,6,9,10). The remaining OTAs form the terminating
resistances (Gm2, Gm14), and gain-setting input and output
buffers for the filter (Gm1, Gm13) [5].
D. Simulated Results
The circuit is designed and simulated using Cadence tool on
IHP SiGe BiCMOS 0.25 µm node. All the transistors have
channel length of 0.24 µm. The widths (µm) of the transistors
are given in Table I. The supply voltage is 1.5 V.
(a)
Fig. 4. Frequency response of the transconductor
For the designed transconductor gain of 43 dB, the phase
margin of 86⁰ is achieved by tuning the gain enhancement
(b)
Fig. 5. (a) Ladder filter prototype, (b) Gm-C filter schematic
2010 Asia Pacific Conference on Circuits and Systems (APCCAS 2010)
6 – 9 December 2010, Kuala Lumpur, Malaysia
To achieve a high cutoff frequency, the filter operates
mainly on parasitic capacitances. This is possible since the
parasitic capacitances are all at nodes where a capacitance is
desired in the filter. Fig. 6. shows the frequency response of
the filter. The response is centred around 600 MHz with 3 dB
bandwidth ranging from 400 MHz to 900 MHz. The values
are summarized below in Table II.
Figure. 7. shows the -40 dB of IM3 at filter centre
frequency with -25 dB two tone signals of 600 MHz and 620
MHz
IV. CONCLUSIONS
A very high frequency wideband bandpass filter is designed
using SiGe BiCMOS technology. To achieve a high cutoff
frequency, the filter operates mainly on parasitic capacitances.
The bandpass filter has centre frequency of 600 MHz, 3 dB
bandwidth of 500 MHz. The IIP3 of this filter is -5.3731 dBm
which shows its highly linear characteristics. The filter
consumes power of 44.87 mW. The noise characteristic of the
filter is also very good.
ACKNOWLEDGMENT
Authors would like to acknowledge Prof.S.Qureshi for
providing access to the tools and IHP microelectronics,
Germany for providing process design kit.
REFERENCES
[1]
Fig. 6. The measured frequency response of the filter
[2]
[3]
[4]
[5]
Fig. 7. Two tone inter-modulation of the filter
TABLE II
SUMMARY OF FILTER SIMULATION RESULTS
Parameters
Simulated Results
Technology
0.25 µm BiCMOS
Filter Order
6
Centre Frequency
600 MHz
3dB Bandwidth
500 MHz
IM3/HD3
-40 dB
IIP3
-5.3731 dBm
Supply
1.5 V
Power Consumption
44.87 mW
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H. Khorramabadi and P. R. Gray, “High-Frequency CMOS
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Feb.1992
Tien-Yu-Lo, and Chung-Chih Hung, “1V Gm-C Filters: Design and
Application, Springer Science, 2009.
James Moritz and Yichuang Sun, “100MHz,6th Order, Leap-Frog GmC High Q Bandpass Filter and On-Chip Tuning Scheme,” ISCAS 2006.