30th Year
1986-2016
ADVANCE PROGRAM
2016 IEEE BIPOLAR / BiCMOS
CIRCUITS AND
TECHNOLOGY MEETING
http://ieee-bctm.org/
Hyatt Regency
New Brunswick, NJ, USA
SEPTEMBER 25 - SEPTEMBER 27, 2016
SHORT COURSE —SEPTEMBER 25, 2016
SPONSORED BY
THE ELECTRON DEVICES SOCIETY OF
THE INSTITUTE OF ELECTRICAL AND
ELECTRONIC ENGINEERS
IN COOPERATION WITH
THE IEEE SOLID-STATE CIRCUITS
SOCIETY
THE IEEE MICROWAVE THEORY &
TECHNIQUES SOCIETY
30th Year
1986-2016
2016 BCTM SCHEDULE AT A GLANCE
Sunday — September 25
Registration opens at 7:30 AM
nd
2 Floor - Conference Center
8:30AM
—
5:40PM
SHORT COURSE – Sunday, September 25
Advances in Design Enablement for RF and High Performance
Analog Circuit Design
2nd Floor – Conference Room # BC
Lunch: Conference Room # A
Conference Room # F – Attendee Lounge Opens at 8:30 am
Monday — September 26
Registration opens at 7:30 AM
Pre-Function – Brunswick Ballroom
*Conference Room # F – Attendee Lounge Opens at 8:00 am
8:00AM
Welcome and Announcements
Brunswick Ballroom
8:30AM
—
9:30AM
Keynote speaker : Peter Kinget (Columbia University)
RF Circuit and System Innovations to Enable a New Generation of
Wireless Terminals: Field programmability, Ultra-high Linearity, and
Compressive Spectrum Scanning
Brunswick Ballroom
9:30AM
Coffee Break
Brunswick Ballroom
9:45AM
—
11:25PM
1. Circuits for Optical
Communications
Brunswick Ballroom
11:25AM
—
12:40PM
12:40PM
—
3:00PM
Conference Room # BC
Lunch Break
(Self-Arrangement)
3.
Emerging Technologies & BCTM Historical Talk
by Paul Davis/John Shirer
Brunswick Ballroom
3:00AM
3:15PM
—
4:55PM
2. Device Physics
Coffee Break
4. Circuit Techniques for
Transmitters
Brunswick Ballroom
5. State of the Art SiGe
Technology
Conference Room # BC
4:55PM
Break
5:45 PM
Dinner Cruise - New York City: Buses will depart from the
Hyatt lobby at 5:45 pm. The cruise will run from 7 pm to 10 pm.
Attendees will return back to the Hyatt around 10:45 pm - 11 pm.
Tuesday — September 27
Registration opens at 8:00 AM
Brunswick Ballroom – Pre-Function Area
8:30AM
—
9:30AM
Keynote speaker : James C. Sturm (Princeton University)
Large-area flexible hybrid electronics: the hardware platform for the
Internet of things
Brunswick Ballroom
9:30AM
9:50AM
—
11:30AM
11:30AM
—
12:50PM
12:50PM
—
2:30PM
2:30
2:50PM
—
4:55PM
Coffee Break
6. Analog Circuits
Brunswick Ballroom
7. Linking Devices, Circuits,
and Systems
Conference Room # BC
Lunch Break
Brunswick Ballroom
8. Advanced Wireless Building
Blocks
Brunswick Ballroom
9. Process Potpourri
Conference Room # BC
Coffee Break
10. Bipolar Transistor Compact
Modeling
Brunswick Ballroom
11. Millimeter-wave
Transmitters and Receivers
Conference Room # BC
END OF BCTM 2016 --- Thank You for Attending!
Visit us at: http://www.ieee-bctm.org
30th Year
1986-2016
Welcome from the BCTM 2016 Chairmen
Welcome to beautiful New Brunswick, NJ! On behalf of the IEEE
BCTM 2016 Executive Committee, we are honored and delighted to
present the 2016 IEEE Bipolar/BiCMOS Circuits and Technology
Meeting (BCTM). Conference highlights feature:
- Keynote addresses from world-renowned speakers. The 1st, by
Peter Kinget of Columbia University, on “RF Circuit and System
Innovations to Enable a New Generation of Wireless Terminals:
Field programmability, Ultra-high Linearity, and Compressive
Spectrum Scanning”. The 2nd keynote is by James C. Sturm of
Princeton University on “Large-area flexible hybrid electronics: the
hardware platform for the Internet of things”
- Full-day short course: “Advances in Design Enablement for RF and
High Performance Analog Circuit Design”, where Dr. Sharad Kapur
from Integrand Software discusses Advanced EM Simulation"; Art
Schaldenbrand of Cadence on “Developments in EDA tools for
analog design”; Dr. Ali Niknejad of University of California Berkeley
on “Modeling of Passives at High Frequencies”, and Dr. Shahriar
Shahramian of Bell Labs on “Circuit design point of view on EM
Simulation, EDA tools, and modeling”
- Forward-looking Emerging Technologies Session with two invited
speakers: Prof. Eli Yablonovitch (University of California Berkeley)
on Energy efficient electronics" and Steven Kovacic (Skyworks) on
“5G Front-End Component Challenges”
- Invited papers exploring advances in analog and wireless design,
device physics, modeling and simulation, process technology.
- Technical papers covering the latest advances in physics, design,
performance, fabrication, characterization, modeling, and application
of Si/SiGe/SiGe:C bipolar, and BiCMOS ICs
- A fabulous evening dinner banquet
The IEEE BCTM is the world’s premier forum focused on the needs
and interests of the bipolar and BiCMOS community. If you are
interested in leading edge bipolar/BiCMOS devices and technology,
circuits, and applications, as well as networking with experts in these
areas, please kindly join us this year in historic New Brunswick, NJ,
USA!
Doug Weiser
General Chair
Texas Instruments
Foster Dai
Technical Program Chair
Auburn University
30th Year
1986-2016
BCTM 2016 REGISTRATION
Register at: http://ieee-bctm.org
Advance registration deadline is August 12 (Friday),
2016.
Group Registration rates are available for Companies and
Organizations sending 5 or more participants to BCTM 2016.
Please contact cshaw.cmpevents@gmail.com for more details
Conference Registration Cost in US Dollars (includes digest &
banquet for regular registration and digest only for students):
ADVANCE
AFTER
(8/12/2016)
(By 8/12/2016)
IEEE Members $675
$775
Non-Members $775
$875
Students
$500
$600
(2) Guest Fee for Dinner Banquet
$115/person
$125/person
(3) Extra 2016 Proceedings (electronic version on USB drive):
Members $50
Non-members $75
Registration Fees: SHORT COURSE
(1) COURSE COST:
MEMBERS/NON-MEMBERS
$400
STUDENTS
$300
(2) SHORT COURSE NOTES
(included with Short Course registration)
Short Course Notes only
$150
All fees are denominated in US$
Full Registration Includes: USB, continental breakfast, all
day refreshments, and banquet cruise to New York.
*Note: lunch is on your own. Additional information will be
provided onsite.
Short course registration includes: course notes/USB,
continental breakfast, short course Lunch, refreshments
Refund Policy:
All requests for refund/cancellation must be received in writing
at least 10 days prior to the conference start date for a full
refund on September 12. Any request thereafter will not be
entitled to a refund. Cancellations will incur a US $50
administration fee. Please submit cancellation requests via
email to cshaw.cmpevents@gmail.com
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HOTEL RESERVATIONS
A block of rooms has been reserved at special discounted rates for
BCTM conference participants at our headquarters hotel, the
HYATT REGENCY NEW BRUNSWICK
2 Albany Street
New Brunswick, NJ 08901, USA
T: + 1.732.867.2258
Website: newbrunswick.hyatt.com
Reservations:
https://resweb.passkey.com/Resweb.do?mode=welcome_ei_new&eve
ntID=14533191
This year’s hotel rates for BCTM 2016 are very reasonable at $179.00
USD per night. As always, attendees are strongly encouraged to
reserve their room at BCTM’s host hotel. *New Brunswick, New
Jersey, is located approximately 45 minutes from New York City via
train and car. Please note that the rate above has also been extended
to BCTM attendees who would like to extend their stays 3 days prior/3
days after BCTM concludes.
*Additional details in regard to optional trips into New York City prior to
BCTM will also be available in the near future.
While there are alternatives, we would like to remind attendees to
please support the Symposium and fully enjoy all the activities by
staying at the official headquarters hotel. The Symposium relies on
attendees staying at the conference Hotel to reduce the costs charged
for the use of meeting rooms. Room reservations should be made as
soon as possible, as there are a limited number available at the
symposium rate. To qualify for the discounted rate reservations
must be made by August 25. Rooms are available at the special
Symposium group rate of US $179 plus tax (15.75%) per night. Rates
are for single occupancy. An extra person charge per person may
apply for 2 or more guests sharing the same guestroom.
If you wish to cancel, please do so 24 hours before arrival to avoid
cancellation penalties.
TRAVEL ARRANGEMENTS
Travel arrangements using the IEEE negotiated air carriers or the
carriers of your choice can be made through World Travel, Inc. by
calling between the hours of 8:00 a.m. and 5:30 p.m. EST Monday
through Friday. Within the US and Canada, call (800) TRY-IEEE, (+1
800 879 4333); and outside of the US and Canada, call +1 717 556
1100. Or, you may visit their on-line travel service web site at
http://www.ieee.org/travel. This secure site offers simple and
convenient service through which you can search, reserve, and ticket
your travel anytime, anywhere. Or you can e-mail your request to
30th Year
1986-2016
ieee@worldtravelinc.com.
IEEE corporate car rental discounts are also available to all attendees
of the symposium. Discount codes below entitle attendees to receive
special rates that have also been negotiated with Avis A606000,
Budget X520000, Hertz 61368, and Enterprise NA24IE1.
Transportation
Hyatt Regency New Brunswick is easily accessed by a variety of public
transportation modes. Please consult the list below for the most
convenient conveyance to our hotel.
To and from Newark Airport:
 Taxi: #1 recommended: Taxi: $65. Tolls included, gratuity is
additional.
 AAA Car Service: 888 777 3055. Fee is $75 one-way, inclusive
of tolls and gratuities.
 Lift and Uber are also alternate options.
 New Jersey Transit (NJ Transit): The New Brunswick train
station is located 2 blocks from the hotel. One-way cost from
this train station to the Newark International Airport via NJ
Transit is $14.50 per person. *Note: you must adhere to
transit schedule to arrive. Train schedules can be found at
http://www.njtransit.com/ .
To New York City:
New Jersey Transit: New Jersey transit located 2 blocks from the hotel;
runs approximately every hour. One-way trip to New York Penn Station
is $13.00 per person.
AAA Car Service: Contact 888 777 3055 for additional information.
Group rates are available.
*Local Shuttle Service: PLEASE REFER TO THE BCTM WEBSITE
FOR DIRECT URL Link to CONTACT ’S AND ADDITIONAL
INFORMATION.
Shuttle service: The Hyatt Regency New Brunswick is proud to provide
complimentary shuttle service within a 5 mile radius of the hotel.
Monday through Friday: 7:00 AM – 7:00 PM
Reservations required, please contact the Front Desk for more
information.
30th Year
1986-2016
ADDITIONAL INFORMATION
CONFERENCE BANQUET: Monday, September 26, 2016:
Hornblower Cruises & Events - New York. Attendees will pass the
Statue of Liberty, Brooklyn and New York Skylines. Dinner will be
served. Attendees will depart from the Hyatt lobby at 5:45 pm. The
cruise will run from 7 pm to 10 pm.
ADMISSION All interested persons are welcome to register and attend
the BCTM; you do not have to be an IEEE member. Admission to
sessions requires a BCTM badge. Please wear your badge at all times.
REGISTRATION Complete registration information is contained in the
centerfold of this booklet as well as on the conference’s web page
(http://ieee-bctm.org). Please use the website to register. The
advanced registration deadline is August 12, 2016. All conference
activities are included in the registration fees (technical sessions, food
breaks and the banquet) as well as a USB flash drive with an
electronic copy of BCTM 2016 Proceedings.
OTHER CONFERENCE SOCIAL EVENTS Several events have been
arranged to promote informal social interactions among conference
participants.
TUTORIAL / SURVEY TALKS Tutorial talks given by invited experts
are intended to give a broad overview of a given subject with a critical
review of technology and applications. They are twice the length of the
usual contributed talk with longer abstracts in the Proceedings.
MEMBERS OF THE PRESS are welcome to attend BCTM. Admission
is free. Just present your business card at the registration desk.
RECRUITING Intensive recruiting undermines the purposes for which
the BCTM was established, and is contrary to IEEE policy.
BEST STUDENT PAPER AND BEST PAPER AWARDS BCTM offers
a Best Paper Award. The BCTM Best Paper Award recognizes and
promotes high quality contributions to scholarly research among
professionals who author and present papers at the conference. All
papers submitted in non-student category are eligible for consideration
for the Best Paper Award.
The BCTM Best Student Paper Award recognizes and promotes
outstanding research led by students. To be eligible for consideration
for the Best Student Paper Award, the following criteria have to be met:
1) the student must have carried out a substantial part of the research
reported in the paper, 2) the student must be the first author and must
present the paper at the conference, 3) the paper must be identified as
a student paper during submission of the paper; and 4) the paper
identified as a student paper in submission, but not presented by the
student will be disqualified for Best Student Paper Award competition.
In this scenario, the paper will be moved to non-student category for
Best Paper Award competition automatically.
Eligible papers are evaluated by the Best Paper Award Committee and
the notifications will be sent out after the conference. The winners of
the awards will be recognized with a $500 check and a plaque at next
year's BCTM conference.
FURTHER INFORMATION BCTM is sponsored by the IEEE Electron
Devices Society (EDS) in co-operation with the IEEE Solid-State
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1986-2016
Circuits Society (SSCS) and the IEEE Microwave Theory &
Techniques Society (MTT).
BCTM 2016 Short Course and Schedule
Conference Room # BC
Advances in Design Enablement for RF and
High Performance Analog Circuit Design
Date: Sunday, September 25, 2016
Time: 8:30am - 5:40pm
Location: Conference Room #BC
Session Chair: Edward Preisler (TowerJazz)
Co-Chair: Wibo van Noort (Texas Instruments)
7:30 - 8:30 AM Registration and breakfast
8:30 - 8:35 AM Welcome
Edward Preisler and Wibo van Noort
Course Overview
Design and simulation of RF/HPA circuits require a unique set of
complex design enablement tools not typically needed for digital or
mixed signal designs. As RF/HPA designs move to higher frequencies
and dynamic range the importance of these tools grows, and in many
cases brand new tools are required to adequately simulate circuit
behavior. The full design flow for such products might cover every
possible design enablement tool: advanced circuit simulation engines,
parasitic extraction tools, EM simulators, thermal simulators, and
others. Further, while compact modeling of active devices is clearly
vital, the importance of modeling of passives is amplified for RF/HPA
design. In this course, four presentations are offered that cover topics
addressing new innovations and developments for RF/HPA design
enablement. The presentations will be given by experts from EDA tool
vendors and academia and an advanced user of these tools. The goal
of the entire course is to inform attendees of the latest developments
across all design enablement disciplines that will aid in the next
generation of demanding RF/HPA circuit designs.
8:35 - 10:25 AM
Analog IC Design Methodology and Automation to
Address Emerging Design Challenges
Instructor: Art Schaldenbrand (Cadence Design Systems)
In this short course we will explore how evolving end market
requirements are changing IC design. We will start by looking at
market and technology trends and translate those trends into design
challenges. Then we will consider the changes in design methodology
required to address these challenges. Finally, we will explore how the
methodology can be automated to improve designer productivity and
the increasingly complex relationship between the analog designer, the
foundry, and the EDA tool provider. One example we will consider is
that to maintain or accelerate design turn-around time in spite of
increased process variation, the effect of process variation needs to be
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considered during design. This is achieved by identifying the worst
case conditions at the start of design and using them during design.
Identifying these worst case conditions requires advances in design
automation. We will close by considering some of the challenges
facing analog IC designers today.
Art Schaldenbrand is the Product Manager of Spectre Circuit
Simulator. Art has over 35 years of EDA and analog design
experience. He joined Cadence Design Systems, Japan in 1996 as
field application engineer supporting custom IC design tools. Prior to
Cadence, Art worked at Westinghouse Electric and Harris
Semiconductor as an analog IC designer. He graduated with a BS in
Electrical Engineering from Michigan State University
10:25 - 10:45 AM Break
10:45 AM - 12:35 PM
Modeling and synthesis of passive components for
RFICs
Instructor: Sharad Kapur (Integrand Software)
We describe the use of an electromagnetic simulator for modeling
integrated RF components and circuits. These simulators are fast and
accurate enough to provide excellent models of such components. We
describe how they can handle features of advanced IC processes
where the physical properties of wires (width, thickness, and
resistance) vary depending on the surrounding wiring. Because the
simulator handles mask-ready layout without the need for manual
simplification, it is feasible to simulate thousands of possible designs
and build scalable parameterized component models. Such scalable
models allow for fast choices of optimal components such as inductors,
transformers, baluns, t-coils and MOM capacitors and have become a
standard part of a foundry design kit.
Sharad Kapur is the president and co-founder of Integrand Software,
Inc. He graduated with a Ph.D. in Computer Science (Numerical
Analysis) from Yale University in 1996. He joined Bell Labs in 1996 as
a member of technical staff. While at the design automation group at
Bell Labs he co-developed several large software packages and tools,
for electromagnetic analysis, circuit simulation and chip-level
extraction. In 2003 he co-founded Integrand Software, Inc and helped
develop the EMX 3D EM simulator. He is the author of over 30 peerreviewed publications, primarily in the area of numerical analysis and
electronic design automation. He is the holder of 6 US patents.
12:35 - 13:30 PM Lunch
1:30 - 3:20 PM
Needle in a haystack – How to Find Hidden
Parasitics in mm-Wave Layouts
Instructor: Shahriar Shahramian (Nokia-Bell Labs)
This short course explores the hidden impairments which are often
overlooked or difficult to locate in mm-Wave layouts and interconnects.
Using real-life fabricated circuit blocks operating in the W-Band and
optical circuits operating beyond 100Gb/s you are invited to search for
parasitic capacitive, inductive and resistive elements which can
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adversely affect the circuit performance. After modeling of these
elements, simulations demonstrate the impact of the parasitics on
bandwidth, center frequency, stability and noise-figure. Using simple
and quick modeling techniques the designers can incorporate various
layout effects into their design.
Shahriar Shahramian (M ’06) received his Ph.D. degree from
University of Toronto in 2010 where he focused on the design of mmwave data converters and transceivers. Dr. Shahramian has been with
the Bell Laboratories division of Alcatel-Lucent (now Nokia), Murray
Hill, NJ since 2009 and is currently the Director of the mm-Wave ASIC
Research Department. He is also a member of the technical program
committee of Compound Semiconductor Integrated Circuit
Symposium. His research focus includes the design of mm-wave
wireless and wireline integrated circuits. He is the lead designer of
several state-of-the-art ASICs for optical coherent and wireless
backhaul product development at Bell Laboratories. Dr. Shahramian
has been the recipient of Ontario Graduate Scholarship, University of
Toronto Fellowship and the best paper award at the CSIC Symposium
in 2005 and RFIC Symposium in 2015. He has also held an adjunct
associate professor position at Columbia University, has received
several teaching awards and is the founder and host of The Signal
Path educational video series.
3:20 - 3:40 PM Break
3:40 - 5:30 PM
Passive Devices for Communication Integrated
Circuits
Instructor: Ali Niknejad (UC Berkeley)
This short course will review the fundamentals of co-design of high
performance circuits with passive components, such as inductors,
transformers, and transmission lines. Topics will cover passive device
analysis and simulation, layout, and circuit design trade-offs such as
loss and bandwidth. The focus will be integrated silicon passive
devices from RF to mm-wave frequencies. Parasitic electromagnetic
coupling in a chip environment, including through bond-wires and
package, will be discussed. Isolation techniques will be reviewed. The
final part of the lecture will cover high frequency design techniques
with transmission lines, including matching circuits and resonator
design.
Ali M. Niknejad received the Ph.D. degree in electrical engineering
from the University of California, Berkeley 2000, where he is currently
a professor and faculty director of the Berkeley Wireless Research
Center (BWRC). Prof. Niknejad is an IEEE Fellow, the recipient of the
2012 ASEE Frederick Emmons Terman Award for his textbook on
electromagnetics and RF integrated circuits. He was the co-recipient
of the IEEE International Solid-State Circuits Conference (ISSCC)
2013 and 2010 Jack Kilby Awards for Outstanding Student Papers,
and the co-recipient of the Outstanding Technology Directions Paper at
ISSCC 2004 for co-developing a modeling approach for devices up to
65 GHz. He is a co-founder of HMicro and the inventor of the
REACH(™) technology, which has the potential to deliver robust
wireless solutions to the healthcare industry. His general research
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interests lie within the area of wireless communications and biomedical
sensors and imaging.
5:30 - 5:40 PM Course Evaluation
INTRODUCTORY REMARKS AND KEYNOTE
WELCOME AND ANNOUNCEMENTS
8:00–8:30 AM — Brunswick Ballroom
KEYNOTE SPEECH
8:30–9:30 AM — Brunswick Ballroom
“RF Circuit and System Innovations to Enable a
New Generation of Wireless Terminals: Field
programmability, Ultra-high Linearity, and
Compressive Spectrum Scanning”
Peter Kinget (Columbia University)
Wireless communications have become an essential part of every
sector of the national and global economy. Both existing cellular, WiFi
and GPS systems and new emerging systems like video over wireless,
the Internet of Things and machine-to-machine communications are
projected to increase the mobile wireless data traffic by orders of
magnitude in the coming decades. This is resulting in a growing
spectrum deficit given that the radio spectrum is a finite resource.
Cognitive radio is a proposed paradigm shift to opportunistically use
the available spectrum for improved spectral usage efficiency. Several
key circuit innovations are required to make the realization of this
vision possible. Future “smart” terminals will need to quickly assess the
spectrum usage and require power-efficient spectrum scanning
capabilities. They further need to receive at multiple frequencies using
a variety of standards. This leads to very stringent receiver linearity
and blocking requirements given the absence of high quality front-end
tunable filters. Designing for worst-case RF scenarios further leads to
excessive power consumption in the terminals, and dynamically
adapting the RF performance in the field to the RF spectrum conditions
is emerging as a required receiver feature.
Peter R. Kinget received the engineering and Ph.D. degrees in
electrical engineering from the Katholieke Universiteit Leuven,
Belgium, in 1990 and 1996, respectively. From 1996 to 1999 he was a
Member of Technical Staff at Bell Laboratories, Murray Hill, NJ. From
1999 to 2002 he held various technical and management positions in
IC design and development at Broadcom, CeLight and MultiLink. He
joined the faculty of the Department of Electrical Engineering,
Columbia University, NY in 2002 where he currently serves as a
Professor. He is also a consulting expert on patent litigation and a
technical consultant to industry. His research interests are in analog,
RF and power integrated circuits and the applications they enable in
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communications, sensing, and power management. He is widely
published in journals and conferences, has co-authored 3 books and
holds 17 US patents. Dr. Kinget is a Fellow of the IEEE. He has been
an Associate Editor of the IEEE Journal of Solid State Circuits and the
IEEE Transactions on Circuits and Systems II. He has served on the
Technical Program Committees of the IEEE Custom Integrated Circuits
Conference, the Symposium on VLSI Circuits, the European SolidState Circuits Conference, and the International Solid-State Circuits
Conference. He currently is a "Distinguished Lecturer" for the IEEE
Solid-State Circuits Society, a member of the Board of the Armstrong
Memorial Research Foundation and an elected member of the IEEE
Solid-State Circuits Society Adcom. He is a co-recipient of the "Best
Student Paper Award - 1st Place" at the 2008 IEEE Radio Frequency
Integrated Circuits (RFIC) Symposium; of the "First Prize" in the 2009
Vodafone Americas Foundation Wireless Innovation Challenge; of the
"Best Student Demo Award" at the 2011 ACM Conference on
Embedded Networked Sensor Systems (ACM SenSys); of the "2011
IEEE Communications Society Award for Advances in Communication"
for an outstanding paper in any IEEE Communications Society
publication in the past 15 years; of the "First Prize ($100K)" in the 2012
Interdigital Innovation Challenge (I2C); and of the “Best Student Paper
Award – 2nd Place” at the 2015 IEEE Radio Frequency Integrated
Circuits (RFIC) Symposium.
SYMPOSIUM PROGRAM
1. Circuits for Optical Communications
Monday 9:45 AM — Brunswick Ballroom
Session Chair: Michael Moeller
Co-Chair: Christoph Scheytt
(1.1) 9:45–10:35 AM – SiGe BiCMOS Technologies
for High-speed and High-volume Optical
Interconnect Applications
Thé Linh Nguyen
In this paper we will discuss the challenges of circuit design for highspeed and high-volume optical interconnect and how SiGe BiCMOS
technologies can help. Advantages of SiGe BiCMOS are illustrated
through examples of design requirements from optical front-ends (TIA
and modulator and laser driver) to clock and data recovery and
SerDes. We will also look ahead to the future and predict the product
evolution and key requirements of optical interconnects and
performance of SiGe BiCMOS technology required to address such
specifications.
(1.2) 10:35–11:00 AM – A 50 Gb/s TIA in 0.25μm
SiGe:C BiCMOS in Folded Cascode Architecture
with pnp HBTs (Student)
I. García López, P. Rito, A. Awny, B. Heinemann, D. Kissinger,
and A. C. Ulusoy
This paper presents the design and electrical characterization of a
transimpedance amplifier (TIA) implemented in a complementary 0.25
μm SiGe:C BiCMOS technology which offers a fT/fmax of 110 GHz/180
GHz for the npn and 95 GHz/140 GHz for the pnp transistor,
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respectively. Featuring folded cascode architecture by means of the
available pnp HBTs, the amplifier exhibits a differential transimpedance
gain of 52.5 dBΩ and a 3 dB bandwidth of 32 GHz with a measured
differential average input referred current noise density of 13.1 pA/√Hz,
while dissipating 70 mW of power. Clear eye diagrams up to 50 Gb/s
data rate are reported. To the best of the authors’ knowledge, this is
the first time pnp transistors are used at such speed, achieving an
overall performance comparable to, or better than, other TIA
implementations in faster technologies.
(1.3) 11:00–11:25 AM – The Effect of Strong
Equalization in High-Speed VCSEL-Based Optical
Communications up to 48 Gbit/s (Student)
Guido Belfiore, Ronny Henker and Frank Ellinger
In this paper the design of a VCSEL driver with strong equalization is
presented. Unlike other published works the pre-emphasis provided
from the proposed driver and the output voltage swing are
independently tunable up to the saturation of the output stage (~700
mVpp in 50  load environment). The driver is designed in 130 nm
SiGe BiCMOS technology. Thanks to the various bandwidth extension
techniques, the electrical data rate at which the driver can operate is
higher than 50 Gbit/s. A wide open optical eye diagram is measured at
48 Gbit/s with a 20 GHz VCSEL. The driver and the VCSEL consume
only 188 mW from a dual voltage supply of 2.5 and 3.4 V. To the best
of the authors knowledge 3.9 mW/(Gbit/s) is the highest reported
energy-efficiency for a common-cathode VCSEL driver with data-rate
higher than 40 Gbit/s. Moreover an open eye at 48 Gbit/s is the fastest
reported for a common cathode VCSEL driver without pre-emphasis in
the receiver.
2. Device Physics
Monday 9:45 AM — Conference Room # BC
Session Chair: Vibhor Jain
Co-Chair: Guanghai Ding
(2.1) 9:45–10:10 AM – Modeling of High-Current
Damage in SiGe HBTs under Pulsed Stress (Student)
Uppili S. Raghunathan, Brian Wier, Rafael Perez Martinez,
Zachary E. Fleetwood, Anup Omprakash, Hanbin Ying, Saeed
Zeinolabedinzadeh, and John D. Cressler
High-current pulsed stress measurements are performed on SiGe
HBTs to characterize the damage behavior and create a
comprehensive physics-based TCAD damage model for Augerinduced hot-carrier damage. The Auger hot-carrier generation is
decoupled from classical mixed-mode damage and annealing on the
output plane by using pulsed stress conditions to modulate the selfheating within the device under stress. The physics of high-current
degradation is analyzed, and a temperature dependent degradation
model is presented. This model is the first of its kind in both the CMOS
and bipolar communities and solves a significant portion of the puzzle
for predictive modeling of SiGe HBT safe-operating-area (SOA) and
reliability.
(2.2) 10:10–10:35 AM – On the Use of Vertical
Superjunction Collectors for Enhanced Breakdown
Performance in SiGe HBTs (Student)
30th Year
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Brian R. Wier, Uppili S. Raghunathan, Zachary E. Fleetwood,
Michael A. Oakley, Alvin J. Joseph, Vibhor Jain, and John D.
Cressler
The implementation of a “superjunction” collector design in a silicongermanium heterojunction bipolar transistor is explored for enhancing
breakdown performance. The superjunction collector is formed through
the placement of a series of alternating pn-junction layers in the
collector-base space charge region in order to modify the carrier
energy profile and reduce avalanche generation. An overview of the
physics underlying superjunction collector operation is presented with
TCAD simulations, and practical superjunction design techniques are
discussed. The first measured data on a superjunction collector is also
presented and shows a pronounced improvement in breakdown
performance.
(2.3) 10:35–11:00 AM – Investigation of DoubleEmitter Reduced-Surface-Field Horizontal Current
Bipolar Transistor Breakdown Mechanisms
Marko Koričić, Josip Žilak, and Tomislav Suligoj
Breakdown behavior of double-emitter reduced-surface- field horizontal
current bipolar transistor is extensively analyzed by measurements and
3D device simulations. By the addition of the 2nd drift region, BVCEO of
double-emitter structure is improved from 12 V up to 36 V and can be
tuned by the length of the drift region. By increasing the length of the
drift region, positive feedback loop of the common-emitter softbreakdown can be completely broken making the BVCEO independent
on transistor current gain. Transistors with BVCEO and BVCBO equal to
the collector-substrate breakdown voltage are demonstrated. We also
report that base current reversal in forced-VBE measurement does not
occur and cannot be used for accurate determination of BVCEO of
analyzed structures.
(2.4) 11:00–11:25 AM – DC and RF breakdown
voltage characteristics of SiGe HBTs for WiFi PA
applications
Vibhor Jain, Hanyi Ding, Renata Camillo-Castillo, Alvin Joseph
Breakdown voltage and RF characteristics relevant for RF power
amplifiers (PA) are presented in this paper. Typically, DC collector-toemitter breakdown voltage with base open (BVCEO) or DC collector-tobase breakdown with emitter open (BVCBO) has been presented as the
metric for voltage limit of PA devices. In practical PA circuits, the RF
envelope voltage can swing well beyond BVCEO without causing a
failure. An analysis of output power swing limitations and DC
breakdown is presented with attention to biasing and temperature.
3. Emerging Technologies
Monday 12:40 PM — Brunswick Ballroom
Session Chair: Michael Schroter
(3.1) 12:40–1:20 PM – 5G Front-End Component
Challenges (Invited)
Stephen J. Kovacic
Semiconductor and package technology choices for 5G
communication systems are considered. The market context and
existing RF Front-End UE architectures are reviewed with emphasis on
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SIP technology. Rapid customization of modules is needed in order to
serve different manifestations of 5G systems in the early phases of
market deployment.
(3.2) 1:20–2:00 PM – The Scientific Challenge of
Replacing the Transistor with a Lower Voltage
Device (Invited)
Eli Yablonovitch
The NSF Center for Energy Efficient Electronics Science (E3S) is
searching for an ultralow-voltage switching device to replace the
current transistor. E3S applies a multi-disciplinary approach, involving
four
research
themes:
nanoelectronics,
nanomechanics,
nanophotonics, and nanomagnetics. This talk will try to answer:
What’s standing in the way?
(3.3) 2:00–2:40 PM – THz Bandwidth InP HBT
Technologies and Heterogeneous Integration with Si
CMOS (Invited)
M. Urteaga, A. Carter, Z. Griffith, R. Pierson, J. Bergman, A.
Arias, P. Rowell, J. Hacker, B. Brar, and M.J.W. Rodwell
Through aggressive lithographical and epitaxial scaling, the
bandwidths of InP-based heterojunction bipolar transistors have been
extended to THz frequencies. At 130nm emitter dimensions, transistors
with maximum frequencies of oscillation (fmax) of >1THz have been
demonstrated with accompanying circuit demonstrations at 670GHz. At
250nm emitter dimensions, high efficiency and high power density mmwave power amplifiers covering E-band (71GHz) to G-band (235GHz)
have been fabricated. The utility of these high performance transistors
can be further enhanced through heterogeneous integration with Si
CMOS. We have demonstrated wafer-scale 3D integration of InP and
Si using a low temperature oxide-to-oxide bonding process with
embedded Cu interconnects.
2:40–3:00 PM – Thirty Years of BCTM, a
Unique Conference (Invited) – Brunswick
Ballroom
Paul Davis and John Shirer
A look back at the history of the conference through photographs and
stories including
● transitional events (such as the first year)
● "interesting" anecdotes (such as Bob Pease, declaring himself the
Czar of voltage Regulators, and dressing for the part)
● special events (such as the transistor birthday)
● "brag points" of BCTM (such as the prestige of the invited speakers,
incl. 2 Nobel Prize Winners), quality publications, and the
cooperative unpaid committee
● technical (vs. exhibitor) emphasis
Paul Davis was educated at WVU, MIT, and Lehigh University with a
BS, MS, and PhD degree (1968). After a 2-year tour in the Army as an
electronic instructor, he joined Bell Labs of AT&T, in 1962, as a
Member of Technical Staff. While there, he designed custom bipolar
IC’s for several different types of Bell System products, including
Picturephone © Visual Telephone, Undersea Cable, desk set keypad
dial, T1 and D bank circuits, undersea cable regenerators, 200 MHz
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fiber optic and clock recovery circuits, electronic telephone line feed
circuits, and GSM cellular transceivers IC’s. The bipolar/SAW cellular
architecture he developed and promoted in the early 1990’s sold over
1 Billion phones by 1998. He retired from Lucent-Bell Labs in 2001. He
has 19 US patents, and was elected Fellow of IEEE in 2011, with the
citation, “for development of bipolar integrated circuits”. He has
attended BCTM since 1989, and was a member of the Technical
and/or Executive committees for 20 years. He has attended ISSCC
continuously for more than 50 years and was on the Technical
Committee for 10 years.
4. Circuit Techniques for Transmitters
Monday 3:15 PM — Brunswick Ballroom
Session Chair: Patrice Gamand
Co-Chair: Leonardo Vera
(4.1) 3:15–4:05 PM – Applying Bipolar Transistors in
Dynamic Power Supply Transmitters (Invited)
Earl McCune
Dynamic power supply transmitters (DPST), including the techniques
of envelope tracking (ET) and direct polar (DP) modulation, have a
century of success in some applications. The original motivation was to
improve the energy efficiency of the final power amplifier (PA), and that
remains true today. These are methods to improve overall energy
efficiency across wide signal and tuning bandwidths. Not all transistor
types perform equally well in the various DPST architectures. This
paper provides a quick review of DPST techniques and then examines
how the presently available bipolar transistors apply to the various
DPST options. It is concluded that bipolar transistors are presently
much more suitable for ET than for DP implementations.
Measurements demonstrate and explain this difference.
(4.2) 4:05–4:30 PM – The Impacts of Base Ballast
Resistor and LTE 16QAM Signal Bandwidth on HighEfficiency Linear SiGe Power Amplifier Design
(Student)
J. Tsay, J. Lopez, and D.Y.C. Lie
This paper investigates the design of a linear highly-efficient SiGe
power amplifier (PA) where its linearity, power-added efficiency (PAE)
and POUT are studied vs. different LTE 16QAM signal BW and base
ballast resistance Rb. The PA is designed in a 0.35-μm SiGe BiCMOS
technology with through-silicon via (TSV), passing the stringent LTE
spectrum emission mask (SEM) at average linear POUT =
23.5/23.1/23.1 dBm with 48.0/45.2/44.6% PAE for LTE 5/10/20 MHz
inputs at Rb = 500 Ω. However, both linearity and PAE degrade when
Rb decreases to 330 Ω or increases to 1000 Ω. The adjacent channel
leakage ratios ACLR1/ACLR2 exhibit over 10-21 dB degradation at Rb
= 330 Ω and 1000 Ω for LTE 20 MHz input at POUT = 23.1 dBm (P1dB =
22.3 dBm), while they are practically unchanged against Rb for 5 MHz
LTE input or at 6 dB POUT back-off at 17.1 dBm. Envelope-tracking (ET)
is also used to improve PA's efficiency at back-off for Rb = 500 Ω. The
data suggests for SiGe PA design with TSV, Rb can be used to
improve thermal stability, while its performance are dependent on RF
signal bandwidth, Rb, BVCER, and I/O matching, making design
optimization complex.
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(4.3) 4:30–4:55 PM – A Low Phase Noise Tri-band LO
Generation for Ku and E Band Radios for
Backhauling Point-to-Point Applications (Student)
D. Cabrera, JB Begueret, N. Verascina, O. Tesson, O.
Mazouffre, P. Gamand
This paper demonstrates a fully integrated tri-band LO generation
system based a low phase noise 12 GHz sub-harmonic VCO and an
injection locked frequency tripler (ILFT) as the signal source. The
system generates simultaneously three outputs at fo, fo/2 and 2×fo,
with maximum frequency of 36 GHz, 18 GHz and 72 GHz respectively.
The system which is implemented in a 0.25-μm SiGe:C BiCMOS
technology, has a phase noise of -107.72 dBc/Hz at 1 MHz offset from
the 36 GHz signal measured at the fo -port. All outputs have a tuning
range of 9.5%. The in-band output power at the fo, fo/2 and 2×fo
outputs is higher than 3 dBm, 0 dBm and -20 dBm respectively. The
whole system draws 120 mA for a power supply of 2.5 V.
5. State of the Art SiGe Technology
Monday 3:15 PM — Conference Room # BC
Session Chair: Jack Pekarik
Co-Chair: Alexander Fox
(5.1) 3:15–3:40 PM – A 90nm BiCMOS Technology
featuring 400GHz fMAX SiGe:C HBT
V. P. Trivedi, J. P. John, J. Young, T. Dao, D. Morgan, I. To, R.
Ma, D. Hammock, S. Mehrotra, L. Radic, B. Grote, T.
Roggenbauer, and J. Kirchgessner
A 90nm BiCMOS technology with a SiGe:C HBT having fMAX >400GHz
is presented. Both lateral and vertical scaling of the SiGe bipolar
transistor are described, enabling SiGe HBT performance metrics
fT/fMAX of ~230GHz/400GHz to be achieved with a minimum gate delay
of <3ps. A medium breakdown device is also integrated, achieving an
fT*BVCEO product of 310GHz*V. CMOS implant and HBT process
optimizations to address the additional thermal budget of the HBT
module are also discussed. In concert with high-quality passives, this
technology is especially suited for millimeter wave applications with
high digital gate density requirements.
(5.2) 3:40–4:05 PM – Advanced Si/SiGe HBT
architecture for 28-nm FD-SOI BiCMOS (Student)
V.T. Vu, D. Celi, T. Zimmer, S. Fregonese, P. Chevalier
This paper presents a novel Fully Self-Aligned Architecture (FSA)
Si/SiGe HBT architecture using Selective Epitaxial Growth (SEG) and
featuring an Epitaxial eXtrinsic Base Isolated from the Collector
(EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI
CMOS technology developed at STMicroelectronics. All the
parameters of the architecture such as the boron-doped base link, the
emitter width and height, the pedestal oxide and sidewall thicknesses
are evaluated by TCAD simulation. A low base-collector capacitance,
independent from the extrinsic base doping is obtained. Optimized
architecture exhibits 420 GHz fT and 780 GHz fMAX.
(5.3) 4:05–4:55 PM – Advantages of SiGe-pnp over
Si-pnp for Analog and RF enhanced CBiCMOS and
Complementary Bipolar Design Usage (Invited)
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Jeff A. Babcock, Joel Halbert, Hiroshi Yasuda, Alexei
Sadovnikov, Jonggook Kim, Alan Buchholz, Robert Malone,
Marco Corsi, Greg Cestra, and Mattias Dahlstrom
The evolution of silicon and silicon-germanium pnp transistors is
reviewed in this paper. The motivation for SiGe-pnp transistors in
Complementary Bipolar (CBi) and CBiCMOS is discussed with a view
on device parametric parameters that help gage the usefulness of
these devices in analog and RF design. We review the basic process
architectures and process building blocks for CBiCMOS. SiGe-pnp
versus Si-pnp performance metrics are highlighted followed by a
discussion on circuit blocks that benefit from having near matched
complementary bipolar transistors.
Tuesday, September 27, 2016
KEYNOTE SPEECH
8:30–9:30 AM — Brunswick Ballroom
“Large-area Flexible Hybrid Electronics:
A Hardware Platform for the Internet of Things
and People (IoTP)”
James C. Sturm, Naveen Verma and Sigurd Wagner
(Princeton University)
An emerging trend in electronic systems is the ability to gather data
and interact with the human environment – both humans themselves
and their physical infrastructure. People are on the scale of meters in
size, and their physical infrastructure can be much larger still. These
length scales are incompatible with the millimeter length scale and rigid
form factor of conventional IC’s. Large-area electronics built directly
on flexible plastic or metal sheets, meters in size, is of the right scale to
integrate sensors for such applications. A flexible and stretchable form
factor may be crucial for the application, or for transporting and
installing a final product such as a roll of “electronic wallpaper.” On the
other hand, handling the large amount of data from sensors and
interfacing with the cloud will inevitably require IC’s, as transistors
directly fabricated on large-area substrates at low-temperature and
with low-cost lithography have relatively poor performance. Thus a
“hybrid” approach is required, selectively integrating a minimum
number of IC’s, but using thin film devices when the electronics must
be dispersed over large areas.
This talk will review the design and experimental performance of four
different large-area hybrid systems (i) strain sensing sheets for civil
infrastructure monitoring, (ii) a “remote” gesture sensing system based
on a capacitive approach that can sense gestures from distances
approaching one meter, (iii) a “voice separation” system, consisting of
a 2-meter array of flexible microphones, which isolates individual
speakers when multiple people are speaking at once, and (iv) a flexible
and conformal EEG sensing system.
These systems will be used to illustrate a platform approach towards
building such systems based on laminating multiple sheets of different
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functionalities together, as opposed to straightforward monolithic
integration, using near-field wireless approaches to transmit data and
power from one sheet to another without metal-metal contacts, which
might be problematic in flexible systems. These systems rely on core
thin-film circuitry blocks such as low-power sensor scanning, low-noise
chopper-stabilized
amplifiers,
high-frequency
oscillators
and
demodulators, and data compression before IC interfacing. The circuit
performance can be enhanced by the high-quality passives available in
large-area technology. Finally, the impact of improved thin film device
technologies on the systems and circuit blocks will be described.
In the mid-90's, I led the creation of some of the first smart wearable
computers (back then we considered under 50 lbs to be "wearable").
Our initial goal was to recognize human emotion from objective data
measured from our bodies, and use it to make the technology smarter.
We created new algorithms for signal processing and used machine
learning to combine information from physiology, faces, voices,
posture, and gesture. In this talk I will highlight some of the more
surprising discoveries enabled recently as these wearable sensing
technologies have evolved. These include how electrical signals on
the surface of the wrist can communicate emotional excitement, stress
and deep brain activity, and how everyday wearable motion sensors
can be mined for information communicating your heart-rate,
respiration, and identity. I'll present ways in which wearables can
affect our social-emotional and personal connections, with surprising
implications drawn from autism, sleep, epilepsy, and learning.
James C. Sturm was born in Berkeley Heights, NJ, in 1957. He
received the B.S.E. degree in electrical engineering and engineering
physics from Princeton University in 1979 and the M.S.E.E. and Ph.D.
degrees in 1981 and 1985, respectively, both from Stanford University.
In 1979, he joined Intel Corporation, Santa Clara, CA, as a
Microprocessor Design Engineer, and in 1981 he was a Visiting
Engineer at Siemens, Munich, Germany. In 1986, he joined the faculty
of Princeton University, where he is currently the Stephen R. Forrest
Professor in Electrical Engineering. From 1998 to 2015, he was the
director of the Princeton Photonics and Optoelectronic Materials
Center (POEM) and its successor, the Princeton Institute for the
Science and Technology of Materials (PRISM). In 1994- 1995, he was
a von Humboldt Fellow at the Institut fuer Halbleitertechnik at the
University of Stuttgart, Germany. He has worked in the fields of siliconbased heterojunctions, thin-film and flexible electronics, photovoltaics,
the nano-bio interface, three-dimensional (3–D) integration, and
silicon-on-insulator. Dr. Sturm is a fellow of IEEE. He has won over
ten awards for teaching excellence and was a National Science
Foundation Presidential Young Investigator. In 1996 and 1997, he was
the technical program chair and general chair of the IEEE Device
Research Conference, respectively. He served on the organizing
committee of IEDM (1988 to 1992 and 1998 to 1999), having chaired
both the solid-state device and detectors/sensors/displays committees.
He has served on the boards of directors of the Materials Research
Society and the Device Research Conference, and co-founded Aegis
Lightwave and SpaceTouch.
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6. Analog Circuits
Tuesday 9:50 AM — Brunswick Ballroom
Session Chair: Laleh Najafizadeh
Co-Chair: Kimia Ansari
(6.1) 9:50–10:15 AM – Linear Ultra-Broadband NPNOnly Analog Correlator at 33 Gbps in 130nm SiGe
BiCMOS Technology (Student)
A. R. Javed, J. C. Scheytt and U. v. d. Ahe
An ultra-broadband analog correlator consisting of a four-quadrant
multiplier and an ultra-fast resettable integrator using only NPN
transistors was designed, fabricated, and measured. For the integrator,
a cross-coupled transistor pair is used as a negative resistance
generator. A novel ultra-fast reset circuit is implemented which allows
to reset the integrator within very short time of 120 ps. The chip was
fabricated using 130 nm SiGe BiCMOS technology with fT of 250 GHz
and fmax of 300 GHz. In the measurements carried out on printed circuit
board, the correlator operated without noticeable performance
degradation with inputs up to 33 Gbps which correspond to a
bandwidth of more than 24 GHz. The correlator exhibits high linearity
with output P1dB of more than 9.9 dBm (700 mVdiff) for both inputs. It
dissipates 122.5 mW for the core circuit excluding the 50 Ω output
driver. To the knowledge of the authors, the circuit represents the
fastest analog correlator published so far. It can be used for spread
spectrum communication, radar signal processing, and measurement
applications.
(6.2) 10:15–10:40 AM – Current Regulator with
Energy Limitation in the Unpowered State Featuring
Bipolar Discharge Path
Sri Navaneeth Easwaran, Sunil Kashyap Venugopal, Robert
Weigel
A new technique for limiting the surge current during short to battery in
the unpowered state of low side driver is presented. This technique
does not affect the main current regulation behavior in the powered
state. The energy is limited to 28 micron Joules in the unpowered state
and regulates the current to 3 A in the powered state of the driver.
(6.3) 10:40–11:05 AM – A 4-GHz 32-bit Direct Digital
Frequency Synthesizer in 0.25 µm SiGe HBT with
SFDR > 46 dBc up to Nyquist Bandwidth (Student)
Xuan Guo, Danyu Wu, Lei Zhou, Huasen Liu, Jin Wu, and
Xinyu Liu
A 32-bit direct digital frequency synthesizer with a maximum operating
frequency of 4.5 GHz fabricated in 0.25 m SiGe HBT is presented.
The phase-to-amplitude mapping circuit is implemented with nonlinear
DAC coarse quantization and ROM-based piecewise linear
interpolation. The measured SFDR is between 46 dBc and 60 dBc
under a 4.0 GHz clock and the hopping time is less than 10 ns. This
chip occupies 5.25 mm2 including bond pads and dissipates 3.46 W
with a 4.0 V digital supply and 4.0 V analog supply. The proposed
DDFS demonstrates excellent performance achieving a FOM of 234.9
GHz ·2(SFDR/6)/W.
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(6.4) 11:05–11:30 AM – A 30 GS/s 6-bit SiGe ADC
with Input Bandwidth over 18 GHz and Full Data Rate
Interface
Danyu Wu, Lei Zhou, Yinkun Huang, Peng Wang, Jin Wu, Zhi
Jin and Xinyu Liu
In this paper, a time-interleaved 30GS/s 6bit ADC fabricated in 0.18μm
SiGe BiCMOS technology has been demonstrated. A bandwidth
boosting technique and packaging solution has been proposed which
enables the ADC to achieve input bandwidth over 18 GHz. A full data
rate interface is integrated to transmit all the data in real time. The
ADC has a SFDR >35 dBc over the entire Nyquist frequency. An
effective number of bits (ENOB) above 5.0 are achieved for low
frequency input tones, dropping to 3.5 at 16 GHz.
7. Linking Devices, Circuits and Systems
Tuesday 9:50 AM — Conference Room # BC
Session Chair: Breandán Ó hAnnaidh
Co-Chair: Andrej Rumiantsev
(7.1) 9:50–10:40 AM – Co-simulation and Co-design
of Chip-Package-Board Interfaces in HighlyIntegrated RF Systems (Invited)
V. Issakov, M. Wojnowski, H. Knapp, S. Trotta, H.-P. Forstner,
and K. Pressel
The level of integration for RF and mm-wave systems is continuously
increasing. Highly-integrated system on chip solutions have to be
encapsulated in a package and assembled on a board. In addition, to
be more attractive as a product, the trend goes towards further
integration of passives and antennas in a package. This drives the
system in package solutions. However, electrical properties of the
package and board may have a significant effect on system
parameters, especially at high frequencies. Hence, layout features of
package and board must be carefully modelled and considered during
the design. Furthermore, it is often insufficient to model chip, package
and board separately, as some high-frequency effects may not be
captured. An example is electromagnetic coupling between integrated
coils on chip and routing traces in package. In this paper we describe
considerations on co-simulation and co-design of highly-integrated RF
systems by means of accurate electromagnetic modelling. We
demonstrate the approach and various aspects of chip-package-board
co-design based on examples of systems for various applications: 6
GHz VCO using embedded inductor; backhaul communication system
in package for V-band and E-band and a four-channel 77 GHz
automotive radar transceiver in a package with four dipole antennas.
(7.2) 10:40–11:05 AM – The Broadband Darlington
Amplifier as a Simple Benchmark Circuit for
Compact Model Verification at mm-Wave Frequency
(Student)
Anindya Mukherjee, Chenye Lin, Michael Schröter
Benchmark circuit are small circuit blocks that resemble the major
features of the active and passive devices for a given process
technology. Such blocks are attractive for verifying the compact
models delivered in process design kits as well as for demonstrating
the process performance at the earliest possible time. This paper
presents results of two broadband Darlington amplifier versions that
30th Year
1986-2016
were designed as a benchmark circuit during the EU DOTSEVEN
project with the purpose of verifying compact models at mm-wave
frequencies and under realistic circuit operating conditions. The circuits
were fabricated and its measured performance is compared to
simulation results.
(7.3) 11:05–11:30 AM – Analysis and Modeling of the
Long-Term Ageing Rate of SiGe HBTs under MixedMode Stress
G. G. Fischer
By means of long-term mixed-mode stress tests of high-speed SiGe
HBTs an empirical ageing function for compact models was
constructed. This ageing function models saturation of the aging rate
as a function of stress time and stress current and is applicable for all
relevant mixed-mode stress conditions of this HBT type. Additionally,
1000h stress tests on a high-voltage HBT revealed that not only
saturation but even reversal of ageing rate is possible in the long run.
8. Advanced Wireless Building Blocks
Tuesday 12:50 PM — Brunswick Ballroom
Session Chair: Dietmar Kissinger
Co-Chair: Hua Wang
(8.1) 12:50–1:40 PM – Beyond the Boundaries:
Enabling New Circuit Opportunities by Using SiGe
HBTs in Counterintuitive Ways (Invited)
John D. Cressler
SiGe HBT technology has enjoyed substantial success over the past
25 years for use in realizing performance-constrained, highlyintegrated mixed-signal electronics spanning the range of DC to submm-wave operational frequencies. This success has been bolstered by
advances in device scaling which have been truly impressive, now
routinely achieving multi-hundred GHz frequencies, a fact which is
currently opening many new and interesting application possibilities.
Most of these emerging opportunities were never envisioned at the
very beginning of this field (which is reflective of the inherent nature of
innovation), and many involve using the SiGe HBT in ways which may
appear counterintuitive to “classical” circuit designers. Examples
include operation: in radiation environments, in inverse mode, in weak
saturation, beyond SoA boundaries, at deep cryogenic temperatures,
and at high temperatures. This invited paper will explore this emerging
design space, both from device and circuit perspectives.
(8.2) 1:40–2:05 PM – A Passive Total Power
Radiometer in 0.25 μm SiGe BiCMOS for Millimeterwave Imaging (Student)
E.S. Malotaux and M. Spirito
In this paper we present a high sensitivity total power radiometer frontend integrated in a 0.25 μm SiGe BiCMOS technology. The radiometer
consists of a two-stage LNA co-integrated with a common-emitter
square-law detector, providing a 3 dB system bandwidth of 6 GHz
around 57 GHz. An optimized non-50-Ohm impedance interface
between the LNA and the detector results in an improved system
responsivity and sensitivity. The fabricated front-end achieves a peak
responsivity of 61 MV/W at 56 GHz, which, combined with an output
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spectral noise density 194 nV/√Hz at 500 Hz, results in an minimum
3.2 fW/√Hz NEP.
(8.3) 2:05–2:30 PM – A Wideband Active Bidirectional SiGe Digital Step Attenuator Using an
Active DPDT Switch
Moon-Kyu Cho, Ickhyun Song, Zachary E. Fleetwood, and
John D. Cressler
A 6-bit active bi-directional silicon-germanium (SiGe) digital step
attenuator (DSA) with multi-octave bandwidth using an active doublepole double-throw (DPDT) switch is demonstrated. To compensate the
insertion loss (IL) and frequency dependent loss characteristics of
conventional passive attenuators without using any additional amplifier
and equalizer, the proposed attenuator employs active DPDT switches,
which provide 4-way switching and bidirectional operation. The
measured gain is 6.0-8.0 dB and the input and output return loss is
better than 9 dB for 2-20 GHz. The measured root mean square (RMS)
amplitude and phase errors in the major state are less than 0.4 dB and
3.5 degree, respectively. The chip size is 1.43 x 1.23 mm2, including
pads. The proposed active bidirectional DSA consumes 24 mA from a
2.5 V supply.
9. Process Potpourri
Tuesday 12:50 PM — Conference Room # BC
Session Chair: Todd Thibeault
Co-Chair: Jay John
(9.1) 12:50–1:15 PM – Side-Use of a Ge p-i-n Photo
Diode for Electrical Application in a Photonic
BiCMOS Technology (Student)
S. Lischke, D. Knoll, S. Tolunay-Wipf, C. Wipf, C. Mai, A. Fox,
F. Herzel, and M. Kaynak
In this paper we demonstrate the potential use of a germanium p-i-n
diode, available without additional processing effort in a photonic
BiCMOS technology, for electronic applications. A cut-off frequency
above 400 GHz was obtained by s-parameter measurements without
any certain design optimization of the diode. The device construction
on SOI yields in the isolation of the diode from the substrate.
Moreover, the lateral current flow enables low series resistance for the
diode. Potential applications are antenna-switching or mixers.
(9.2) 1:15–1:40 PM – Ge-on-Insulator Lateral Bipolar
Transistors
J.-B. Yau, J. Yoon, J. Cai, T. H. Ning, K. K. Chan, S. U.
Engelmann, D.-G. Park, R. T. Mo, and G. Shahidi
We report the first demonstration of thin-base symmetric lateral NPN
bipolar transistors built on 8-inch Ge-on-insulator (Ge-OI) wafers. A
Ge-OI device can achieve the same collector current as a Si-OI device
but at ~ 460 mV lower VBE due to the bandgap of Ge being 460 meV
smaller than that of Si. Lower operation voltage should translate
directly into lower power dissipation. CMOS-like process was used to
fabricate lateral Ge-OI bipolar transistors. The measured collector and
base currents are examined and compared with those of Si-OI and
SiGe-OI devices to shed light on process-related device physics. The
large observed base current at small VBE is attributed to recombination
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at the Ge/BOX interface in the emitter-base diode space-charge
region.
(9.3) 1:40–2:05 PM – Low Gate Drive IGBT Enabling
Direct Control through Digital Isolator Power
Edward Coyne, Pat McGuinness, Seamus Lynch, Christine
McLoughline, Catriona O’Sullivan, Bill Lane, Larry O’Sullivan,
John Liddy
Known to the power industry, there is an increasing functional safety
need to isolate delicate control systems from the violent world of the
Insulated Gate Bipolar Transistor (IGBT), and this has resulted in a
growing demand for Digital Isolators. This is where the gate control
signal for the IGBT can be coupled across a dielectric barrier, while the
barrier itself is capable of withstanding high working voltages and
surge events.
(9.4) 2:05–2:30 PM – Novel npn Bipolar Transistor
with High Gain, High Early Voltage, and High BVceo in
an Advanced SmartMOS Technology
Xin Lin and Ronghua Zhu
A high performance npn bipolar transistor has been demonstrated in a
0.13μm SOI SmartMOSTM technology. This novel bipolar transistor
consists of a shallow emitter confined by shallow trench isolation (STI),
a base with multiple regions each serving a different purpose without
compromising one another, and a lightly doped collector region
surrounded by continuous p-type regions biased with the base
potential. The base region below the emitter has a relatively low
dopant concentration and is crucial to the carrier transport; the
relatively more heavily-doped and deep base region between the
emitter and collector effectively confines the depletion of the collector;
and the p-type region above the collector as well as the p-epi
surrounding the collector enable the collector to be fully depleted when
the collector is biased high. Attributed to these unique features, the
npn bipolar transistor exhibits superior characteristics, including a high
current gain of 83, a high Early voltage of 1750V, and a high BVceo of
59V.
10. Bipolar Transistor Compact Modeling
Tuesday 2:50 PM — Brunswick Ballroom
Session Chair: Peter Zampardi
Co-Chair: Breandán Ó hAnnaidh
(10.1) 2:50–3:15 PM – Why is There No Internal
Collector Resistance in HICUM?
M. Schröter, S. Lehmann, and Andreas Pawlak
The internal (or epi-) collector region in a bipolar (hetero-)junction
transistor strongly determines the bias dependent terminal behavior.
Most compact transistor model attempt to capture the current-voltage
behavior of the epi-collector by a special equivalent circuit element
(and associated analytical formulations) in addition the usual transfer
current source representing just the base region. This paper provides
(i) theoretical proof that a separate representation of the epi-collector
region in an equivalent circuit is neither required nor necessarily
advantageous in terms of accuracy and (ii) a physics-based guide on
how to model the epi-collector consistently if a separate description is
still desired. The theoretical results are validated by numerical device
simulation.
30th Year
1986-2016
(10.2) 3:15–3:40 PM – A HICUM/L2 Model for HighVoltage BJTs
Andreas Pawlak, Breandán Ó hAnnaidh, Michael Schroter
Although latest developments in Si BJTs and SiGe HBTs typically
focus on high-speed devices and strong competitors for high-voltage
(HV) devices exist (e.g. GaAs HBTs and HEMTs), HV Si BJTs still find
widespread application. This paper demonstrates the application of
HICUM/L2 to Si BJTs with very high breakdown voltages and
highlights the model features that are relevant for the most prominent
properties of HV transistors. It further provides a guideline for
parameter extraction. Very good agreement over the entire operating
and a wide temperature range are obtained.
(10.3) 3:40–4:05 PM – An Improved Scalable SelfConsistent Iterative Model for Thermal Resistance in
SiGe HBTs (Student)
Suresh Balanethiram, Anjan Chakravorty, Rosario D’Esposito,
Sebastien Fregonese, Thomas Zimmer
In this paper we present an improved self-consistent iterative model for
thermal resistance in SiGe HBTs. The proposed model evaluates both
the upward and downward heat dissipation from the heat source
located at the base-collector junction. Along with the temperature
dependency, thermal conductivity degradation due to heavy doping
and Ge composition in the base region is included in the proposed
model. It is observed that the model accuracy is improved once these
physical effects are included along with the upward heat diffusion.
Scalability of the proposed model is validated with the measured data
for different emitter geometries.
(10.4) 4:05–4:30 PM – Hybrid Small-Signal -Model
for the Lateral NQS Effect in SiGe HBTs (Student)
Shon Yadav, Anjan Chakravorty, and Michael Schroter
The state-of-the-art and -models for the lateral non-quasi-static (NQS)
effect are analyzed. The superiority of the -model to capture the
lateral NQS effect is demonstrated through small-signal simulations of
both the models, implemented in Verilog-A. A hybrid model is
proposed and a corresponding formulation of the base impedance is
obtained. The equation gives the base impedance of the state-of-theart as well as the -model under appropriate conditions. The
methodology to implement the hybrid model in Verilog-A is discussed.
The hybrid model shows significantly higher accuracy than both the
state-of-the-art model and the -model when compared with the device
simulation data.
11. Millimeter-wave Transmitters and
Receivers
Tuesday 2:50 PM — Conference Room # BC
Session Chair: Bruce Kim
Co-Chair: Thierry Taris
(11.1) 2:50–3:40 PM – Circuit Techniques for HighEfficiency Millimeter-wave Transmitters in SiGe and
CMOS SOI Processes (Invited)
James F. Buckwalter
30th Year
1986-2016
Injection locking circuit techniques could enable highly efficient
operation in future millimeter-wave radio transmitters integrated in
highly-scaled Silicon CMOS/BiCMOS technologies. Enabling spectrally
efficient communication at millimeter-wave bands (>30 GHz) is
reviewed to specifically investigate operation under back-off conditions
and comparisons are made between high-efficiency transmit
architectures at mm-wave bands. This work suggests that outphasing
modulation using injection locking as a well suited approach for phase
generation. A microwave demonstration is reviewed to discuss the
issues confronting extending these architectures. The injection-locked
outphasing modulator circuit is implemented in 45 nm SOI CMOS and
delivers 9.2 dBm to a 50- external load at 8 GHz while consuming
only 36.5 mW to achieve a 22.7% overall system efficiency with a 64QAM 2.1% Error Vector Magnitude (EVM) at 60 Mb/s. Additionally, the
application of similar injection locking techniques for millimeter-wave
phased array transceivers is discussed and recent work is reviewed on
these systems at 71-86 GHz.
(11.2) 3:40–4:05 PM – A 76- to 81-GHz Packaged
Single-Chip Transceiver for Automotive Radar
Takeji Fujibayashi, Yohsuke Takeda, Weihu Wang, Yi-Shin
Yeh, Willem Stapelbroek, Seiji Takeuchi, and Brian Floyd
This paper presents a flip-chip packaged 76- to 81-GHz transceiver
chip implemented in SiGe BiCMOS technology for both long-range and
short-range automotive radar applications. The single chip contains a
two-channel transmitter with +18-dBm saturated output power per
channel; an LO chain with x4 multiplier, wide-band 20-GHz VCO with 100-dBc/Hz phase noise at 1-MHz offset referenced to a 77-GHz
carrier, and divide-by-four prescaler; and a six-channel receiver with
10- to 11-dB noise figure, 14- to 15-dB conversion gain and +1-dBm
input P1dB in unpackaged condition. The interconnect loss through the
BGA package at 80 GHz is 1.5 to 2 dB. Built-in self-test (BIST) circuits
are integrated to enable RF output power, receiver gain, relative
channel-to-channel phase and internal temperature measurement.
(11.3) 4:05–4:30 PM – Scalable Sensor Platform with
Multi-Purpose Fully-Differential 61 and 122 GHz
Transceivers for MIMO Radar Applications
Herman Jalli Ng, Maciej Kucharski, Dietmar Kissinger
This paper describes a scalable sensor platform consisting of several
multi-purpose 61 and 122 GHz transceivers that are designed in a
fully-differential architecture and implemented in a Silicon-Germanium
BiCMOS technology. The former transceiver achieves a higher
transmit output power as well as receive gain and is meant for
applications requiring a high dynamic range, while the latter transceiver
allows a higher modulation bandwidth and is meant for high resolution
applications. The transceivers include a frequency multiplier that
generates the 61 and 122 GHz carrier signals from a single external
30.5 GHz LO signal that is also fed to an output buffer in the
transceivers. The proposed architecture enables the cascading of
multiple transceivers and allows thus the implementation of a MIMO
radar system with 2 different frequency bands. The transceivers are
equipped with BPSK modulators as well as an I/Q receiver and can be
utilized as a base to build a very flexible software-defined radar
platform.
30th Year
1986-2016
(11.4) 4:30–4:55 PM – A 162 GHz Power Amplifier
with 14 dBm Output Power (Student)
Jidan Al-Eryani, Herbert Knapp, Jonas Wursthorn, Klaus
Aufinger, Soran Majied, Hao Li, Sabine Boguth, Rudolf
Lachner, Josef Boeck, and Linus Maurer
A 3-stage power amplifier (PA) with 14dBm saturated output power
(Psat), 29.5 dB small-signal gain, and 4.8% power-added efficiency
(PAE) at a frequency of 162GHz is presented. From 155 to 165 GHz,
Psat remains higher than 12.5 dBm, while the small-signal gain varies
from 35.4 dB to 28.3 dB. Maximum output power and gain
performance are obtained by using a differential cascode topology and
operating the transistors well beyond their open-base collector-emitter
breakdown voltage (BVCEO), and by optimum matching of the three
stages of the PA. To our best knowledge, this is the highest reported
output power for a silicon-based PA beyond 150 GHz. The chip is
fabricated in a 130nm SiGe BiCMOS technology with fT /fmax = 250/370
GHz.
EXECUTIVE COMMITTEE
Doug Weiser
Texas Instruments, General Chair
Fa Foster Dai
Auburn University, Technical Program Chair
Peter Magnee
NXP Semiconductors, Technical Program Vice-Chair
Pete Zampardi
Qorvo, Publications Chair
Edward Preisler
TowerJazz, Short-Course Chair
Wibo Van Noort
Texas Instruments, Short-Course Vice-Chair
Michael Schroter
TU Dresden / UC San Diego, Emerging Technology Chair
Laleh Najafizadeh
Rutgers, Local Arrangements Chair
Rob Rassel
GLOBALFOUNDRIES, Finance Chair
Sorin Voinigescu
University of Toronto, JSSC Guest Editor
Edward Preisler
TowerJazz, Publicity Chair - US
Andrej Rumiantsev
MPI Corporation, Publicity Chair - Europe/Asia
Catherine Shaw
C. Shaw, LLC, Conference Manager
Patrice Gamand
Consulting PG, Analog & Mixed-Signal Chair
Tomislav Suligoj
University of Zagreb, Device Physics Chair
Breandán Ó hAnnaidh
Analog Devices, Modeling & Simulation Chair
Jay John
NXP Semiconductors, Process Technology Chair
Nils Pohl
Fraunhofer FHR, Wireless Chair
TECHNICAL PROGRAM COMMITTEE
ANALOG/MIXED SIGNAL SUBCOMMITTEE
Patrice Gamand
Sorin Voinigescu
Koichi Murata
Johann-Christoph Scheytt
Michael Möller
Laleh Najafizadeh
Kwang-Jin Koh
Kimia T. Ansari
DEVICE PHYSICS SUBCOMMITTEE
Tomislav Suligoj
Pete Zampardi
Peter Magnee
Jiahui Yuan
Vibhor Jain
Kai Kwok
Guanghai Ding
Jonggook Kim
MODELING/SIMULATION SUBCOMMITTEE
Breandán Ó hAnnaidh
Consulting PG, Chair
University of Toronto
GigOptix
University Paderborn
Saarland University
Rutgers
Virginia Tech
Huawei
University of Zagreb, Chair
Qorvo
NXP Semiconductors
SanDisk
GLOBALFOUNDRIES
Skyworks
Analog Devices
Texas Instruments
Analog Devices, Chair
30th Year
Andrej Rumiantsev
Adam DiVergilio
Marco Bellini
Michael Schroter
Vadim Issakov
Scott Parker
Jin Tang
PROCESS TECHNOLOGY SUBCOMMITTEE
Jay John
Alexander Fox
Jack Pekarik
Hiroshi Yasuda
Josef Boeck
Joost Melai
Todd Thibeault
Pascal Chevalier
WIRELESS SUBCOMMITTEE
Nils Pohl
Wibo Van Noort
Fa Foster Dai
Bruce Kim
Hua Wang
Thierry Taris
Wei Kung Deng
Dietmar Kissinger
Steve Kovacic
Yan Li
Michael McPartlin
Yuan Yao
Leonardo Vera
1986-2016
MPI Corporation
GLOBALFOUNDRIES
ABB
TU Dresden / UC San Diego
Infineon
Qorvo
Texas Instruments
NXP Semiconductors, Chair
IHP Microelectronics
GLOBALFOUNDRIES
Texas Instruments
Infineon
NXP Semiconductors
TowerJazz
STMicroelectronics
Fraunhofer FHR, Chair
Texas Instruments
Auburn University
City College of New York
Georgia Tech
University of Bordeaux
Richwave
IHP Microelectronics
Skyworks
Qorvo
Skyworks
Broadcom
Inphi Corp
30th Year
1986-2016
MAPS & LOCAL INFORMATION
Hyatt Regency New Brunswick
First floor level
Registration, coffee break, lecture
sessions
30th Year
1986-2016
Hyatt Regency New Brunswick
30th Year
1986-2016
Local Directory:
BANKS:
Bank of America 410 George Street (732) 545.5115
TD Bank 70 Bayard Street (732) 867.5732
Wells Fargo 120 Albany Street (732) 843.4200
BAR/LOUNGE:
George Street Ale House (American) 378 George St (732) 543.2408
Glo (Lounge) 367 George St (732) 246.8330
Perle (Nightclub) 13 Paterson St (732) 937.6113
BREAKFAST:
Hansel & Griddle (Breakfast/Sandwiches) $ 112 Church St (732) 846.9727
CaffeBene (Café/Coffee Shop) 356 George Street (732) 828.0760
COFFEE:
Dunkin’ Donuts (within New Brunswick Train Station) 1 Railroad Plaza (732)
220.1270
Dunkin’ Donuts 335 George St (732) 246.2070
Starbucks 391 George St (732) 828.8946
CONVENIENCE/GROCERY STORE:
7-Eleven (Convenience Store) 358 George St
Key Foods (Grocery) 100 Kirkpatrick St
Rite Aid (Pharmacy) 360 George St (732) 247.0814
ENTERTAINMENT:
George Street Playhouse 9 Livingston Ave (732) 846.2895
State Theater 15 Livingston Ave (732) 246.7469
Stress Factory (Comedy Club) 90 Church St (732) 545.4242
FAST FOOD/CASUAL DINING
Burger King (Fast Food) 373 George St (732) 246.3040
Destination Dogs (Hot Dogs) 101 Paterson St (732) 993.1016
Chipotle (Mexican) 387 George Street (732) 249.0070
Subway (Sandwiches) 354 George St, (732) 249-4440
GOVERNMENT:
New Brunswick Courthouse/Town Hall Kirkpatrick St & Bayard St
US Postal Service (USPS) 86 Bayard St (800) 275.8777
HOSPITALS:
Robert Wood Johnson Hospital Somerset St & Little Albany (732)828.3000
St. Peter’s Hospital 254 Easton Ave (732) 745.8525
RESTAURANTS:
Catherine Lombardi (Italian) $$$ 3 Livingston Ave (732) 296.9463
Chapathi House (Indian) $ 349 George Street (732) 416.8787
Clydz (American/Martinis) $$$ 55 Paterson St (732) 846.6521
Delta’s (Southern Cuisine) $$ 19 Dennis St (732) 249.1551
Desta (Ethiopian) $$ 88 Albany St (732) 249-0494
Due Mari (Italian/Seafood) $$$ 78 Albany St (732) 296.1600
Esquina Latina (Cuban) $$ 25 Liberty St (732) 543.1630
Frog and the Peach $$$$ (French-Inspired American) $$$$ 29 Dennis St (732)
846.3216
Harvest Moon Brewery & Café (American) $$ 392 George St (732) 249.6666
Hotoke (Japanese/Asian) $$ 350 George St (732) 246.8999
INC (American/New) $$ 302 George St (732) 640-0553
30th Year
1986-2016
Directory Cont’d
Indochine (Vietnamese/Asian) $$ 371 George St (732) 745-2928
Jimmy’s BBQ (American) $$ 5 Easton Ave (732) 249.7427
My Way (Korean) $$ 351 George St (732) 545.5757
Old Bay Restaurant $$ (Creole) 63 Church St (732) 246.3111
Old Man Rafferty’s (American) $$ 106 Albany St (732) 846.6153
Panico’s (Italian) $$$ 103 Church St (732) 545.6100
Stage Left (American) $$$ 5 Livingston Ave (732) 828.4444
Steakhouse 85 (Steakhouse) $$$ 85 Church St (732) 247.8585
Sushi Room (Japanese) $$ 12 Easton Ave (732) 640.0407
The Counter (Burgers) $ 341 George St (732).543.1267
Tumulty’s (Irish Pub) $$ 361 George St (732) 545.6205
Veganized (Vegan/Vegetarian) $$ 9 Spring St (732) 342.7412
World of Beer (Sports Bar) $$ 335 George Street (732) 543.1804
Mike’s Courtside (Sports Bar) $ 1 Elm Row (732) 455.8511
STAFF PICKS
HARVEST MOON BREWERY
“This is a great little brewery with excellent wings and live music (usually
on weekends). The great part about this place is that they also have a
dining room upstairs if you just need a quiet place to dine. They also have
Karaoke on the first Thursday of every month. ”
Christine Shin Rooms Manager
OLD MAN RAFFERTY’S
“Old Man Rafferty’s has been in this town for years and it’s the best place
for lunch. Try any of their sandwiches – the portions are perfect and don’t
forget to order one of their fabulous desserts.”
Roumany Tawadrous Assistant Rooms Manager
“I second Old Man Rafferty’s. If you love chocolate desserts, you have to
try the Vesuvius cake!”
Ashleigh Barrall Front Desk Agent
GARDEN STATE ALE HOUSE
“A great pub for a good drink and delicious appetizers – try the Bang Bang
Shrimp. If you prefer a quieter environment, they have additional seating
in the basement level. ”
Stephanie Cruz Front Desk Supervisor
THE COUNTER
“A great spot for a classic burger and fries. The build-your-own burger
option is a lot of fun with over a thousand different ingredient
combinations. If you’re looking for something sweet, the adult milkshakes
are a must!”
Erica Feliciano Front Desk Agent
CLYDZ
“This place not only makes the best martinis in the area, they also have
fantastic service. As you enter this Bar & Restaurant, you descend into a
basement level, which gives it a great speakeasy vibe. Try the For A Good
Time or Moscow Mule. Don’t forget to take home one of the drink napkins
– they have drink recipes on them!”
Lavanya Nayar Front Desk Agent
30th Year
1986-2016
CONFERENCE MANAGER
Catherine Shaw, CMP
BCTM Conference Manager
Phone: 732-501-3334
cshaw.cmpevents@gmail.com
CONFERENCE HEADQUARTERS
HYATT REGENCY NEW BRUNSWICK
2 Albany Street
New Brunswick, NJ 08901, USA
T: + 1.732.867.2258
30th Year
1986-2016
CALL FOR PAPERS
2017 BIPOLAR/BiCMOS CIRCUITS AND
TECHNOLOGY MEETING
Marriott Biscayne Bay, Miami, Florida, USA
www.ieee-bctm.org
Short Course: October 21, 2017;
Conference: October 19-20, 2017
The Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)
is a forum for technical communication focused on the needs
and interests of the bipolar and BiCMOS community. Papers
covering the design, performance, fabrication, testing and
application of bipolar and BiCMOS integrated circuits, bipolar
phenomena, and discrete bipolar devices are solicited. All
papers must be suitable for a twenty-minute presentation. Text
and figures must not have been presented at other
conferences or published in any scientific or technical
publications prior to BCTM.
Publication in the BCTM 2017 Proceedings does not preclude
publication in an IEEE journal, and authors are encouraged to
do so. A Special Section in the IEEE Journal of Solid-State
Circuits will include selected papers from BCTM 2017.
Papers are solicited in the following areas:
ANALOG/MIXED
SIGNAL: Analog ICs: Mixed
analog/digital ICs - Digital ICs - DACs and ADCs - Operational
amplifiers - Voltage references and regulators - Integrated
filters - Sensors - Networking ICs, MUX/DEMUX, Clock and
data recovery, Decision circuits, Equalizers - Optical data links,
Laser and modulator drivers - Gate arrays - Cell libraries High-voltage ICs - Medical electronics - Motor controls Analog subsystems within a VLSI chip - Packaging of highperformance ICs.
WIRELESS CIRCUIT DESIGN: Low Noise Amplifiers Automatic gain control - Mixers - Voltage controlled oscillators Frequency synthesizers - Power amplifiers - RF switches Suppression of noise and distortion - Radio subsystems - RF
Packaging - Integrated passives - Millimeter-wave circuits and
systems.
DEVICE PHYSICS: New device physics phenomena in Si,
SiGe, and III-V devices - Device design issues and scaling
limits - Hot electron effects and reliability physics - Transport
and high field phenomena - Noise - Linearity/Distortion - Novel
measurement techniques - Operation in extreme environments
(low and high temperatures, radiation effects).
30th Year
1986-2016
MODELING/SIMULATION: Improved BJT and HBT models
- Behavioral modelling techniques - Parameter extraction
methods and test structures - De-embedding techniques - RF
and thermal simulation techniques - Modelling of passives,
interconnect and packages - Statistical modelling - Device,
process and circuit simulation - CAD/modelling of power
devices - packaging of power devices and ESD phenomena.
PROCESS TECHNOLOGY: Advances in processes and
device structures demonstrating high speed, low power, low
noise, high current, high voltage, etc. BiCMOS processes Advanced process techniques - Si and Si-C homojunction
bipolar/BiCMOS devices, III-V and SiGe heterojunction
bipolar/BiCMOS devices. Manufacturing solutions related to
Bipolar and BiCMOS yield improvements. Fabrication of highperformance passive components, including, MEMs. Process
technology related to discrete and integrated bipolar/BiCMOS
power devices, IGBT, RF power devices including DMOS.
Wide bandgap bipolar devices (e.g., SiC, GaN, GaAs) and
related process technology.
WIRELESS CIRCUIT DESIGN: Low Noise Amplifiers Automatic gain control - Mixers - Voltage controlled oscillators Frequency synthesizers - Power amplifiers - RF switches Suppression of noise and distortion - Radio subsystems - RF
Packaging - Integrated passives - Millimeter-wave circuits and
systems.
STUDENT
paper
submissions
are
highly
encouraged. Papers must be clearly marked as 'STUDENT
SUBMISSION' in the paper submission system to be eligible
for the Best Student Paper Award.
If you know of people who may have a paper to
contribute, please bring this Call for Papers to their
attention.
IMPORTANT DEADLINES FOR AUTHORS
April 16, 2017: Abstract and manuscript submission deadline
June 12, 2017: E-mail notification sent.
September 4, 2017: Final proceedings manuscript due
SUBMISSION AND CONTACT INFORMATION
Visit the conference website: http://www.ieee-bctm.org, or
contact: Catherine Shaw, CMP, BCTM Conference Manager,
Phone 1-732 501-3334, e-mail: cshaw.cmpevents@gmail.com
30th Year
1986-2016
2016 BCTM SPONSORS
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