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Analog FE: ASIC
Upgrade of the front end electronics of the
LHCb calorimeter
D. Gascón, E. Picatoste, C. Abellan, F. Machefert, J. Lefrançois, O. Duarte
ICC-UB,URL,LAL
LHCb upgrade electronics – CERN – July 21th 2011
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Outlook
I.
Introduction
II.
Input stage
III. Channel architecture
IV.
Technology
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I. Introduction: current ECAL/HCAL FE
LAL-Orsay
HCAL
clip
Analogue 10 m
PM
ADC
ECAL
PM
L0
Trigger
clip
same
electronics
•Pulse shaping in 25 ns
•Residue < 1% after 25 ns
•Integrator plateau : 4 ns
•Linearity < 0.5%
•Rise time ~ 5 ns
Pipeline
Readout
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I. Introduction: motivation and task sharing
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PM current has to be reduced
ƒ Otherwise PMT would die rapidly (require a factor ~ 5)
ƒ FE electronics gain has to be increased correspondingly
ƒ FE noise should not be increased in the operation !
z
ƒ Voltage amplifier: < 1 nV/sqrt(Hz)
ƒ Current amplifier: < 10 pA/sqrt(Hz)
ƒ Active cooled termination required:
ƒ ASIC development @ UB (Edu’s and this talks)
Switch INT (Calc)
1E-11
DL INT (Sim)
1E-12
DL INT with Rg noise (Sim)
1E-13
CDS + Switched int (Calc)
1E-14
1E-15
PSD [V^2/Hz]
For 12 bit DR, input referred noise:
Current Amp [V^2/Hz]
1E-10
ƒ GBT for data transmission @ 40MHz
ƒ Digital development @ LAL (Frédéric’stalk)
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http://indico.cern.ch/materialDisplay.py?contribId=
1&sessionId=0&materialId=slides&confId=59892
New front end board is required:
ƒ Low noise analog electronics
z
See talk noise in June 2009 meeting:
1E-16
1E-17
1E-18
1E-19
1E-20
1E-21
1E-22
1E-23
1E-24
1,0E+00
But 2/3 of the signal are lost by clipping:
1,0E+01
1,0E+02
1,0E+03
ƒ Alternative solution: remove clipping at the PM base (detector)
ƒ Perform clipping after amplification in FE
ƒ Alternative analog COTS + delay line solution
ƒ COTS development @ URL (Carlos’ talk)
1,0E+04
1,0E+05
1,0E+06
1,0E+07
1,0E+08
1,0E+09
1,0E+10
f [Hz]
This talk considers single
ended implementation,
results should be scaled
by xsqrt(2)
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I. Introduction: requirements
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Requirements (LOI):
Energy range
Calibration
Dynamic range
Value
Comments
0-10 GeV/c (ECAL)
1-3 Kphe / GeV
Transverse energy
Total energy
4 fC /2.5 MeV / ADC cnt
4 fC input of FE card: assuming 25 Ω
clipping at PMT base
12 fC / ADC count if no clipping
4096-256=3840 cnts :12 bit
Enough? New physic req.? Pedestal
variation? Should be enough
Noise
<≈1 ADC cnt or ENC < 5 -6 fC
< 0.7 nV/√Hz
Termination
50 ± 5 Ω
Passive vs. active
AC coupling
Needed
Low freq. (pick-up) noise
Baseline shift
Prevention
Dynamic pedestal subtraction
How to compute baseline?
(also needed for LF pick-up)
Number of samples needed?
4-5 mA over 25 Ω
50 pC in charge
Max. peak current
1.5 mA at FE input if clipping
Spill-over
correction
Spill-over noise
Clipping
Residue level: 2 % ± 1 % ?
<< ADC cnt
Relevant after clipping?
Linearity
< 1%
Crosstalk
< 0.5 %
Timing
Individual (per channel)
PMT dependent
See talk about noise in
June 2009 meeting:
http://indico.cern.ch/materialDis
play.py?contribId=1&sessionId=
0&materialId=slides&confId=59
892
This talk considers single
ended implementation,
results should be scaled
by xsqrt(2)
II. Input stage: active line termination
z
Electronically cooled termination required:
ƒ 50 Ohm resistor noise is too high
ƒ e. g. ATLAS LAr (discrete component)
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Common gate with double voltage feedback
ƒ Inner loop to reduce input impedance preserving linearity and with low noise
ƒ Outer loop to control the input impedance accurately
Zi ≈
z
z
1 g m1
R1
+ RC1
G
R1 + R2
Transimpedance gain is given by RC1
Noise is < 0.5 nV/sqrt(Hz)
ƒ Small value for R1 and R2
ƒ Large gm1 and gm2
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Need ASIC for LHCb
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32 ch / board: room and complexity
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II. Input stage : LAPAS chip for ATLAS LAr upgrade
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TWEPP 09
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II. Input stage: LAPAS chip for ATLAS LAr upgrade
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Technology:
ƒ IBM 8WL SiGe BiCMOS
ƒ 130 nm CMOS (CERN’s techno)
ƒ Radiation tolerance:
ƒ FEE Rad Tolerance TID~ 300Krad,
ƒ Neutron Fluence ~1013 n/cm2
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Circuit is “direct” translation
ƒ Need external 1 uF AC coupling
capacitor for outer feedback loop
ƒ Three pads per channel required:
ƒ Input
ƒ Two for AC coupling capacitor
ƒ Voltage output
M. Newcomer “LAPAS chip”
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II. Input stage: current output / current feedback
• Current mode feedback:
ƒ Inner loop: lower input impedance
Why 2 outputs? Why 2 polarities?
See next slides
ƒ Current feedback (gain): mirror: K
ƒ Outer loop: control input impedance
ƒ Current feedback: mirror: m
• Current gain: m
• Input impedance
1 g m1 + Re
K
Zi ≈
mR f
+
1+ K
1+ K
• Current mode feedback used
ƒ Optical comunications
ƒ SiPM readout
• Low voltage
ƒ Only 1 Vbe for the super common base input stage
• Better in terms of ESD:
ƒ No input pad connected to any transistor gate or base
POWER < 10 mW
III. Channel architecture
Very difficult to
integrate HQ
anlog delay lines
z
z
z
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2 switched
alternated paths
as in PS/SPD
Switching noise !
Fully differential
ASAP
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Current mode amplifier
Switched integrator
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Fully differential Op Amp
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12 bit: flip-around architecture
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To match ADC input impedance
Track and hold
Analogue multiplexer
ADC driver
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III. Channel architecture: pseudo-differential input
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Pseudo-differential input attenuates ground (and CM) noise in FE:
ƒ Mitigates Vgndi (connducted) noise (attenuation depends on matching)
ƒ Symmetrical chip/PCB layout also mitigates capacitive coupling (xtalk, pick-up)
z
z
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Drawback: uncorrelated HF noise x √2
ƒ Predictable and stable effect
Current mode preamplifier makes easier pseudo differential input:
ƒ Current: 2 pads per channel
ƒ Voltage (external component): 6 pads per channel
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III. Channel architecture
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Switched integrator
ƒ
ƒ
ƒ
ƒ
Integrator plateau : 4 ns
Linearity < 1%
Residue < 1% after 25 ns
Reset time < 5 ns
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Rf to improve plateau
ƒ 100 ns time constant
ƒ Cancel slow component of
the clipped signal (remanent)
In+
+
-
FDOA
+
In-
Out0,2
Out+
t (ns)
0,0
-
0
25
50
75
100
125
150
175
CMOS
switches
V normalized
-0,2
-0,4
-0,6
-0,8
-1,0
Clipped Pulse (Anatoli)
-1,2
Test Pulse
200
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III. Channel architecture
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Track and hold
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12 bit: flip-around architecture
clk_n
Vin+
+
clk
clkd
Vrefth
clk
FDOA
clkd
Vin-
Vo-
-
+
-
clk
clk_n
Vo+
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III. Channel architecture
FDOA specifications
Parameter
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Fully differential Op Amp
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Folded cascode + Miller stage with CMFB
Folded
cascode
NPN CE
amp
M
M
VrefCE
M
VrefCE
Value
Gain bandwidth
500 MHz
Phase margin
> 65º
Slew rate
> 0.5 V/ns
VCM
1.2 to 1.8 V
M
M
M
Vout+
VoutM
Vcas
Vcas
Vin+
M
M
Vb1
Vb2
M
Vin-
RDegenertion
Vb2
Pole
compensation
Vcmref
Vb1
M
Vb2
M
M
Vb2
M
Common
Mode
Feedback
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IV. Technology: choice of technology
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SiGe BiCMOS is preferred:
ƒ SiGe HBTs have higher gm/Ibias than MOS: less noise, less Zi variation
ƒ SiGe HBTs have higher ft (>50 GHz): easier to design high GBW amplifiers
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Several technologies available:
ƒ IBM
ƒ IHP
ƒ AMS BiCMOS 0.35 um
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AMS is preferred
IBM
IHP
AMS
HBT ft
> 100 GHz
190 GHz
60 GHz
CMOS
0.13 um
0.13 um
0.35 um
Proto Cost
[€ /mm2]
>3K
>3K
ƒ Factor 2 or 3 cheaper
ƒ Too deep submicron CMOS not required / not wanted:
ƒ Few channels per chip (4 ?)
ƒ Smaller supply voltage
ƒ Worst matching
ƒ Radiation hardness seems to be high enough (to be checked)
1K
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IV. Technology: radiation tolerance
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Requirements:
ƒ Dose in 5 years (TID): 10-20 krad
ƒ Neutron fluence?
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AMS SiGe BiCMOS 0.35 um should be ok:
ƒ Omega studies about ILC calorimeters…
ƒ ATLAS: CNM studies: http://cdsweb.cern.ch/record/1214435/files/ATL-LARG-SLIDE-2009-337.pdf
ƒ CMS: Technology adopted for HCAL upgrade (QIE10 chip)
• Total radiation dose = 10 krad = 100 Gy
• Neutron fluence = 1013/cm2
• Charged hadron fluence = 2 x 1010/cm2
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Possible to share efforts on rad
qualification? Enginnering run? Cost…
Radiation tolerance should be taken into account at design:
ƒ Cumulative effects:
ƒ Use feedback (global or local): minimal impact of beta degradation
ƒ Not rely on absolute value of components, use ratios but
ƒ Transient events:
ƒ Guard rings for CMOS and substrate contacts: avoid SEL
ƒ Majority triple voting: SEU hardened logic (if any)
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V. Status and plans
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Prototyped in AMS :
ƒ
ƒ
ƒ
Low noise current amplifier:
Basic schemes
Integrator:
ƒ
ƒ
ƒ
High GBW fully differential OpAmp
Track and hold
Clock generation
See Edu’s talk
z
Channel will be final with:
ƒ
ƒ
ƒ
Analogue multiplexer
ADC driver
Tuneablility on gain, input
impedance and integration plateau
ƒ
ƒ
To compensate process variations
To cover different operation conditions
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BACK-UP
I. Introduction: voltage output versus current output
z
Voltage output:
ƒ Pros:
ƒ Tested
ƒ Cons:
ƒ I (PMT) -> V and V -> I
(integrate)
ƒ Larger supply voltage required
ƒ External components
ƒ 2 additional pads per channel
z
Current output (“à la PS”)
ƒ Pros:
ƒ “Natural” current processing
ƒ Lower supply voltage
ƒ All low impedance nodes:
ƒ Pickup rejection
ƒ No external components
ƒ No extra pad
ƒ Cons:
ƒ Trade-off in current mirrors:
linearity vs bandwidth
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II. Preamplifier: current output / mixed feedback
• Mixed mode feedback:
ƒ Inner loop: lower input impedance
ƒ Voltage feedback (gain): Q2 and Rc
ƒ Outer loop: control input impedance
ƒ Current feedback: mirrors and Rf
• Variation of LAr preamplifier
• Current gain: m
• Input impedance
Zi +
Vbe
+
Vbe
-
1 g m1 + Re
+ mR f
g m 2 Rc
• Problem:
ƒ Voltage feedback for the super common base needs 2 Vbe (about 1 .5 V !)
ƒ Small room for current mirrors with 3.3 V
ƒ Need cascode current mirrors
ƒ 5 V MOS available: but poor HF performance
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Possible alternative to delay line clipping or gaussian shaping
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Possible alternative to delay line clipping or gaussian shaping
IV. Technology issues: effect of process variations
z
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Input impedance is the key point
Two types of parameter variation simulated
ƒ Mismatch between closely placed devices (local variation component to component)
ƒ No problem: 1 % level
ƒ Process variation (lot to lot):
ƒ Problem: 10-30 % level !! (uniform distribution)
ƒ
z
Pessimistic: experience tell that usually production parameters are close to the typical mean values
In principle process variation affects whole production (1 run)
ƒ Could be compensated with an external resistor in series / parallel with the input
z
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Variation wafer-to-wafer or among distant chips in the same wafer:
ƒ Can not be simulated
ƒ Higher than mismatch and lower than process variation
ƒ According to previous experience: 2-3 % sigma: BUT NO WARRANTY
Should we foresee a way to compensate it?
ƒ Group (2-3) chips and:
ƒ Different pcb (2 – 3 different external resistor values
ƒ Tune a circuit parameter
ƒ Automatic tunning
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IV. Technology issues: effect of process variations
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Input impedance controllable by:
ƒ Tune feedback resistor Rf
ƒ Difficult: small value (Ron of the switch)
ƒ Tune second feedback current
ƒ Binary weighted ladder (3 bits?): simple
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How control current ladder control?
ƒ Group ASICs a fix the value, set by:
ƒ External jumper
ƒ Slow control: dig interface required
ƒ Automatic tunning
Vcc
Rext
ƒ Reference voltage
ƒ Reference currents: external or band gap
ƒ External resistor
+
Rint
Current
ladder
ƒ Wilkinson or SAR ADC style logic
Iref
Iref
n
Logic