High Voltage SwitchedSwitched-Mode
Power Supply for ThreeThree-Phase
AC Aircraft Systems
A Senior Project
Presented to
The Faculty of the Electrical Engineering Department
California Polytechnic State University, San Luis Obispo
In Partial Fulfillment
Of the Requirements for the Degree
Bachelor of Science
By
John Brewer, Jr.
And
Kamaljit Bagha
June, 2010
© 2010 John Brewer, Jr. and Kamaljit Bagha
ii
Table of Contents
Section
Page
Title Page
i
Table of Contents
ii
List of Table and Figures
iv
Acknowledgements
vi
I.
INTRODUCTION
1
II.
BACKGROUND
3
2.1
Predator® - Too Versatile For Its Own Good
3
III.
REQUIREMENTS
5
IV.
DESIGN
7
4.1
Inverter Project Design Overview
7
4.2
The Power Stage
10
4.3
The PWM Control Circuit and Signal Flow
17
4.4
The LC Output Filters
28
V.
CONSTRUCTION
32
5.1
PWM Control Circuit Assembly
32
5.2
Inductor Construction
33
5.3
Wire Harnesses, Connectors, and Cable Fabrication
35
5.4
Power Plane Construction
36
5.5
Enclosure Fabrication
36
iii
5.6
System Assembly
37
VI.
TESTING
38
VII.
CONCLUSION AND RECOMMENDATIONS
45
VIII.
BIBLIOGRAPHY
48
Appendices
A. Schematic
50
B. Bill of Materials
66
C. Circuit Board Layout
69
D. Circuit Board IC and Component Locations
70
E. Hardware Configuration and Layout
71
iv
List of Tables and Figures
Table
Page
3.1
MIL-STD-704F AC System Requirements [3]
5
3.2
Summary of Inverter Project Requirements
6
B.1
Bill of Materials and Donated Items
66
2.1
MQ-1 Predator Drone
3
2.2
MQ-9 Reaper Drone, originally named “Predator B”
4
4.1
IGBT Half-Bridge Configuration
7
4.2
Block Diagram of Inverter Project
9
4.3
Bootstrap Supply Topology with Protection
11
4.4
Nomenclature Used for IGBT Switching Transition
15
4.5
PWM Control Signal Flowchart
18
4.6
dsPIC-based Function Generator
19
4.7
Passive Component Nomenclature for UC3637…
21
4.8
Generating a Trigger Pulse
25
4.9
Bode Plot of Second Order LC Filter
28
5.1
Portion of Circuit Board Layout Graphic
32
5.2
Wire Wrapping
33
5.3
Inductor Bobbin
33
5.4
Tightly Wound Inductor
34
Figures
v
5.5
Wood Handle to Support Bobbin
34
5.6
Finished Inductor with Connectors and Mylar Tape
34
5.7
Fabricated Wire Harnesses
35
5.8
Top and Bottom Sides of Copper-Clad Board
36
5.9
Inverter System Assembly
37
6.1
Ideal Inverter Pspice Simulation
38
6.2
Output Voltage Waveform of Ideal Inverter Simulation
39
6.3
IGBT Gate Driver and Half-Bridge Pspice Simulation
39
6.4
High-side (green) and low-side (blue) IGBT…
40
6.5
Adjustable Three-Phase Sinusoidal Reference…
42
6.6
Trigger Pulse successfully generated by AD823AN…
42
6.7
Square wave with 97% duty cycle successfully generated…
43
6.8
Three-phase and Neutral-phase Duty Cycle limited…
43
6.9
Three-phase Inverter Output Voltage referenced…
44
6.10
Three-phase Inverter Output Voltage referenced…
44
C.1
Microsoft PowerPoint Circuit Board Layout
69
D.1
IC and Component Circuit Board Location
70
E.1
Hardware Configuration and Layout
71
E.2
Test Bench Setup
72
Acknowledgements
Acknowledgements
We would like to thank –
Mr. John (Jeff) Brewer, Director of Electrical Engineering for the Aircraft
Systems Group at General Atomics Aeronautical Systems, Inc. for providing and
funding a challenging project for us to work on and offering the technical support
needed to complete this project. We appreciate him sharing his knowledge and
insight of the broad range of topics that this project covers and have been inspired
to work hard and never stop learning as electrical engineers.
Dr. Taufik, Professor of Electrical Engineering at California Polytechnic State
University, San Luis Obispo, as our faculty advisor for this project. His dedication
and excellence as a teacher both in the classroom and lab have equipped us with a
solid foundation of knowledge and understanding in the field of power electronics.
His teaching curriculum and techniques significantly contributed to our ability to
“Learn by Doing” here at Cal Poly.
Mr. Jaime Carmo, Cal Poly EE Department Electronics Technician, for his
support and generous donation of time, equipment, and parts throughout the
construction, testing, and fabrication stages of our project.
Mr. Cole Brooks, Cal Poly mechanical engineer and friend, for his assistance
in metal parts fabrication
Our families for supporting our educational endeavors.
Sincerely,
John Brewer, Jr. and Kamaljit Bagha
1
I.
INTRODUCTION
With the advent of the first power rectifier by an American engineer and
applied physicist, Robert Hall, in 1952, a new form of power control and conversion
was born – Power Electronics. The successive arrival of thyristors in 1957, bipolar
transistors in the 1960s, power MOSFETs in the late 1970s, and IGBTs in the 1980s
led to the rapid advancement of power electronics in all fields of electrical
engineering [1]. These fields include utility power distribution, industrial electronics,
and especially aircraft electronics because of the small size of power electronic
components. A few applications of power electronics in these fields include power
quality controllers, variable speed drives, and power supplies.
Power electronics is unique in its method of power control and conversion in
that it is based on the switching fully-on and fully-off of semiconductor devices to
regulate power flow. More efficient than linear power regulation which uses
variable resistance to regulate power flow, switching semiconductor devices by
using a technique called “Pulse Width Modulation (PWM)” is the method used in a
modern “switching” or “switched-mode” power supply (SMPS). PWM is a technique
where the duty cycle of the semiconductor switch is manipulated to control power
flow through the switch. As a result, the output voltage delivered to the load can be
2
well regulated to produce a fixed Direct Current (DC) voltage or a desired Alternating
Current (AC) voltage.
There are two types of converter topologies used in SMPS design – isolated
and non-isolated. Transformers are used in the design of isolated converters to
provide flexibility in circuit design by allowing for separate (isolated) input and
output current return paths to “ground.” Non-isolated converters, however, do not
use transformers and the input current ground is used as the ground for the output
load current.
For our application, we have designed a non-isolated SMPS that produces AC
output voltage from DC input voltage – this is known as a DC/AC converter or,
simply, an inverter. It uses the common method of Pulse Width Modulation to
switch Insulated Gate Bipolar Transistors (IGBTs) to control the flow of power from
±DC input voltage “rails” to three-phase, sinusoidal AC output voltage. In the next
section of this report, we will present the background and application of our inverter
design.
3
II.
BACKGROUND
Our three-phase, sinusoidal inverter project was sponsored by Jeff Brewer,
the Director of Electrical Engineering at General Atomics Aeronautical Systems, Inc.
(GA-ASI). The purpose of this project was to design and build a proof-of-concept
high-power switched-mode inverter. This project began the development process
for a high-voltage three-phase AC power supply for use on any of the Predator®
Unmanned Aircraft Systems (UAS) that GA-ASI manufactures.
2.1
Predator® – Too Versatile For Its Own Good
Predator® aircraft like the ones shown in Figure 2.1 and Figure 2.2 are used
by multiple branches of the United States’ military and homeland security including
the Air Force, Army, U.S. Customs and Border Protection, Central Intelligence
Agency, and NASA. They are popular for their wide range of applications including
remote sensing, reconnaissance, weapons delivery, search and rescue, and
surveillance. Predator® systems are versatile
aircraft platforms upon which an increasingly
large array of electronic device payloads like
sensors, weapons, and communications
equipment can be mounted.
Fig. 2.1 – MQ-1 Predator Drone
Source: Public Domain
4
Currently, these devices are powered by 28 VDC power on the aircraft – one of three
standard aircraft power systems prescribed by MIL-STD-704F [3]. Because these
aircraft are required to support an increasing number of electronic payloads, the
weight of the cables in the aircraft needed to deliver 28 VDC power to these
payloads exceeds practicality. So, to counteract this problem, plans to provide highvoltage power systems in accordance with MIL-STD-704F on Predator® aircraft are in
effect. It is estimated that the cable weight required to distribute power on the
aircraft will be reduced by a factor of ten when high-voltage power is provided [2].
These plans include the provision of a 270VDC system and a three-phase AC system
as outlined in the next section of this report.
Fig. 2.2 – MQ-9 Reaper Drone, originally named “Predator B”
Source: Public Domain
5
III.
REQUIRE
REQUIREMENTS
The purpose of our project was to design and build a non-isolated DC/AC
SMPS capable of supplying 10 kW for a standard three-phase AC aircraft power
system. According to MIL-STD-704F,
“AC systems shall provide electrical power using single-phase or three-phase
wire-connected grounded neutral systems. The voltage waveform shall be a
sine wave with a nominal voltage of 115/200 volts [115 VRMS] and a nominal
frequency of 400 Hz” [3].
Because MIL-STD-704F also prescribes AC system requirements like the
sample shown in Table 3.1, the production level version of our inverter will require
the use of closed-loop feedback to provide adequate line and load regulation.
However, designing a closed-loop system was beyond the scope of this project, so
an open-loop system was required.
Table 3.1 – MIL-STD-704F AC System Requirements [3]
Characteristics
Steady State Voltage:
Limits
108.0 VRMS to 118.0 VRMS
Voltage Unbalance:
3.0 VRMS (maximum)
Voltage Modulation:
2.5 VRMS (maximum)
DC Component:
Voltage Phase Difference:
Steady State Frequency:
Frequency Modulation:
Peak Voltage:
+0.1 to -0.1 Volts
116° to 124°
393 Hz to 407 Hz
4 Hz
±271.8 Volts
6
Lastly, the production level version of our inverter will be powered by the
engine alternator on the aircraft. The three-phase, variable voltage, variable
frequency engine alternator power will be rectified and regulated to produce
±190 VDC rails from which the inverter will draw its power [2]. Since this
rectification and regulation of engine alternator power is beyond the scope of this
project, it was required that our proof-of-concept inverter work from ±125 VDC rails
for three-phase operation given 10Ω resistive loads. This requirement was limited
by the available test equipment in Cal Poly’s EE Department Power Electronics Lab.
The nominal requirements of our inverter project are summarized below in
Table 3.2. In the following section of this report, we will present a system overview
of our inverter project followed by a more detailed discussion of the circuit design
process.
Table 3.2 – Summary of Inverter Project Requirements
Nominal System Requirements
Converter Topology:
Input Voltage:
Output Voltage:
Output Voltage Waveform:
Non-Isolated SMPS
±125 VDC
85 VRMS AC
Three-Phase, Sinusoidal
Steady State Frequency:
400 Hz
Maximum Output Power:
10 kW
7
IV.
DESIGN
This section of our report represents a majority of the work that went into
this project – circuit design. In this section, we will present an overview of our
inverter project followed by a series of discussions covering the details of the circuit
design, signal flow, and discrete components used.
4.1
Inverter Project Design Overview
The design of our three-phase sinusoidal inverter is based on the PWM
switching of N-Channel IGBTs connected in a half-bridge configuration as shown in
Figure 4.1. As the high-side and low-side IGBTs are complementarily switched fullyon and fully-off, they connect the load to the
+DC and -DC Rails, respectively. Since the
output is connected to one of two voltage
polarities during this method of switching, it is
known as Bipolar Switching. Because the
output voltage is effectively an amplified
version of the PWM Control Input, this stage of
the inverter system can be considered the
Fig. 4.1 – IGBT Half-Bridge Configuration
Source: John Brewer, Jr.
Power Amplification stage and is shown in the System Block Diagram in Figure 4.2.
8
The IGBT Gate Drivers and Floating Bootstrap Supply topology required to drive
N-Channel IGBTs in this configuration are also indicated in Figure 4.2 and will be
discussed in Section 4.2.1.
The PWM Control Input is generated by the PWM Control Circuit block. The
PWM Control Circuitry is responsible for generating the sinusoidal reference
waveforms, establishing the switching frequency, creating PWM signals, limiting the
duty cycle of the PWM signals, and interfacing logic-levels. A thorough discussion of
the PWM Control Circuitry will be presented in Section 4.2.2 of this report.
The final piece of our inverter design is the inductor/capacitor (LC) output
filters on each phase. The LC output filters were designed to smooth the PWM
output of the Power stage and filter out high-frequency harmonics introduced by
IGBT switching. These will be discussed in Section 4.2.3.
An important characteristic to note about our inverter design is the fourth
IGBT Half-Bridge “leg” which is used to create a virtual ground (neutral) through
which phase currents from an unbalanced three-phase load can return to the DC
input supply. The PWM Control Input to this neutral leg will have a nominal 50%
duty cycle, creating a voltage that is one-half the DC supply voltage upon which the
three-phase sinusoidal output voltages will be centered. The creation of this neutral
return is necessary in the case that a bipolar DC supply with ground connection is
unavailable and a unipolar DC supply must be used.
Fig. 4.2 – Block Diagram of Inverter Project
Source: John Brewer, Jr. and Kamaljit Bagha
9
10
4.2
The Power Stage
As mentioned in Section 4.1, the Power Stage consists of two IGBTs
connected in a Half-Bridge configuration. Four identical half-bridge legs form the
foundation of our three-phase inverter and are responsible for controlling power
flow from the DC Input Supply to each phase output voltage – Phase A, Phase B,
Phase C, and Neutral.
Jeff Brewer donated the IGBTs that were to be used for this project –
IRGP50B60PD1, WARP2 Series IGBT with Ultrafast Soft Recovery Diode from
International Rectifier (IR). These IGBTs are high-speed, high-power, SMPS,
N-Channel IGBTs capable of withstanding a collector-to-emitter voltage of 600V.
Driven with a gate-to-emitter voltage of 15V, these IGBTs can source 33A with
maximum turn-on and turn-off delay times of 40ns and 150ns, respectively [4]. With
an operational output voltage of 115VRMS, the resulting power output capability of
all three inverter phases combined can then be calculated to be:
= 3 ∗ ∗ (Eq. 4-1)
∴ = 3 ∗ 33 ∗ 115 = 11.385
In conclusion, using these IGBTs will fulfill our requirement to design a threephase inverter capable of supplying 10kW with an output voltage of 115VRMS. In the
next section, we will discuss the floating bootstrap supply topology required for
11
switching N-Channel devices, the IGBT Gate Driver design process, and design
measures taken to protect the IGBTs.
4.2.1 Bootstrapping, IGBT Gate Drivers, and Transient Voltage Protection
N-Channel semiconductor devices are commonly used in half-bridge
configurations as our IGBTs are used in the power stage of our inverter. However,
these N-channel devices require a charge applied to the gate that is positive with
respect to the emitter such that (VGE > VTH). While this does not present a problem
for turning on low-side devices with a power supply referenced to the –DC rail, the
same supply would be unable to turn on the corresponding high-side device as the
high-side emitter follows the output voltage of the half-bridge – a much larger
voltage than the supply voltage. Therefore, a bootstrap supply topology is required.
As illustrated by the schematic of a typical bootstrap supply topology in
Figure 4.3, a bootstrap capacitor is connected from the power supply, VCC, to the
high-side emitter. Due to
the charge storage
characteristics of a
capacitor, the bootstrap
capacitor voltage will rise
+VCC above the high-side
emitter, providing the
Fig. 4.3 – Bootstrap Supply Topology with Protection
Source: John Brewer, Jr.
12
necessary gate drive voltage to turn on the high-side device. When an internal
switch in the Gate Driver Integrated Circuit (IC) connects node VB to the high-side
gate, the high-side device will turn on. It will then turn off when the gate is
disconnected from VB and connected to VS by internal switches in the Gate Driver IC.
However, the high-side device will also turn off if the charge on the bootstrap
capacitor is depleted due to parasitic gate current. Because of this, the duty cycle of
the high-side device switching must be limited and the bootstrap capacitor sized
accordingly to prevent premature/uncontrolled turn-off of the high-side device.
For our project, we decided to use the Si8234BB ISOdriver manufactured by
Silicon Labs as our High-Voltage Integrated Circuit (HVIC) Gate Driver. This recently
released HVIC Gate Driver contains two completely isolated high-side/low-side
drivers in one package that are each capable of sourcing 4.0A peak output current.
The isolated drivers are controlled by a single PWM Control Input signal and an
external resistor used to program the deadtime created between the switching of
the high-side and low-side devices. The input logic side of the device is 5V TTL
compatible, while the output side can support the 15V supply used to switch our
IGBTs. Also note that we have incorporated the Disable pin of the Si8234BB device
into our circuit design to provide the functionality of being able to turn combinations
of our phase output voltages on or off [5].
We consulted IR’s “Design Tips for Using Monolithic High Voltage Gate
Drivers” during the design process for our HVIC gate drivers and floating bootstrap
13
supply [6]. To size the bootstrap capacitor, we started by calculating the maximum
voltage that the bootstrap capacitor voltage was allowed to drop (∆VBS) when the
high-side IGBT was supposed to be on. To do this, we decided from Fig. 8 of our
IGBT datasheet that the minimum gate-to-emitter voltage to allow should be 11V in
order to guarantee a collector-to-emitter voltage of about 2V given a collector-toemitter current around 33A. Also, we used a value of 1V for the typical forward
voltage drop of the MUR460 power rectifier used to protect VCC as shown in
Figure 4.3 [7]. As a result, we obtain
∆ = − − , − ,
(Eq. 4-2)
∴ ∆ = 15 − 1 − 11 − 2 ≅ 1
We then confirm that VGE,min > VBSUV- where VBSUV- is the high-side supply
undervoltage negative going threshold of 8.10V as indicated in Table 1 of the
“Si823x” datasheet from Silicon Labs [5].
The next step in sizing the bootstrap capacitor was to consider the following
factors contributing to a decrease in VBS:
- IGBT turn-on required Gate charge (QG) =
308nC (max)
[4]
- IGBT Gate-Emitter leakage current (IGES) =
100nA
[4]
- Output supply quiescent current (IDDAQ) = 3.0mA (max)
[5]
- Bootstrap diode instantaneous reverse current (ILK_D) = 50μA
[7]
- Bootstrap capacitor leakage current (ILK_C) =
- High-side on time (TH,on) =
24.5μs
0μA
(use ceramic capacitors)
(98% duty cycle at 40kHz)
14
Then we have
#$% = # + ' + (() + %*_, + %*_ - ∗ ./,
(Eq. 4-3)
∴ #$% = 30812 + 31001 + 3.04 + 505 + 056 ∗ 24.558 ≅ 38312
And the minimum size of the bootstrap capacitor can be calculated by
2, =
)9:9;<
(Eq. 4-4)
∆=>?
∴ 2, =
@A@
B=
≅ 3831C
So, to account for estimation error and temperature drift, we decided to use a
bootstrap capacitance of 660nF, almost twice as big as the calculated CBOOT,min. As
mentioned earlier, MUR460 power rectifiers are an ideal choice for use as the
bootstrap diode in our bootstrap supply design. These devices were also donated to
our project and can withstand a reverse voltage of 600V and have a reverse recovery
time of less than 100ns [7].
The final design issues to be mentioned regarding the design of the IGBT gate
drivers are the addition of decoupling capacitors, sizing of gate resistances, and
measures taken for protecting the IGBTs and HVIC Gate Drivers. Sufficient
decoupling capacitance was added to our gate driver design by placing ceramic and
electrolytic capacitors in parallel with the gate drive supply voltage very close to
both the low-side Gate Driver output pins and the bootstrap diode. The ceramic
capacitor provides a fast charge tank and limits
DF
DE by reducing the equivalent
series resistance while the electrolytic provides a longer lasting charge tank.
15
The process for sizing the gate resistances consisted of both calculations to
derive ballpark figures and hardware experimentation. From “Design Tips for Using
Monolithic High Voltage Gate Drivers,” we can estimate the necessary size of the
turn-on gate resistor by fixing the switching-time. As shown in Figure 4.4, the
switching time is defined
as the time spent to
reach the end of the
plateau voltage resulting
from charging the IGBT
gate capacitances with
QGC and QGE. Estimating
Fig. 4.4 – Nomenclature Used for IGBT Switching Transition
Source: International Rectifier [6]
an appropriate switching time to be about 115ns and knowing QGC and QGE to be
105nC and 45nC, respectively, we can calculate
$=$ =
)GH I)GJ
∴ $=$ =
(Eq. 4-5)
KLM
BNOIPO
BBOQ
≅ 1.3
And
R$% =HH T =UV (Eq. 4-6)
W;XJY;GJ
where Vge* is approximated to be 6.2V from Fig. 17 of our IGBT datasheet [4], and
R$% RZ3Q
[\]^6
& R,
(Eq. 4-7)
16
Where RON(source) is 2.7Ω according to the Si8234BB datasheet, and RG,on is the value
for the high-side IGBT gate resistor [5]. As a result, we have
R,
=
BO=T_.`=
B.@$
− 2.7Ω ≅ 4Ω
And following IR’s Design Tip, we size the low-side IGBT gate resistor to be larger
than the gate resistor of the high-side device – about 5Ω. This will result in softer
switching of the low-side device and a reduction in magnitude of the voltage
transients caused by parasitic inductances during switching.
Lastly, the design of the Power stage includes devices added to protect IGBTs
and HVIC Gate Drivers from transient voltage spikes caused by parasitic inductances
in the circuit. First, Zener clamp diodes with a reverse voltage breakdown voltage of
16V are added across the gate-to-emitter junctions of both high-side and low-side
devices. Shown in Figure 4.3, these Zener clamps protect the HVIC Gate Driver
output, sink current generated by transient voltage spikes occurring on the collector,
and keep the IGBT gate-to-emitter voltage from exceeding the maximum limit of
20V [4]. Another clamp device used is the series combination of a 16V Zener diode
and MUR460 Power Rectifier positioned between the VS pin of the HVIC Gate Driver
and the –DC rail also shown in Figure 4.3. The purpose of this clamp device is to
guarantee that VS does not exceed maximum undervoltage limits when negative
voltage transient spikes are induced by parasitic inductances. The production level
version of our inverter will include the placement of reverse-biased transient voltage
17
suppression diodes with a reverse breakdown voltage <600V across the collector-toemitter IGBT terminals. These will protect the IGBTs from damage caused by voltage
transients on the DC supply rails or half-bridge output node. Due to the DC input
supply test limits, we omitted these diodes from our proof-of-concept design.
The circuit schematics for the four Power Stages of our inverter design can be
found on Sheets 11, 12, 13, and 14 of the system schematic in the Appendices. In
the next section of this report, we will discuss the PWM Control Circuit and signal
flow.
4.3
The PWM Control Circuit and Signal Flow
The PWM Control Circuit is the “brain” of our inverter project and is
responsible for generating our three-phase sinusoidal reference signals, producing
PWM Control signals for all three-phases and neutral, limiting the duty cycle of the
PWM Control signals, and interfacing logic levels. It was designed using discrete
analog components with the exception of a Microchip dsPIC 16-bit Digital Signal
Controller-based function generator. Considerations for choosing the discrete
analog devices we used included availability, ease of prototype implementation,
proven reliability, low replacement cost, and extreme temperature tolerance for
military temperature requirements.
18
In this section of the report, we will present a discussion of the circuit
components used to perform these tasks and cover the details of the circuit design
required to interface these components and generate PWM Control Input signals for
the HVIC Gate Driver of each IGBT half-bridge. Figure 4.5 illustrates the general flow
of a single phase PWM Control signal.
Fig. 4.5 – PWM Control Signal Flowchart
Source: John Brewer, Jr.
19
4.3.1 Generating Three-Phase Sinusoidal Reference Signals
The first step in the design of the PWM Control Circuit was to generate three
sinusoidal reference voltages, each having 120° of phase displacement from the
others. Fortunately, this step was already complete before we began our project.
Manufactured and donated by GA-ASI, the Microchip dsPIC Digital Signal ControllerBased Function Generator shown in Figure 4.6 supplies three-phase sinusoidal
waveforms with accurate sine shape and phase displacement. The frequency and
amplitude of the output sinusoids
are adjustable, but for our
application they are set to have a
frequency of 400 Hz and peak-topeak amplitude of 2V.
In order to make the
amplitude of our inverter output
Fig. 4.6 – dsPIC-based Function Generator
voltage waveforms adjustable,
Source: John Brewer, Jr.
remove the DC offset from the reference sinusoids, and buffer the reference
sinusoids, we AC coupled each of the sinusoidal phase voltages from the function
generator to adjustable gain, non-inverting amplifiers designed using TL082 JFET
Input Op-Amps. Simple RC highpass filters with a cutoff frequency of 1 Hz were used
for the AC coupling. The TL082 op-amps were chosen because of their suitable slew
rate of 13V/μs, low Total Harmonic Distortion of 0.003%, ability to operate from
20
±15V supplies, and compact 8-pin packages containing two op-amps each. The
circuit schematic for this step in the PWM Control Circuit can be located on Sheet 3
of the system schematic in the Appendices.
4.3.2 Generating PWM Signals from Reference Sinusoids
The next step in the design of the PWM Control Circuit was to generate the
PWM Control signals for each phase including neutral by comparing the reference
sinusoids to a triangle wave having a frequency equal to the desired IGBT switching
frequency. Using a PWM Controller IC is the most efficient way to do this, so we
chose the Unitrode UC3637 Switched-Mode PWM Controller for DC Motor Drives.
The UC3637 was chosen because of its high reliability, robustness, and
widespread use in industry. It is easy to program and provides a built in error
amplifier, under-voltage lockout, and can operate from dual power supplies [8].
Concurrently, multiple UC3637 ICs can be readily synchronized according to
Unitrode’s Design Note about “Design Considerations for Synchronizing Multiple
UC3637 PWMs” [9]. This was an important quality of the UC3637 since four PWM
Controller ICs were required in the PWM Control Circuit and the ability to
synchronize them would simplify circuit construction.
We arbitrarily decided to establish the Neutral phase PWM Controller as the
Master PWM device. This IC was “programmed” with the passive components
shown in Figure 4.7 according to the following design requirements:
21
•
Triangle Wave frequency of 40kHz (same as the IGBT switching frequency).
•
Triangle wave amplitude of 20 VP-P (large to increase noise immunity).
•
Modulation scheme with no deadtime (since the Si8234BB IGBT Gate Driver
supplies the necessary high-side/low-side switching deadtime).
•
Under-voltage lockout level of 10.75V (to prevent switching IGBTs when
there is not enough supply voltage to fully turn them on).
Fig. 4.7 – Passive Component Nomenclature for UC3637
Master Device Programming
Source: John Brewer, Jr.
Consulting the Unitrode UC3637 Datasheet and following the Unitrode
Application Note U-102, we calculated the following [8] [10]:
R 3I=9c 6T3T=? 6
∴ R (4-8)
W?
3IBN =6T3T BO =6
N.O$
= 50Ω ≅ 47.5Ω
22
2 W?
`de3I=9c 6T3T=9c 6f
(4-9)
N.O$
∴ 2 `∗PNg/h∗e3IBN =6T3TBN =6f = 313iC ≅ 300 iC
For clarity, we note that the Unitrode Application Note U-102 suggests that the
constant current used to charge the external capacitor, CT, be within the range of 0.3
to 0.5 mA. Because the amplitude of the triangle wave has been designed fairly
large, we programmed ISET to a value on the higher end of this range, 0.5 mA, as
used in Eq. 4-9. Using this higher charging current performs a secondary feature of
allowing the use of a larger capacitor, CT, that will be able to store enough charge to
drive the input of a TL082 op-amp configured as a voltage-follower. This will
produce a buffered triangle wave used to drive the UC3637 slave devices and the
AD823AN op-amp used for generating a trigger pulse for the HCF4538B Monostable
Multivibrator
Since +VTH and -VTH should be symmetrical at ±10V in our application, we set
R1 = R5 and calculate REQ (where REQ = R2 + R3 + R4) after choosing reasonable values
for R1 and R5. Using an iterative process to determine values for R1 and R5, we
•
Calculated REQ
•
Calculated the approximate bias current, IBIAS, through the resistor
divider created by R1, REQ, and R5 between +VS and -VS.
•
Adjusted values accordingly to limit the bias current to an order of
hundreds of microamps. This prevented unnecessary power loss while
23
maintaining the ability to adequately charge the PWM controller
comparator inputs.
As a result,
RB RO 20.4Ω
R) =
` ∗ j ∗ =9c
(4-10)
=? T =9c
∴ R) =
` ∗ `N,PNNk ∗ BN=
BO= T BN=
= 81,600 Ω
We also needed to ensure that the +VSLV node voltage indicated in Figure 4.7
was always less than the magnitude of the triangle wave despite any drift in
resistance, the UC3637 Master PWM device characteristics, or the AD823AN op-amp
characteristics. This will guarantee the generation of a trigger signal for the
HCF4538B Monostable Multivibrator which is used to create a square wave with
frequency equal to the triangle wave and duty cycle of 98%. In order to do this, we
needed to determine the minimum voltage difference, ∆Vmin, required between +VTH
and +VSLV. Following the procedure outlined in Unitrode Design Note DN-53A, we
determined ∆Vmin to be about 1.5V, requiring a ballpark resistance for R2 and R4 to
be 6.3kΩ [9]. However, based upon the hardware available during the construction
phase of our project,
R` = RP = 5.62Ω
and
R@ = 68.1Ω
Yielding
W$ =
I=? T3T=? 6
m In Ij Io Ip
(4-11)
24
IBO= T 3TBO=6
∴ W$ `N,PNNk I O,_`Nk I _A,BNNk I O,_`Nk I `N,PNNk ≅ 2505
Lastly, we used the equation provided in the UC3637 IC datasheet to
establish an undervoltage lockout level of 10.75V. Using a 100kΩ resistor for R6, we
calculated
$ =
∴ Rs =
=?9;Y9 ∗ q
`.O
− R_ =
`.O∗3q Ir 6
q
BN.sO=∗BNNgk
`.O
(4-12)
− 100Ω = 330Ω
At this point, the simplicity of synchronizing the other three UC3637 slave
devices becomes evident. Besides adding 0.1μF decoupling capacitors to all device
pins that are tied to a fixed voltage, we simply connect the +VSLV node to the +VTH
slave device pins, the –VSLV node to the –VTH slave device pins, the SD pin of the
master device to the SD pins of the slave devices, and the buffered triangle wave
output from the TL082 voltage-follower to pins 2, 8, and 10 of the slave PWM
devices.
The -15V low/+15V high PWM Control Input signals are each interfaced with
their respective 74AC00 CMOS NAND Gates by a current limiting resistor/voltage
divider/Schottky diode network that reduces the signal to 0.4V low/+5V high.
In the next sections of this report, we will discuss the portions of the PWM
Control Circuit that limits the duty cycle of the PWM Control Inputs to 98%.
25
4.3.3 Generating a Trigger Pulse
As mentioned in the previous section, our PWM Control Circuit design
includes the use of an AD823AN rail-to-rail FET Input op-amp as a comparator.
According to the AD823AN datasheet, this op-amp has a high slew rate of 22V/μs
and can operate from ±15V supplies [11]. As a result, this op-amp provides the
speed needed for a short switching transition time and required no voltage level
shifting to interface the ±20V buffered triangle wave. Although the AD823AN is a
dual op-amp package, only one of the op-amps is needed by our control circuit.
With the buffered triangle wave tied to the positive input and the +VSLV
voltage tied to the negative input of the comparator, a +15V pulse with duration of
about 1μs is generated when the triangle wave is at its peak and exceeds the +VSLV
threshold as illustrated in Figure 4.8.
This -15V low/+15V high trigger pulse
is interfaced with the HCF4538B
Monostable Multivibrator through a
current limiting resistor and Schottky
diode network that reduce the trigger
Fig. 4.8 – Generating a Trigger Pulse
pulse to a 0.4V low / +15V high pulse.
Source: John Brewer, Jr.
4.3.4 Monostable Multivibrator
After being triggered by the trigger pulse delivered by the AD823AN
comparator, the HCF4538B Monostable Multivibrator configured as a non-
26
retriggerable one-shot generates a 24.5μs pulse. Since the trigger pulse is delivered
every 25μs, the equivalent waveform produced is a 40kHz square wave with a duty
cycle of 98%. This 0V low/15V high signal is interfaced with the 74AC00 CMOS
NAND Gates through a simple resistor divider reducing it to a 0V low/+5V high
signal. The timing equations and wiring configuration for a non-retriggerable oneshot design were given by the HCF4538B datasheet [12]. As illustrated in our
schematic (See Appendix) we paired a 5,600pF timing capacitor, C38, with a 10kΩ
potentiometer, R22, so we could adjust the output pulse of width, T, according to the
equation
. R`` 2@A
(4-13)
`P.OuQ
∴ R`` O,_NNv = 4.375Ω
jt
4.3.5 High-speed CMOS NAND Gates
The 74AC00 CMOS NAND Gates used in our PWM Control Circuit provide the
logical AND function needed to limit the duty cycle of the PWM Control Input signals
to 98% [13]. By “ANDing” the PWM Control input signal for each phase of our
inverter with the square wave output by the One-Shot, the duty cycle of the PWM
Control Input signals are effectively limited to 98%. This provides the high-side IGBT
off-time necessary for recharging the bootstrap capacitor as discussed in Section
4.2.1.
27
4.3.6 Supplying Power to the PWM Control Circuit and Bootstrap Supply
After having figured out how to drive our inverter IGBTs and design the PWM
Control Circuit, we needed to figure out how to supply power to the low-voltage side
of our project. Since the function generator donated to our project by GA-ASI came
with its own power supply, we only needed to supply +15 VDC, -15 VDC, and +5 VDC
to our circuit. For these voltages, we bought two 15V and one 5V isolated AC/DC
wall adapters – the first two sold as “Notebook Adapters” and the latter as an
“Internet Router Adapter.” Since these adapters are isolated, we were able to
reference our PWM Control Circuit DC Bias Supply voltages to the most negative
voltage used for the DC Input Supply to our inverter – a requirement for properly
driving our Half-Bridge IGBT topology with a Bootstrap Supply.
4.3.7 Using Decoupling Capacitors
As we complete our discussion of the PWM Control Circuit, it is important to
note the use of decoupling capacitors throughout our circuit design. The use of
0.1μF ceramic capacitors tied between logic ground and any IC pin connected to a
bias voltage provides sufficient AC decoupling and noise immunity. It is also
important to note the use of sufficiently larg electrolytic bias supply capacitors
located at the circuit board D-sub connector where the power is delivered to the
board.
28
4.4
The LC Output Filters
The design process for our inverter project included the design of three
Second-Order LC filters to be used for smoothing the output voltage waveforms for
each phase of our inverter. The design of these LC output filters was based on the
400Hz output voltage frequency and the 40kHz PWM switching frequency. As
illustrated by the Bode plot in
Figure 4.9, we designed the LC
output filter to have a corner
frequency of 2kHz so it would
effectively pass the 400Hz
voltage waveform while
sufficiently attenuating the 40kHz
PWM switching frequencies. We
also designed the LC filter to have
a low output impedance of 2Ω.
Fig. 4.9 – Bode Plot of Second Order LC Filter
Source: John Brewer, Jr.
Therefore, using
L = 159μH and C = 40μF,
w B
(4-14)
`x√%
∴w B
`xzBO{u/PNu
1,995}~ " 2}~
29
And,
 €
%
(4-15)
BO{u/
∴  € PNu 1.99Ω ≅ 2Ω
4.4.1 Inductor Design
During the design process of the inductors for our inverter, we received
some much needed help from Jeff Brewer [2]. The most significant factor in the
inductor design process was the desired inductance and maximum amount of
current that would flow through an inductor during inverter operation.
Although the nominal output current of each inverter phase is 33A, we
designed the inductors for our inverter to be able to carry up to 50A. Based on the
equation for energy stored in an inductor, we needed to design inductors that could
each store
B
% = ‚ƒ `
(4-16)
`
∴ QK
\^„
B
= ∗ 1595} ∗ 3506` = 0.19875 …†‡ˆ‰8
`
Then using
Š =
`∗L‹ŒVŽ ∗BNo
∴ Š =
where
AP =
area product in cm4.
(4-17)
‘ ∗*’ ∗*“
`∗N.B{AsO∗BNo
ONNN∗P_A∗N.O
= 34.2 ”4P
30
Kj =
the current density coefficient for a given core and a given
temperature rise.
Ku =
the cross sectional area of copper to the total window area or packing
factor.
Bmax = the maximum flux density in Gauss.
from selecting an AMCC-50, size 10, PowerLite C-Core [2] [14] [15]. These PowerLite
cut C-cores are made out of Metglas iron alloy material and will not only make our
inductors easy to fabricate but also allow for fine tuning of inductance by adjusting
the air gap and using an Impedance Bridge
To determine the minimum number of turns, Nmin, and the length of air gap,
Lgap, needed in each leg of the cut C-core inductor, we used
• %W–H,‘ ∗BNt
(4-18)
‘ ∗$U—
∴ • =
BO{u/∗ON$∗BNt
O,NNN∗@.`]n
= 49 E‡˜18
where
L=
Inductance of the inductor in microHenries.
IDC,max =
Maximum current through the inductor in Amps.
Agap =
Total cross sectional area of the air gap including fringing.
And
‚™šv =
.`∗x∗$U— ∗BN›n ∗Zn
∴ ‚™šv =
%
.`∗x∗@.`]n ∗BN›n ∗P{n
BO{u/
(4-19)
= 0.304 ƒ1”ℎ‰8.
31
Lastly, we determined that although making an inductor by wrapping
insulated Copper Foil around a Ferrite Core would result in lower core losses for the
beneficial design tradeoff of higher copper loss, it would be hard to fabricate for a
prototype. So, we chose 10AWG magnet wire with a heavy insulation build for
withstanding temperatures up to 200°C to wrap our AMCC-50 cores with [16]. We
were able to successfully wrap our inductor bobbins with 49 turns and connect two
bobbins in parallel, one on each inductor leg, for a generous inductor current
capacity of 50A.
In the next section of this report, we will discuss the construction phase of
our inverter project.
32
V.
CONSTRUCTION
The construction and assembly phase of our proof-of-concept inverter
project consisted of six main parts – PWM Control Circuit assembly, Inductor
construction, Wire Harnesses, Connectors, and Cable fabrication, Power Plane
construction, Enclosure fabrication, and System assembly.
5.1
PWM Control Circuit Assembly
Before starting construction of the PWM Control Circuit, we used Windows
Paint to create scale drawings of our perforated circuit board (PerfBoard),
components, and ICs. We then copied these scale drawings into Microsoft
PowerPoint where we were then
able to freely move, place, label, and
“wire” components according to our
circuit design. Figure 5.1 shows a
part of our Circuit Board Layout.
To make connections on our
circuit board, we used a combination
Fig. 5.1 – Portion of Circuit Board Layout Graphic
of soldering and wire wrapping;
Source: John Brewer, Jr.
however, soldering was only used to solder short connections like decoupling
capacitors to IC pins while wire wrapping constitutes a majority of our connections.
33
A common prototype technique, wire wrapping uses a wire wrap tool to tightly wrap
30AWG Kynar wire around special wire wrap “posts.”
Using two PerfBoards, one on top of the other, provides a
much stronger circuit board to work with and helps keep
wire wrap posts straight. Figure 5.2 illustrates this
technique. For our proof-of-concept prototype, the design
and fabrication of a Printed Circuit Board (PCB) would not
have been cost effective and would have made circuit
Fig. 5.2 – Wire Wrapping
Source: John Brewer, Jr.
modifications difficult.
5.2
Inductor Construction
To construct the inductors, we needed to wrap 10AWG enameled wire 49
times around the inductor bobbins shown in Figure 5.3. As shown in Figure 5.4, we
needed to guarantee that the wire was wrapped very tightly around each bobbin so
that two bobbins would fit on one core. In
order to prevent cracking a bobbin during
the wrapping process, Jeff Brewer
fabricated the wood handle shown in
Figure 5.5 to fit snugly inside each bobbin
as it was wound.
Fig. 5.3 – Inductor Bobbin
Source: John Brewer, Jr.
34
When it was time to put two wire-wrapped
bobbins on a core, we used the right-hand-rule to
determine the orientation of the bobbins on the
core to guarantee that the flux induced by the
coiled wire on each bobbin was flowing through
Fig. 5.4 – Tightly Wound Inductor
the core in the same direction. Using an
Source: John Brewer, Jr.
Impedance Bridge, we adjusted the air gap of
each inductor to obtain our desired inductance at 2kHz – 159μH. We then used
small squares of PerfBoard as spacers inside the bobbins between the core halves to
maintain the necessary air
gap of each inductor.
Fig. 5.5 – Wood Handle to Support Bobbin
Using a sharp edge,
Source: John Brewer, Jr.
we scraped about an inch of enamel coating from each end of the wires to be
connected. Lastly, we crimped and soldered them to a connector and wrapped up
the inductor using hightemperature Mylar tape
as shown in Figure 5.6.
Fig. 5.6 – Finished Inductor with Connectors and Mylar Tape
Source: John Brewer, Jr.
35
5.3
Wire Harnesses, Connectors, and Cable Fabrication
In order to simplify the assembly, transportation, testing, and modification
process, we designed and fabricated the following wire harnesses, connectors, and
cables:
•
For signals and voltages delivered to our circuit board from the function
generator and low-voltage bias power supply jacks, we wired, soldered, and
applied heat-shrink to the 15-pin D-sub connector shown in Figure 5.7.
•
To connect to the function generator 8-pin inline header output pins, we
used the mating female crimp contact receptacle also shown in Figure 5.7.
•
To connect to the output enable switch voltages from the front panel of our
enclosure, we used a 10-pin inline header with mating crimp contact
receptacle also shown
in Figure 5.7.
•
To connect the DC
Input Voltages to our
Input Capacitors and
Power Planes, we used
Fig. 5.7 – Fabricated Wire Harnesses
three parallel lines of
Source: John Brewer, Jr.
stranded 10AWG wire with crimp/ring connectors.
36
•
To connect output voltage nodes from the copper-clad circuit board to the
inductors and the LC output filters to the enclosure panel, we used stranded
10AWG wire with crimp/ring connectors. These ring connectors in
conjunction with nuts, bolts, washers, and lock washers made it quick to
assemble and disassemble our prototype for modifications.
5.4
Power Plane Construction
In order to effectively reduce parasitic inductances in the DC Input Voltage
supply path, we used double-sided copper-clad board for the ±input voltage
delivered to the IGBTs. We used a combination of precise cutting and drilling to
create isolated copper pads with at
least a 3:1 ratio of length to width for
current flow. A section of both the
top and bottom power planes are
shown in Figure 5.8.
5.5
Enclosure Fabrication
For ease of transportation,
Fig. 5.8 – Top and Bottom Sides of Copper-Clad Board
setup, and testing of our inverter
Source: John Brewer, Jr.
prototype, Jaime Carmo generously donated his time and materials to fabricate a
Plexiglas enclosure for us. This enclosure allowed us to effectively and efficiently
mount all of our system components and display our project for exhibition.
37
5.6
System Assembly
System assembly consisted of placing and arranging system components,
drilling mounting holes in the Plexiglas enclosure, and fastening components
together or to the enclosure with wire ties, circuit board standoffs, nuts, bolts,
washers, and lock washers. Our final System Assembly is shown in Figure 5.9.
Fig. 5.9 – Inverter System Assembly
Source: John Brewer, Jr.
38
VI.
TESTING
For our project, we performed several stages of testing – Ideal Inverter
Pspice simulation, IGBT Gate Driver and Half-Bridge Pspice simulation, PWM Control
Circuit hardware testing, PWM Control Circuit and single IGBT Half-Bridge hardware
low power testing, and full system testing.
For the Ideal Inverter Pspice simulation, we simulated an open-loop
switched-mode single phase PWM inverter circuit with Neutral phase using ideal
components as shown in Figure 6.1 to obtain the output sinusoidal waveform shown
in Figure 6.2.
Fig. 6.1 – Ideal Inverter Pspice Simulation
Source: John Brewer, Jr.
39
120V
80V
40V
-0V
-40V
-80V
-120V
45.0ms
45.5ms
V(R_LOAD:1)- V(R_LOAD:2)
46.0ms
46.5ms
47.0ms
47.5ms
48.0ms
48.5ms
49.0ms
49.5ms
50.0ms
Time
Fig. 6.2 – Output Voltage Waveform of Ideal Inverter Simulation
Source: John Brewer, Jr.
For the IGBT Gate Driver and Half-Bridge Pspice simulation shown in
Figure 6.3, we simulated an IR2113 Gate Driver and IRGP50B60PD1 Half-Bridge
driven with a 40kHz, 50% duty cycle square wave with 1μs of deadtime programmed
in between high-side and low-side switching. Despite not being able to use the
Si8234BB IGBT gate driver in our simulation, we were still able to analyze the
bootstrap power supply topology used to turn the high-side IGBT on. The gate-to-
Fig. 6.3 – IGBT Gate Driver and Half-Bridge Pspice Simulation
Source: John Brewer, Jr.
40
emitter voltage waveforms
40A
and output current waveform
20A
are shown in Figure 6.4.
We tried to limit the
0A
-20A
I(Rload)
20V
time spent developing and
10V
analyzing the Pspice
0V
simulations for our inverter
project because it was difficult
SEL>>
-10V
0s
5us
V(U2:2)- V(U2:3)
10us
V(U3:2)- V(U3:3)
15us
20us
25us
to accurately model all of the
Fig. 6.4 – High-side (green) and low-side (blue) IGBT
gate-to-emitter voltage waveforms. Load
current waveform (top).
parasitic elements that would
Source: John Brewer, Jr.
30us
affect the high-power performance of our hardware design in the end.
Concurrently, our detail-oriented approach to the design of the PWM Control Circuit
and the thorough analysis of the aforementioned design tips and application notes
published by International Rectifier and Silicon Labs regarding HVIC Gate Drivers and
the bootstrap supply topology warranted immediate prototyping and hardware
testing.
As a result, we constructed a prototype of our PWM Control Circuit design,
tested it, and observed successful results. Because we implemented resistance
trimmers at critical points in the circuit, we were able to fully tune the prototype
design. Next, we constructed a low-power single phase prototype of the IGBT Gate
Driver with bootstrap supply and Half-Bridge topology. At this point in the testing,
41
we encountered problems regarding bias supply ground referencing, low-side
decoupling capacitor sizing, and gate resistance sizing which caused us to take a
closer look at IR’s design notes and modify our circuit design. After doing so, our
testing yielded successful results for low-power switching of our IGBTs using ±39VDC
input supply and less than 1A output current.
After completing assembly of the final version of our proof-of-concept threephase inverter design, we performed full system tests. Due to a miscommunication
during a discussion about the DC Power available for testing in Cal Poly’s EE labs, we
were only able to test all three-phases of our inverter with a ±DC input supply
voltage of ±48V due to test equipment voltage and current limits. However, these
tests were all successful.
After powering-up the PWM Control Circuit with the inverter outputs
disabled, we turned on each phase and gradually increased the ±DC input supply
voltage while monitoring all node voltages on the high-voltage side of our circuit –
IGBT Gate Driver pin voltages, IGBT gate, collector, and emitter voltages, supply
voltages, and output voltage. After reaching test equipment current limits, we
reported the following about Figure 6.5 through Figure 6.10:
42
Fig. 6.5 – Adjustable Three-Phase
Three
Sinusoidal Reference signals successfully generated, UC3637
38kHz Triangle Wave successfully generated and compared with
with Sinusoidal Reference
signals to produce three
three-phase PWM Control Input signals.
Fig. 6.6 – Trigger
ger Pulse successfully generated by AD823AN Op-Amp
Op Amp Comparator.
43
Fig. 6.7 – Square wave with 97% duty cycle successfully generated by Trigger Pulse and HCF4538B
One-Shot.
Fig. 6.8 – Three-phase
phase and Neutral-phase
Neutral
Duty Cycle limited PWM Control Input signals
sign successfully
generated.
44
Fig. 6.9 –Three-phase
phase Inverter Output Voltage referenced to supply ground with ±48VDC Input
Voltage. Output voltage is 87 VP-P, 61 VRMS. Output RMS current is 6.2 A. Input RMS
current is supply limit of 6.5 A.
Fig. 6.10 –Three-phase
phase Inverter Output Voltage referenced
reference to virtual ground with ±46VDC Input
Voltage. Output voltage is 86 VP-P, 61 VRMS. Output RMS current is 6.2 A. Input RMS current is
supply limit of 6.5 A.
45
VII.
CONCLUSIONS
CONCLUSIONS AND RECOMMENDATIONS
Designing and fabricating a proof-of-concept high-voltage switched-mode
three-phase inverter capable of supplying 10kW covered a multitude of design
processes and proved to be a challenging endeavor. However, ensuring that a
detail-oriented approach was taken in the research, design, construction, and testing
stages of this project contributed to its successful completion and thorough
presentation in this report. While the original requirements for this project were
not met due to limitations in lab test equipment, observed test results yielded
successful system performance at lower power levels than intended for nominal
operation. Continued development of the proof-of-concept inverter system that has
been designed and fabricated for this project will assuredly lead to a productionlevel version with closed-loop feedback and possibly the following
recommendations.
Given the relatively high-current output capabilities of the Si8234BB HVIC
IGBT Gate Driver, up to two more IGBTs can be placed in parallel with each high-side
and low-side IGBT in the power stage to increase the system current output
capability while maintaining suitable IGBT switching transition times. However,
limitations to this increase in current output capability will rise from parasitic
inductance in the supply current path and action will be necessary to protect against
46
transient voltages. Limitations will also rise from the inability to sufficiently cool
IGBTs while minimizing parasitic inductance by maintaining close IGBT proximity.
The development of a floating supply to replace the bootstrap supply
topology designed for this project would eliminate the duty cycle limitations on the
high-side IGBT. A floating supply able to be ground referenced to the switching
output of the half-bridge would provide for unlimited high-side IGBT on time under
closed-loop control.
Development of a digital microprocessor-based PWM Control system could
potentially reduce the amount of space required by the PWM Control block and
allow for more versatile or accurate control performance. A digital PWM control
system could also have improved noise immunity and temperature tolerance.
If analog PWM control is desired, the design of a well laid-out surface mount
technology PCB is recommended. The signal voltages of the analog system designed
for this project could then be reduced for faster edge transitions so long as the
control circuit is effectively protected from noise and electromagnetic interference
(EMI).
As mention in Section 4.2.3.1, using a ferrite core wrapped with insulated
copper foil for the system inductors would result in lower core and copper losses
than the inductors in the current proof-of-concept system exhibit. This would
decrease the amount of cooling required by the inductors which would increase the
system quality.
47
Having made these recommendations, we maintain that the High-Voltage
Switched-Mode Power Supply for Three-Phase AC Aircraft Systems that we have
designed for this senior project presented to the Electrical Engineering faculty at
California Polytechnic State University, San Luis Obispo will fulfill the requirements
set by the sponsor, Jeff Brewer, after proper high-power testing, tuning, and no
significant design changes have been made.
48
VIII.
BIBLIOGRAPHY
[1]
Power Semiconductor Device,
http://en.wikipedia.org/wiki/Power_semiconductor_device,
Accessed June 4, 2010.
[2]
Brewer, John (Jeff), Director of Electrical Engineering, Aircraft Systems Group,
General Atomics Aeronautical Systems, Inc. Interview.
[3]
MIL-STD-704F,
http://www.wbdg.org/ccb/FEDMIL/std704f.pdf,
Accessed June 5, 2010.
[4]
International Rectifier Datasheet PD-94625B,
http://www.irf.com/product-info/datasheets/data/irgp50b60pd1.pdf,
Accessed June 6, 2010.
[5]
Silicon Labs Datasheet Si8234x,
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si823x.pdf,
Accessed June 7, 2010.
[6]
International Rectifier Design Tips DT04-4 Rev A,
http://www.irf.com/technical-info/designtp/dt04-4.pdf,
Accessed June 7, 2010.
[7]
ON Semiconductor Datasheet MUR460,
http://www.onsemi.com/pub_link/Collateral/MUR420-D.PDF,
Accessed June 7, 2010.
[8]
Unitrode Datasheet UC3637,
http://focus.ti.com/lit/ds/symlink/uc1637.pdf,
Accessed June 7, 2010.
49
[9]
Unitrode Design Note DN-53A,
http://focus.tij.co.jp/jp/lit/an/slua184/slua184.pdf,
Accessed June 7, 2010.
[10]
Unitrode Application Note U-102,
http://focus.ti.com/lit/an/slua137/slua137.pdf,
Accessed June 7, 2010.
[11]
Analog Devices Datasheet AD823AN,
http://www.analog.com/static/imported-files/data_sheets/AD823.pdf,
Accessed June 7, 2010.
[12]
STMicroelectronics Datasheet HCF4538B,
http://www.st.com/stonline/books/pdf/docs/2089.pdf,
Accessed June 7, 2010.
[13]
Fairchild Semiconductor Datasheet 74AC00,
http://www.fairchildsemi.com/ds/74%2F74AC00.pdf,
Accessed June 7, 2010.
[14]
McLyman, Colonel Wm. T. Transformer and Inductor Design Handbook.
Marcel Dekker Inc., Monticello, New York. 2004
[15]
PowerLite C-Cores,
http://www.metglas.com/downloads/powerlite.pdf,
Accessed June 8, 2010.
[16]
Applied Magnets AWG10-11,
http://www.magnet4less.com/product_info.php?products_id=175,
Accessed June 8, 2010.
50
APPENDICES
A.
Schematic
The following pages, 51 through 65, contain the Three-Phase Sinusoidal Inverter
schematic generated for this project.
A
B
C
D
UNLESS OTHERWISE SPECIFIED
PWM LIMIT LOGIC
3
2
Sheet
Sunday, June 06, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
PHASE-C PWM
7
9
15 OUTPUT FILTERS
PHASE-B PWM
6
PWM LIMIT TIMING
14 NEUTRAL GATE DRIVER
PHASE-A PWM
5
8
13 PHASE-C GATE DRIVER
12 PHASE-B GATE DRIVER
SIGNAL BUFFERING
3
NEUTRAL PWM
11 PHASE-A GATE DRIVER
IO CONNECTORS
2
4
10
PWM LIMIT LOGIC
THREE PHASE INVERTER
CONTENTS
3
TABLE OF CONTENTS
4
4
1
5
1. ALL RESISTORS ARE 1/8W, 1%
2. ALL CAPACITORS ARE 10%, 50V.
NOTES:
5
1
1
1
of
15
Rev
E
A
B
C
D
A
B
C
D
10
9
8
7
6
5
4
3
2
1
5
DGND
-190V_SUPPLY
J1
5
15V_RTN
NC
5V_RTN
4
12V_RTN
5V_RTN
A_B_SD_SWCH [14,15]
+5V
5V_RTN
N_SD_SWCH [17]
+5V
5V_RTN
3
15
8
14
7
13
6
12
5
11
4
10
3
2
9
1
15V_RTN
C1
820uF
25V
+15V
J2
3
C91
560uF
C2
4.7uF
DGND
2
C3
820uF
25V
15V_RTN
C4
4.7uF
-15V
2
1
C6
4.7uF
SIN_C [3]
SIN_B [3]
Sheet
Sunday, June 06, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
1
of
+12V
SIN_A [3]
SPARE
SPARE
5V_RTN
C5
820uF
25V
5V_RTN
+5V
+5V
Size
A
Engineer: J. BREWER, JR.
15V_RTN
-15V
+15V
THREE PHASE INVERTER
IO CONNECTORS
C_SD_SWCH [16]
+5V
4
15
Rev
E
12V_RTN
A
B
C
D
A
B
C
D
C8
0.1uF
[2] SIN_B
15V_RTN
+15V
[2] SIN_A
5
5
10uF
16V
C10
R1
100k
DGND
R4
100k
DGND
C9
0.1uF
15V_RTN
-15V
10uF
16V
C7
15V_RTN
R5
1.0k
-
+
4
+15V
R3
20k
1/4W
OUT
-15V
U1B
TL082
6
5
15V_RTN
R2
1.0k
-
+
U1A
TL082
2
3
+15V
8
-15V
4
R6
20k
1/4W
OUT
7
1
C11
0.1uF
3
SIN_B_BUF [6]
[2] SIN_C
15V_RTN
+15V
SIN_A_BUF [5]
[4] TRI_WAVE
C12
0.1uF
10uF
16V
C13
15V_RTN
-15V
R7
100k
-
+
U2A
15V_RTN
-
+
TL082
6
5
1
+15V
U2B
OUT
-15V
R8
1.0k
TL082
2
3
+15V
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
7
Size
A
R9
20k
1/4W
OUT
-15V
Engineer: J. BREWER, JR.
DGND
THREE PHASE INVERTER
SIGNAL BUFFERING
3
8
V+
V-
4
V+
V4
8
V+
V4
8
V+
V4
3
1
of
15
Rev
E
SIN_C_BUF [7]
TRI_BUF [5,6,7,9]
1
A
B
C
D
A
B
C
D
5
-15V
R14
20.5k
R13
5.62k
R12
68.1k
R11
5.62k
R10
20.5k
+15V
5
C14
300pF
R16
10k
1/4W
4
R15
47.5k
4
-15V
R18
330k
R17
100k
+15V
-15V
R20
150k
R19
150k
+15V
C16
0.1uF
3
15V_RTN
C15
0.1uF
1
3
18
14
2
15
16
12
13
C17
0.1uF
15V_RTN
15V_RTN
15V_RTN
C87
0.1uF
11
10
8
9
UC3637
+VTH
-VTH
ISET
SD
CT
+E/A
-E/A
+C/L
-C/L
+AIN
-AIN
+BIN
-BIN
U3
+15V
THREE PHASE INVERTER
MASTER PWM
3
-VS
+VS
6
0.1uF
C19
E/AOUT
AOUT
BOUT
0.1uF
C18
15V_RTN
17
4
7
15V_RTN
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
-15V
5
4
1
of
15
Rev
E
PWM_UVLO [5,6,7]
NEUTRAL_PWM [11]
SLV_THRSH- [5,6,7,9]
SLV_THRSH+ [5,6,7,9]
TRI_WAVE [3]
1
A
B
C
D
A
B
C
D
5
5
[4] SLV_THRSH+
[4] SLV_THRSH-
[4] PWM_UVLO
[3] SIN_A_BUF
[3] TRI_BUF
4
4
15V_RTN
15V_RTN
3
C21
0.1uF
C20
0.1uF
15V_RTN
C22
0.1uF
1
3
18
14
2
15
16
12
13
11
10
8
9
UC3637
+VTH
-VTH
ISET
SD
CT
+E/A
-E/A
+C/L
-C/L
+AIN
-AIN
+BIN
-BIN
U4
+15V
THREE PHASE INVERTER
PHASE-A PWM
3
-VS
+VS
6
0.1uF
C24
E/AOUT
AOUT
BOUT
0.1uF
C23
15V_RTN
17
4
7
15V_RTN
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
-15V
5
5
1
of
A_PWM [10]
1
15
Rev
E
A
B
C
D
A
B
C
D
5
5
[4] SLV_THRSH+
[4] SLV_THRSH-
[4] PWM_UVLO
[3] SIN_B_BUF
[3] TRI_BUF
4
4
15V_RTN
15V_RTN
3
C26
0.1uF
C25
0.1uF
15V_RTN
C27
0.1uF
1
3
18
14
2
15
16
12
13
11
10
8
9
UC3637
+VTH
-VTH
ISET
SD
CT
+E/A
-E/A
+C/L
-C/L
+AIN
-AIN
+BIN
-BIN
U5
+15V
THREE PHASE INVERTER
PHASE-B PWM
3
-VS
+VS
6
0.1uF
C29
E/AOUT
AOUT
BOUT
0.1uF
C28
15V_RTN
17
4
7
15V_RTN
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
-15V
5
6
1
of
B_PWM [10]
1
15
Rev
E
A
B
C
D
A
B
C
D
5
5
[4] SLV_THRSH+
[4] SLV_THRSH-
[4] PWM_UVLO
[3] SIN_C_BUF
[3] TRI_BUF
4
4
15V_RTN
15V_RTN
3
C31
0.1uF
C30
0.1uF
15V_RTN
C32
0.1uF
1
3
18
14
2
15
16
12
13
11
10
8
9
UC3637
+VTH
-VTH
ISET
SD
CT
+E/A
-E/A
+C/L
-C/L
+AIN
-AIN
+BIN
-BIN
U6
+15V
THREE PHASE INVERTER
PHASE-C PWM
3
-VS
+VS
6
0.1uF
C34
E/AOUT
AOUT
BOUT
0.1uF
C33
15V_RTN
17
4
7
15V_RTN
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
-15V
5
7
1
of
C_PWM [11]
1
15
Rev
E
A
B
C
D
A
B
C
D
5
[4] SLV_THRSH+
[3] TRI_BUF
5
-
C36
0.1uF
15V_RTN
6
-
U7B
5
+
15V_RTN
+15V
15V_RTN
C35
0.1uF
2
U7A
3
+
OUT
4
-15V
7
AD823AN
+15V
15V_RTN
-15V
-15V
1
C37
0.1uF
OUT
3
R21
1.0k
15V_RTN
D1
SD103A
3
C38
5600pF
R22
10k
1/4W
16
VDD
Q2/ 9
12+TR(2)
15V_RTN
Vss
HCF4538B 8
15Cx(2)
14RxCx(2)
13RESET(2)
Q2 10
Q1/ 7
11-TR(2)
5 -TR(1)
4 +TR(1)
0.1uF
C39
Q1 6
+15V
3 RESET(1)
2 RxCx(1)
1 Cx(1)
U8
2
1
8
1
of
DUTY_LIMIT [10,11]
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
15V_RTN
Size
A
Engineer: J. BREWER, JR.
THREE PHASE INVERTER
PWM LIMIT TIMING
AD823AN
+15V
4
8
V+
V4
8
V+
V4
15
Rev
E
A
B
C
D
A
B
C
D
[9] DUTY_LIMIT
[6] B_PWM
[9] DUTY_LIMIT
[5] A_PWM
5
5
10.2k
R28
10.2k
R23
10.2k
R29
15V_RTN
D3
SD103A
15V_RTN
D2
SD103A
10.2k
R24
4
4
20.5k
R31
15V_RTN
R30
10.2k
20.5k
R26
15V_RTN
R25
10.2k
15V_RTN
R32
10.2k
15V_RTN
R27
10.2k
2
1
10
9
U9A
U9C
3
74AC00
3
74AC00
8
5
4
13
12
U9B
U9D
11
2
+5V
1
9
1
5V_RTN
C40
0.1uF
Sheet
Sunday, June 06, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
B_DRIVE [15]
A_DRIVE [14]
Size
A
Engineer: J. BREWER, JR.
74AC00
6
74AC00
THREE PHASE INVERTER
PWM LIMIT LOGIC
3
of
15
Rev
E
A
B
C
D
A
B
C
D
[9] DUTY_LIMIT
5
[4] NEUTRAL_PWM
[9] DUTY_LIMIT
[7] C_PWM
5
10.2k
R38
10.2k
R33
10.2k
R39
15V_RTN
D5
SD103A
15V_RTN
D4
SD103A
10.2k
R34
4
4
20.5k
R41
15V_RTN
R40
10.2k
20.5k
R36
15V_RTN
R35
10.2k
15V_RTN
R42
10.2k
15V_RTN
R37
10.2k
10
9
2
1
U10C
U10A
3
74AC00
8
74AC00
3
13
12
5
4
U10D
U10B
6
2
Sheet
Sunday, June 06, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
+5V
1
10
1
5V_RTN
C41
0.1uF
NEUTRAL_DRIVE [17]
C_DRIVE [16]
Size
A
Engineer: J. BREWER, JR.
74AC00
11
74AC00
THREE PHASE INVERTER
PWM LIMIT LOGIC
3
of
15
Rev
E
A
B
C
D
A
B
C
D
[2] A_B_SD_SWCH
[10] A_DRIVE
5
C43
0.1uF
5
5V_RTN
C86
0.1uF
R43
100k
1/4W
0.1uF
C42
8
Si8234BB
VDDI
NC
DT
6
7
DISABLE
4
12
10
GNDB 9
VOB
VDDB 11
NC
13
NC
GNDI
5
4
15
GNDA 14
VOA
VDDA 16
VDDI
NC
2
3
PWM
1
U11
5V_RTN
+5V
4
C45
C44
+15V
C49
C82
C48
C46
0.33uF
D6
MUR460
+15V
15V_RTN
0.1uF
0.33uF
10uF
3
15V_RTN
C47
0.33uF
0.1uF
10uF
D8
MUR460
D7
16V
+190V
D10
16V
D9
16V
2
2
-190V
2
U13
2
U12
IRGP50B60PD1
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
4.7
R45
3.9
R44
THREE PHASE INVERTER
PHASE-A GATE DRIVER
3
1
1
3
3
1
1
3
3
11
1
1
of
15
Rev
E
PHASE_A [18]
A
B
C
D
A
B
C
D
[2] A_B_SD_SWCH
[10] B_DRIVE
5
C51
0.1uF
5
5V_RTN
C88
0.1uF
R46
100k
1/4W
0.1uF
C50
8
Si8234BB
VDDI
NC
4
10
GNDB 9
VOB
VDDB 11
DT
6
7
NC
DISABLE
12
13
NC
GNDI
5
4
15
GNDA 14
VOA
VDDA 16
VDDI
NC
2
3
PWM
1
U14
5V_RTN
+5V
4
C53
C52
+15V
C57
C83
C56
C54
0.33uF
D13
MUR460
+15V
15V_RTN
0.1uF
0.33uF
10uF
3
15V_RTN
C55
0.33uF
0.1uF
10uF
D15
MUR460
D14
16V
+190V
D17
16V
D16
16V
2
2
-190V
2
U16
2
U15
IRGP50B60PD1
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
4.7
R48
3.9
R47
THREE PHASE INVERTER
PHASE-B GATE DRIVER
3
1
1
3
3
1
1
3
3
12
1
1
of
15
Rev
E
PHASE_B [18]
A
B
C
D
A
B
C
D
[2] C_SD_SWCH
[11] C_DRIVE
5
C59
0.1uF
5
5V_RTN
C89
0.1uF
R49
100k
1/4W
0.1uF
C58
8
Si8234BB
VDDI
NC
4
10
GNDB 9
VOB
VDDB 11
DT
6
7
NC
DISABLE
12
13
NC
GNDI
5
4
15
GNDA 14
VOA
VDDA 16
VDDI
NC
2
3
PWM
1
U17
5V_RTN
+5V
4
C61
C60
+15V
C65
C84
C64
C62
0.33uF
D20
MUR460
+15V
15V_RTN
0.1uF
0.33uF
10uF
3
15V_RTN
C63
0.33uF
0.1uF
10uF
D22
MUR460
D21
16V
+190V
D24
16V
D23
16V
2
2
-190V
2
U19
2
U18
IRGP50B60PD1
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
4.7
R51
3.9
R50
THREE PHASE INVERTER
PHASE-C GATE DRIVER
3
1
1
3
3
1
1
3
3
13
1
1
of
15
Rev
E
PHASE_C [18]
A
B
C
D
A
B
C
D
[2] N_SD_SWCH
5
C67
0.1uF
[11] NEUTRAL_DRIVE
5
5V_RTN
C90
0.1uF
R52
100k
1/4W
0.1uF
C66
8
Si8234BB
VDDI
NC
4
10
GNDB 9
VOB
VDDB 11
DT
6
7
NC
DISABLE
12
13
NC
GNDI
5
4
15
GNDA 14
VOA
VDDA 16
VDDI
NC
2
3
PWM
1
U21
5V_RTN
+5V
4
C69
C68
+15V
C73
C85
C72
C70
0.33uF
D27
MUR460
+15V
15V_RTN
0.1uF
0.33uF
10uF
3
15V_RTN
C71
0.33uF
0.1uF
10uF
D29
MUR460
D28
16V
+190V
D31
16V
D30
16V
2
2
-190V
2
U22
2
U21
IRGP50B60PD1
2
Sheet
Monday, June 07, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
Size
A
Engineer: J. BREWER, JR.
4.7
R54
3.9
R53
THREE PHASE INVERTER
NEUTRAL GATE DRIVER
3
1
1
3
3
1
1
3
3
14
1
1
of
15
Rev
E
NEUTRAL [18]
A
B
C
D
A
B
C
D
5
[15] PHASE_B
[14] PHASE_A
5
160uH
L2
160uH
L1
4
4
PWR_GND
C76
20uF
400V
PWR_GND
C74
20uF
400V
C77
20uF
400V
C75
20uF
400V
SIN_B_OUT
SIN_A_OUT
3
[17] NEUTRAL
[16] PHASE_C
160uH
L4
160uH
L3
2
PWR_GND
C78
20uF
400V
-190V
C81
3300uF
350V
C80
3300uF
350V
+190V
Sheet
Sunday, June 06, 2010
Date:
2
Document Number
SCHEMATIC, THREE PHASE INVERTER
1
15
1
SIN_C_OUT
PWR_GND
C79
20uF
400V
Size
A
Engineer: J. BREWER, JR.
THREE PHASE INVERTER
OUTPUT FILTERS
3
of
15
Rev
E
A
B
C
D
66
B.
Bill of Materials
Table B.1 – Bill of Materials and Donated Items
Item
Hardware
CS Hyde Metalized Mylar Tape, 2.2 mil. Thick,
1' x 72 yds
SPDT 6A F.LVR Switch
SPDT 6A R.LVR Switch
D-Sub 15 Pin Male
D-Sub 15 Pin Female
Pre-Punched IC-Spacing Perfboard 2-3/4"x6"
2-Sided Cooper Clad Board 4.5"x6.125"
Assorted Cable Ties 8"
8-10 Stud Ring Terminals
Door Handles
PCB Standoff 1"
PCB Standoff 2 1/4"
Crimp Pins Male
Plastic Rectangular Crimp Pin Receptacle
Corner Brace 1-1/2"
White Screw Bumper
Ring Tongue Connector
#4-40 x 1/2' Round Head - Slotted Bolt
#4-40 x 1/2' Round Head - Phillips Bolt
#4-40 Nut
#6-32 x 3/8' Round Head - Slotted Bolt
#6-32 Nut
#6 Lock Washer
#6 SAE Washer
#10-32 x 3/8" Round Head - Slotted Bolt
#10-32 x 1/2" Round Head - Slotted Bolt
#10-32 x 5/8" Round Head - Slotted Bolt
#10-32 x 3/4" Round Head - Slotted Bolt
#10-32 x 1" Rounded - Slotted Bolt
#10-32 x 1/2" Flat Head- Phillips Bolt
#10-32 Nut
#10 Lock Washer
#10 SAE Washer
Aluminum Flat Plate
Unit
Price ($)
13.5
3.69
3.69
2.49
2.49
3.99
3.99
5.99
0.14
3.49
0.45
0.35
0.1
0.5
0.63
0.49
0.25
0.1
0.1
0.03
0.1
0.03
0.06
0.03
0.1
0.1
0.1
0.1
0.1
0.1
0.03
0.06
0.03
9.85
Quantity
1
2
1
1
1
3
3
1
21
2
4
2
15
2
4
8
13
12
4
10
16
16
28
40
8
8
5
16
9
8
59
75
69
1
Total
Price ($)
13.5
7.38
3.69
2.49
2.49
11.97
11.97
5.99
2.94
6.98
1.8
0.7
1.5
1
2.52
3.92
3.25
1.2
0.4
0.3
1.6
0.48
1.68
1.2
0.8
0.8
0.5
1.6
0.9
0.8
1.77
4.5
2.07
9.85
67
Polyolenfin Heat Shrink Tubing 3/32"
Polyolenfin Heat Shrink Tubing 3/32"
IC Socket Mach Pin WW 8Pos Gold - AR08-HZW/T-R
IC Socket Mach Pin WW 14Pos Gold - AR14-HZW/T-R
IC Socket Mach Pin WW 16Pos Gold - AR16-HZW/T-R
IC Socket Mach Pin WW 18Pos Gold - AR18-HZW/T-R
Square Machine Post - 100
Coaxial DC Power Jack
Coaxial DC Power Plug
Electronics
Texas Instruments - OpAmp Dual JFET Input TL082CP
Unitrode - SM Crtl for DC Motor Drive - UC3637
Analog Devices Inc - OpAmp JFET R-R Dual AD823AN
Fairchild Semiconductor - Quad 2 Input Nand 74AC00B
International Rectifier - IGBT - IRGP50B60PD1
STMicroelectronics - Multivibrator - HCF4538B
Silicon Labs - High Side / Low Side Driver - Si8234BB
Mallory CGS332T350X5L 3300μF 350VDC Capacitor
United Chemi-Con - Cap Elect 820uF 50V
Panasonic - ECG - Cap 4.7uf 25V Cer - PCC2251CT-ND
TDK Corp - Cap Cer 10uF 16V X7R RAD FK20X7R1C106K
Panasonic - ECG - Cap Elect 10uF 400V - EEUED2G100
BC Components - Cap Cer .10UF 50V K104K15X7RF5TH5
Murata Electronics NA - Cap Cer 300pF 50V
Murata Electronics NA - Cap Cer 5600pF 50V
TDK Corporation - Cap Cer 0.33uF 50V FK24X7R1H334K
United Chemi-Con - Cap Elect 560uF 50V
Diodes Inc - Diode Schottky 40V 400MW - SD103A-T
ON Semiconductor - Switchmode -Diode 4A 600V
Murata Electronics NA - Trim Pot Cerm 100kOhm Stackpole Electronics Inc - RES 1kOhm 1/8W 5% Murata Electronics NA - Trim Pot Cer 20kOhm
Yageo - Res 20.5kohm 1/4W 1% Metal Film
Stackpole Electronics - Res MF 1/8W 5.62kOhm 1%
Stackpole Electronics Inc - Res MF 1/8W
68.1kOhm 1%
1.79
1.95
1.69
2.53
2.9
2.9
4.99
3.29
3.29
1
1
3
2
5
4
1
4
4
1.79
1.95
5.07
5.06
14.5
11.6
4.99
13.16
13.16
0.77
7.28
2
4
1.54
29.12
5.64
1
5.64
0.6
8.28
0.65
3.71
71.45
1.29
0.79
2
16
1
4
2
3
3
1.2
132.48
0.65
14.84
142.9
3.87
2.37
0.83
3
2.49
0.67
8
5.36
0.06
0.3
0.62
51
1
1
3.06
0.3
0.62
0.21
0.86
0.65
0.65
1.38
0.09
1.38
0.57
0.15
12
1
5
8
8
4
3
6
2
2.52
0.86
3.25
5.2
11.04
0.36
4.14
3.42
0.3
0.15
1
0.15
68
Stackpole Electronics Inc - Res MF 1/8W
47.5kOhm 1%
Murata Electronics NA - Trim Pot Cerm
10kOhm 12Trn
Stackpole Electronics Inc - Res MF 1/8W
330kOhm 1%
Stackpole Electronics Inc - Res MF 1/8W
150kOhm 1%
Stackpole Electronics Inc - Res MF 1/8W
10.2kOhm 1%
Stackpole Electronics Inc - Res MF 1/8W 3.9Ohm 1%
Stackpole Electronics Inc - Res MF 1/8W 4.7Ohm 1%
Wire
UL- Stranded Hookup Wire - 22AWG - Red 25'
UL- Stranded Hookup Wire - 22AWG - Green 25'
UL- Stranded Hookup Wire - 22AWG - Black 25'
10AWG - Mil Spec - M81044/ 9-10-9 - White 10'
10AWG - Mil Spec - M81044/ 9-10-0 - Black 10'
26AWG - Stranded HookupWire - Red - 25'
26AWG - Stranded HookupWire - Black - 25'
26AWG - Assorted Stranded HookupWire - 25'
Magnet Wire / Winding Wire - 10 AWG, 11LBS
Wire Roll Repl 30AWG Blue 50'
Wire Roll Repl 30AWG Yellow 50'
Wire Roll Repl 30AWG Green 50'
Wire Roll Repl 30AWG Orange 50'
Donated Items
Plexiglass Project Box 22 3/8"X 20 1/8" X 9 1/4"
dsPIC Funtion Generator
Electrocube 945B 20μF 400VDC Capacitor
Powerlite C-Core AMCC 50
Powerlite Bobbin AMCC-50BOB
0.15
1
0.15
1.81
2
3.62
0.15
1
0.15
0.15
2
0.3
0.15
0.15
0.15
16
4
4
2.4
0.6
0.6
2.33
2.33
2.33
4
4
2.25
2.25
4.99
124.99
9.12
9.12
9.12
9.12
1
1
1
1
1
1
1
1
1
1
1
1
1
Grand
Total
2.33
2.33
2.33
4
4
2.25
2.25
4.99
124.99
9.12
9.12
9.12
9.12
Quantity
1
1
6
8
8
757.27
69
C.
Circuit Board Layout
Fig. C.1 – Microsoft PowerPoint Circuit Board Layout
Source: John Brewer, Jr. and Kamaljit Bagha
70
D.
Circuit Board IC and Component Locations
Fig. D.1 – IC and Component Circuit Board Location
Source: John Brewer, Jr. and Kamaljit Bagha
71
E.
Hardware Configuration and Layout
Fig. E.1 – Hardware Configuration and Layout
Source: Kamaljit Bagha
72
Fig. E.2 – Test Bench Setup
Source: Kamaljit Bagha