International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 2, Issue 2, March – April 2013
ISSN 2278-6856
Optimization and Simulation of Two Stage
Operational Amplifier Using 180nm and 250nm
Technology
Haresh S. Chaudhari1, Nilesh D. Patel2 and Jaydip H. Chaudhari3
1,3
PG Student, Gujarat Technology University, Electronics and Communication,
LCIT-Bhandu, Mehsana, Gujarat, India
2
Assistant Professor, Electronics and Communication, LCIT-Bhandu,
Mehsana, Gujarat, India
Abstract:
As the CMOS process entering the nanometer
scale analog circuit will need to operate in lower and lower
supply voltage. This trend is primarily driven by the need to
low power and low voltage requirement on the consumer
electronics market. High gain enables the circuit to operate
efficiently in a closed loop feedback system. The design is
optimization and simulates on TSMC 180nm and 250nm
CMOS process at 1.8 V and 2.5 V supply voltages respectively.
Supply voltage under room temperature 27ºC. The simulation
result shows that a bandwidth is 8.10 MHz and 2.19 MHz in
180nm and 250nm Technology. Gain is 64.539 dB and 59.696
dB achieved for the two stage op-amp circuit.
Keywords: Two stage operational amplifier, fully
differential, MOSFET.
1. INTRODUCTION
Operational amplifier is among the most used electronic
devices today, used in a wide range of consumer devices,
industrial and scientific. In many applications of
operational amplifiers, the gain of a single stage amplifier
is not sufficient. Architectures of operational amplifiers
using two or more gain stages widely used in higher gains
are needed. Op-amps are available in many topologies, a
two stage op-amp is an example of this kind, which is
used when the high input impedance and low output
impedance is needed.
CMOS operational amplifiers can be used effectively for
the practical consequences for example the design of a
switched capacitor filter, analog-digital converters,
oscillator, and digital-analog converter and waveform
generators.
The objective of the design methodology in this paper is
to propose a simple but accurate equation for the design
of high gain two stage CMOS op-amp. To do this, a
simple analysis with some significant parameters (phase
margin, bandwidth, gain margin, slew rate etc.) is
performed. Process maintains a wide variety of
specifications and constraints. In this paper, we formulate
the CMOS op-amp design problem and their aspect
ratios. The method we can be applied to a wide variety of
Volume 2, Issue 2 March – April 2013
amplifier architectures, but in this paper we apply the
method to a specific two-stage CMOS op-amp.
The simulation results have been obtained by TSMC
180nm and 250nm CMOS technology. Design has been
carried out in Mentor Graphics tool. After the simulation,
most of the transistors size still needed to be modified in
order to optimize the performance.
2. BLOCK DIAGRAM OF TWO STAGE CMOS
OP-AMP
Operational amplifier is the backbone for many analog
circuit designs. Optimization of all parameters in a design
has become mandatory now-a-days. In the recent years,
various topologies of a new genus have evolved and been
used in various applications. Here, we chose a simple pair
differential amplifier Immune input amplifier, common
source amplifier (high gain) to the output amplifier, a
current mirror circuit as bias circuit, and a buffer circuit
compensation current as well as a Miller capacitance in
series with one another.
The topology of the circuit designed is that of a standard
CMOS two stage op-amp. It comprised of three
subsections of circuits, namely differential gain stage,
second gain stage and bias strings.
2.4. Differential Gain Stage
The first subsection of interest is the differential gain
stage which is comprised of transistor M1 to M4. In
figure 1 transistor M1 and M2 are standard N channel
MOSFET transistor which form the basic input stage of
the amplifier. The gate of M1 is the inverting input and
the gate of M2 is the non-inverting input. A differential
input signal applied across the two input terminals will be
amplified according to the gain of the differential stage.
The transconductance of this stage is simply the
transconductance of M1 or M2. M3 and M4 are the active
load transistors of the differential amplifier. The current
Page 152
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 2, Issue 2, March – April 2013
ISSN 2278-6856
mirror active load used in this circuit has three distinct
advantages. First, the use of active load devices creates a
large output resistance in a relatively small amount of die
area.
Figure 1 The topology chosen for this Op-Amp design
2.2 Second Gain Stage
The second stage is a current sink load inverter. The
purpose of the second gain stage, as the name implies, is
to provide additional gain, in the amplifier. Consisting of
transistor M5 and M8, this stage takes the output from
the drain of M2 and amplifies it through M5 which is in
the standard common source configuration. Similar to the
differential gain stage, this stage employs an active
device, M8, to serve as the load resistance for M5. The
gain of this stage is the transconductance of M5 times the
effective load resistance comprised of the output
resistance of M5 and M8. M8 is the driver while M7 acts
as load.
2.3 Bias String
The biasing of the operational amplifier is achieved with
only two transistors along with a current source.
Transistor M6 and the current source supply a voltage
between the gate and source of M7 and M8. Transistor
M7 and M8 sink a certain amount of current based on
their gate to source voltage which is controlled by the bias
string. M6 is diode connected to ensure it operate in the
saturation region. Proper biasing of the other transistors
in the circuit is controlled by the node voltages present in
the circuit itself.
3. TWO STAGE OP-AMP SCHEMATIC DESIGN
The op-amp DC gain is greater than 55 dB. Schematic of
an unbuffered, two stage CMOS op-amp with an nchannel input pair in figure 2. It is assumed that all
transistors are in saturation for the above relationships.
Volume 2, Issue 2 March – April 2013
Figure 2 Schematic design of two stage CMOS op-amp
4. SIMULATION RESULT
4.1 Simulation Result for 180nm Technology
Frequency Response:
Figure 3 Result of gain, gain margin, phase margin and
bandwidth in 180nm technology
Obtained result in 180nm technology is gain= 64.539 dB,
gain margin is 17.997 dB, phase margin = 75.837º,
bandwidth = 8.10 MHz, and power dissipation for 180nm
tech. is 0.92 mV.
Slew Rate:
Page 153
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 2, Issue 2, March – April 2013
ISSN 2278-6856
Figure 6 Result of slew rate in 250nm technology
Figure 4 Result of slew rate in 180nm technology
Obtained slew rate is 25.69 V/µs.
Table 1: Comparison between 180nm and 250nm
technology results
Technologies
4.2 Simulation Result for 250nm Technology
Frequency Response:
Parameters
180nm
250nm
Gain (dB)
64.539
59.696
Gain margin (dB)
17.997
12.984
Phase Margin (º)
75.837
78.822
Bandwidth (MHz)
8.10
2.19
Power Dissipation
(mV)
0.92
2.09
Slew Rate (V/ µs)
25.69
11.99
5. CONCLUSION
Figure 5 Result of gain, gain margin, phase margin and
bandwidth in 250nm technology
Obtained result in 250nm technology is gain= 59.696 dB,
gain margin is 12.984 dB, phase margin = 78.822º,
bandwidth = 2.19 MHz, and power dissipation for 250nm
tech. is 2.09 mV.
Slew Rate:
Obtained slew rate is 11.99 V/µs.
In this paper two stage op-amps is optimized and
simulated in 180nm and 250nm technology. Power supply
of the architecture is 1.8V and 2.5V respectively.
Obtained gain in 180nm tech. is 64.539 dB, bandwidth is
8.10 MHz’s and power dissipation is 0.924 mW. In
250nm tech. gain is 59.696 dB, bandwidth is 2.19 MHz
and power dissipation is 2.09 mW. Try to improve gain
and bandwidth in these two technologies and also find
other characteristics (parameters) of two stage op-amp.
References
[1] Amana Yadav “Design of Two-Stage CMOS OpAmp and Analyze the Effect of Scaling”
International Journal of Engineering Research and
Applications (IJERA) ISSN: Vol. 2, Issue 5,
September- October 2012, pp.647-654.
[2] Amana Yadav, “A Review Paper on Design and
Synthesis of two stage CMOS op-amp” International
Volume 2, Issue 2 March – April 2013
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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 2, Issue 2, March – April 2013
ISSN 2278-6856
Journal of Advances in Engineering & Technology
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[3] Bhavesh H. Soni, Rasika N. Dhavse, “Design of
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[4] Zihong Liu, Zhihua Wang, Chao Bian, Chun Zhang,
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Nilesh D. Patel, Assistant Professor, L.C.
Institute of Technology, Bhandu received his B.E.
degree from SCET, Surat and M. Tech – VLSI
Design from Institute of Technology, Nirma
University, Ahmedabad.
Jaydip H. Chaudhari received B.E
degree
from Dharmsigh Desai University, and pursuing
M.E. in VLSI System Design from Laljibhai
Chaturbhai Institute of Technology Bhandu,
Mehsana.
[5] Ramakant A. Gayakawad “Op-Amps and linear
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[7] Nikola Ivanisevic, Mirjana Videnovic-Misic, Alena
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[8] Savisha A. P. Mahalingam, Md. Mamun, Labonnah
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[9] J.Mahattanakul, “Design Procedure for Two-Stage
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[10] Sachin kumar Rajput, “Design of Two-Stage High
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[11] Rajkumar Singh Parihar, “Design of a Fully
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[12] http://en.wikipedia.org/wiki/Operational_amplifier
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AUTHOR
Haresh S. Chaudhari
received my B.E
degree from L.D.R.P. Institute of Technology
and Research, and pursuing M.E. in VLSI
System Design from Laljibhai Chaturbhai
Institute of Technology Bhandu, Mehsana. My area of interest
on analog circuit and low power VLSI.
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