Analog Integr Circ Sig Process (2013) 74:193–201
DOI 10.1007/s10470-012-9978-5
A single capacitor loop filter phase-locked loop with frequency
voltage converter
Jeong-hoon Nam • Young-Shig Choi
Moon G. Joo
•
Received: 7 May 2012 / Revised: 19 June 2012 / Accepted: 3 October 2012 / Published online: 18 October 2012
Ó Springer Science+Business Media New York 2012
Abstract A novel phase-locked loop that has a loop filter
consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop
(PLL) works stably demonstrating that the FVC works
effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 lm
CMOS process show that the phase noise is -109 dBc/Hz
at 10 MHz offset from 752.7 MHz output frequency.
Keywords Frequency voltage converter Phase-locked loop Phase noise
1 Introduction
Phase-locked loops (PLL) have been widely used in frequency synthesizers for communication systems and clock
signal generators for integrated digital chips. Typically, a
PLL consists of a phase frequency detector (PFD), a charge
pump (CP), a loop filter (LF), a voltage-controlled oscillator
(VCO), and a divider [1]. A PLL is usually the third-order
closed loop system that includes the second-order LF consisting of two capacitors and one resistor. It has one low
frequency zero, and three poles consisting of two poles at
J. Nam Y.-S. Choi (&)
Department of Electronics Engineering, Pukyong National
University, 599-1 Daeyeon 3-dong, Nam-gu, Busan 698-737,
South Korea
e-mail: choiys@pknu.ac.kr
M. G. Joo
Department of Telecommunication Engineering,
Pukyong National University, 599-1 Daeyeon 3-dong, Nam-gu,
Busan 698-737, South Korea
origin and one pole at high frequency. Careful design of
poles and zero location is required to ensure a stable operation of PLL. The type of second-order PLL with a firstorder LF consisting of one resistor and one capacitor is easy
to design for a stable operation of PLL. It has one low
frequency zero and two poles at origin. However, this type
of second-order PLL has not been popular because it has a
large spur caused by the resistor of LF. The other type of
second-order PLL has a single capacitor LF, but it has not
been used because it oscillates due to the two poles at origin.
Various architectures of the PLL without a resistor in LF
have been published. A feed-forward path is introduced to
make a stabilizing loop zero without a resistor in LF [2, 3].
The feed-forward scheme does not contribute in improving
noise characteristic. A sampled-feed-forward LF with
switches is implemented to replace a conventional RC LF
[4, 5]. The sampled-feed-forward LF produces a fixed
duration proportional voltage in VCO input. It does contribute in improving spur performance.
This paper introduces a new architecture of second-order
PLL consisting of a single capacitor LF and an frequency
voltage converter (FVC). The FVC works effectively as a
resistor for stable operation of the proposed single capacitor
LF PLL. The FVC also changes the closed loop transfer
function of the proposed PLL and improves noise characteristic unlike the previously published PLL with no resistor
in LF. The noise characteristic would also be better than that
of the conventional second-order LF PLL because the closed
loop of VCO and FVC reduces the largest VCO noise in PLL.
In Sect. 2, the proposed architecture is explained. Sections 3 and 4 illustrate the major building blocks and simulation results, respectively. The measurement results are
reported in Sect. 5. The merits of the proposed PLL compared with the conventional PLL are described in Sect. 6.
Finally, the conclusion is presented in Sect. 7.
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Analog Integr Circ Sig Process (2013) 74:193–201
UP
DN
VLF
CP
Rz
LF
VLF
Kvco1
FVC
VFVC
Kvco2
+ VCO
Cs
φo
Cz
(a)
(a)
Fref
UP-DN
UP-DN
with Cs
VLF
Vproportional
VLF
Vintegral
(b)
VFVC
Fig. 1 a Conventional RC LF. b Output voltage of RC LF
Vproportional
VLF + VFVC
Vintegral
(b)
2 Proposed PLL with FVC
2.1 Role of FVC
In the conventional RC LF shown in Fig. 1(a), the two
terms of proportional and integral control signals are the
results produced by a resistor and a capacitor in series as
shown in Fig. 1(b), respectively. When a PFD detects a
phase error, it asserts UP or DN outputs in a way that their
net pulse width is proportional to the error. As these PFD
outputs control the activation of the UP and DN currents of
the CP, the net current fed into the RC filter would be
proportional to the phase error. This current gives rise to a
voltage across the resistor (Vproportional), of which net
contribution to the VCO phase is proportional to the
present phase error. Also, this current gives rise to a voltage across the capacitor (Vintergral), which is equal to the
integral of all the current fed to the filter, thus the sum of
the phase errors. The sum of Vproportional and Vintergral
determines the VCO frequency and phase.
In the proposed PLL, the FVC decreases/increases the
input voltage of the VCO. During the UP pulse, a CP
dumps the error charge to a capacitor Cp, giving rise to a
voltage equal to Vproportional ? Vintergral as shown in Fig. 2.
It increases the VCO frequency and then the output voltage
of FVC begins to decrease, leaving only the Vintergral on the
VCO. Therefore, the FVC works effectively as a resistor.
2.2 A single capacitor LF PLL with FVC
The proposed PLL as shown in Fig. 3(a) consists of a conventional PLL, in which the first-order LF of single capacitor
(Cp) and an FVC are used. The FVC generates a voltage
corresponding to the VCO output frequency at N/M times of
123
Fig. 2 a Conceptual block diagram. b Output signals of LF and FVC
and an effective VCO input voltage
Fref. The inner loop of the FVC and VCO is the negative
feedback closed loop which suppresses the VCO noise
independently from the outer PLL closed loop. When the
first-order LF is used, the PLL becomes unstable, but the PLL
with the FVC in Fig. 3 demonstrates stable operation
because the FVC works effectively as a resistor. The closed
and open loop transfer functions from Fig. 3(b) are as
follows
Ip 1 KVCO1
/o
2p sCp s
¼
/i 1 þ 1 Ip 1 KVCO1 þ N K KVCO2
N 2p sCp s
M sCy
2
1 Ip KVCO1 N 2p K KVCO2
1
HOL ¼
þ
N 2p s
M Ip Cy KVCO1 sCp
ð1Þ
ð2Þ
where Ip is the CP current, Cp is the single capacitor in LF,
N and M are the division ratio of the divider in PLL and
FVC loop, Kvco1 and Kvco2 are the gains of VCO for LF
and FVC, respectively.
The following Eq. (3) is the open transfer function of the
conventional PLL with the LF of serially connected one
capacitor (C) and one resistor (R).
1 Ip KVCO
1
HOL ¼
Rþ
ð3Þ
N 2p s
sC
From Eqs. (2) and (3), the effective R of the proposed PLL
can be assumed as follows
R¼
N 2 2p K KVCO2
:
M Ip Cy KVCO1
ð4Þ
Analog Integr Circ Sig Process (2013) 74:193–201
Fref
PFD
CP
195
VCO
LF
Fout
Kvco1
Kvco2
FVC
1
M
DIV
(a)
φi
+
−
⊕
I
1
sC p
p
2π
+
0
1
N
−
sφo
⊕
+
K VCO 1
s
K
1
sC y
⊕
φo
+
N
KVCO 2
s
1
M
Fig. 4 Closed loop transfer functions of a conventional PLL and a
single capacitor PLL with FVC
(b)
Fig. 3 Proposed PLL with FVC. a Block diagram and b linear model
The magnitude of effective R is easily changed by using
many variables in Eq. 4. The FVC creates a zero in Eq. (2),
which enables the PLL of single capacitor LF to operate
without any stability problems. The closed loop transfer
functions of a conventional and the proposed PLL are
plotted in Fig. 4 using the parameters the fabricated
(designed) PLL. Figure 4 shows how the FVC changes
the closed loop transfer function in the proposed PLL.
Peaking is shown in the conventional single capacitor LF
PLL, but the FVC removes the peaking in the close loop
transfer function of the proposed PLL. It narrows the
bandwidth, consequently, suppresses phase noises further.
As the gain of FVC increases, more phase noise is
suppressed as shown in Fig. 4.
Figure 5 shows the root locus of the proposed PLL. As
the FVC gain increases from 0 to infinity, poles on the
imaginary axis move to the left-half plane and back to the
origin on the imaginary axis. As the gain of FVC increases,
the proposed PLL becomes less stable, however, the FVC
enables the PLL of single capacitor LF to operate stably
with the reasonable FVC gain.
2.3 Dynamic response
In order to understand the dynamic behavior of the proposed PLL and analyze the noise behavior of blocks in
PLL, Eq. (1) is converted to Eq. (5)
/o
x2n
¼N 2
/i
s þ 2xn f s þ x2n
ð5Þ
where f is the damping factor and xn is the natural
frequency. f and xn are as follows:
Fig. 5 Root locus of PLL with FVC
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1 Ip 1
Kvco1
xn ¼
N 2p Cp
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2
N 3 2p K 2 Kvco2
:
f¼
Cp 2
2
M Ip
Cy Kvco1
ð6Þ
ð7Þ
When f\1, the phase and frequency step response of
the proposed PLL are as follows:
"
f
/o ðtÞ ¼ M/ N 1 pffiffiffiffiffiffiffiffiffiffiffiffiffi efxn t cos
1 f2
( qffiffiffiffiffiffiffiffiffiffiffiffiffi
!)#
f
2
1
pffiffiffiffiffiffiffiffiffiffiffiffiffi
xn 1 f t tan
ð8Þ
1 f2
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Analog Integr Circ Sig Process (2013) 74:193–201
φn,FVC
+
⊕
−
0
s
1
sC y
K
⊕
φn,VCO
KVCO 2
s
⊕
φo
φo
M
d
dt
1
M
Fig. 6 Linear model of FVC and VCO with intrinsic noise sources
Fig. 7 Linear model of proposed PLL with FVC
"
f
/o ðtÞ ¼ Mx N t pffiffiffiffiffiffiffiffiffiffiffiffiffi efxn t cos
1 f2
( qffiffiffiffiffiffiffiffiffiffiffiffiffi
!)#
f
2
1
pffiffiffiffiffiffiffiffiffiffiffiffiffi
xn 1 f t tan
1 f2
/o
/n;VCO
ð9Þ
Equations (8) and (9) show that the output of the
proposed PLL follows the phase and frequency change of
its input signal. The locking time of the proposed PLL
depends on the term of xn f which determines the decaying
envelope of sinusoidal transient response. In other words,
2xn f is the FVC loop gain as shown in the denominator of
Eqs. (1) and (5). The higher FVC loop gain, the shorter
locking time.
2.4 Noise analysis
The linear model of the closed loop of VCO and FVC is
shown in Fig. 6 and the transfer function of /o = /n;vco
and /o = /n;FVC are as follows:
/o
KVCO2
¼
/n;FVC s þ M1 CKy KVCO2
ð10Þ
/o
s
¼
:
/n;VCO s þ M1 CKy KVCO2
ð11Þ
Equations (10) and (11) show that /o = /n;VCO and
/o = /n;FVC have a high-pass and low-pass transfer function, respectively. The closed loop of VCO and FVC
suppresses the VCO noise which is usually the largest
among the noise sources in PLL. The FVC noise which has
a low-pass transfer function can be suppressed by designing a large gain FVC.
A linear noise model of the proposed PLL with FVC
depicting all the intrinsic noise sources is shown in Fig. 7.
The noise contribution of each block is considered to be an
additive noise source at the output of the block. The
transfer functions of various noise sources shown in Fig. 8
are as follows:
/o
KVCO2 s
¼
/n;FVC s2 þ 2xn f s þ x2n
123
ð12Þ
¼
s2
s2 þ 2xn f s þ x2n
ð13Þ
1
/o
Cp KVCO1
¼ 2
/n;CP s þ 2xn f s þ x2n
ð14Þ
/o
KVCO1 s
¼
/n;LF s2 þ 2xn f s þ x2n
ð15Þ
/o
/n;DIV
¼
Ip 1
2p Cp
KVCO1
s2 þ 2xn f s þ x2n
:
ð16Þ
These equations demonstrate the effectiveness of FVC
in noise suppression. The term of FVC in the denominator
of Eqs. (10) through (16) decreases the magnitude of the
transfer functions of various noise sources. The transfer
functions of each noise source are plotted in Fig. 8 using
the parameters in the fabricated (designed) PLL by
assuming that the magnitude of each noise is the same. In
Fig. 8, the magnitude of each noise depends on the magnitude of the transfer function of noises. As the gain of
FVC increases, the height of peaking decreases. The higher
the FVC gain, the greater the phase noise suppression.
Tradeoff is required between stability and noise suppression for the design of the proposed single capacitor LF PLL
with FVC.
3 Circuits
The FVC, a simplified FVC of [6], is shown in Fig. 9. The
gain of FVC, K, is as follows
K ¼ IFVC
Tout 1
2 K0 þ 1
ð17Þ
where IFVC is the supplying current to Cx, Tout is the
period of input signal, Fout, to MP, K’ is the ratio of Cx to
Cy. The control signals of a1 and a2 are non-overlapped.
When the Fout is at its low level, transistor MP is turned on
and Cx is charged. While a1 is high, switch SW is turned
on and the charge is transferred from Cx to Cy. While a2 is
Analog Integr Circ Sig Process (2013) 74:193–201
197
(a)
(b)
(c)
Fig. 9 FVC. a Circuit, b control signal block, and c control signal
timing
Fig. 8 Frequency-domain noise analysis of the proposed PLL with
FVC. a K/Cy = 0.0017 A s/F and b K/Cy = 0.017 A s/F. Magnitude
of each intrinsic noise sources is assumed to be the same
high, transistor MN is turned on and the remaining charge
of Cx is discharged to the ground. The FVC and the VCO
are connected to make a negative feedback closed loop as
shown in Fig. 3. As the frequency of Fout goes high, VFVC
goes low. As the frequency of Fout goes low, VFVC goes
high. Whenever the VCO output frequency varies, the FVC
works as a compensator and it suppresses the VCO noise.
The duty ratio of VCO can be changed from many variables such as process variations and ambient temperature.
The divider (M = 2) is used to give a 50 % duty ratio to
the input signal to FVC. The constant duty ratio is
important because it is capable of generating the proportional output voltage of the FVC according to the frequency of VCO.
The voltage controlled resistor (VCR) is used to control
the delay time of the VCO. The VCO used in the proposed
PLL has two VCRs for inputs from LF and FVC as shown
Fig. 10 VCR controlled VCO
in Fig. 10. The LF and FVC output voltage, Vctrl and VFVC,
are converted into a current used for controlling the delay
time of VCO through VCR. The VCR converts its input
voltage variation into a large current variation, and then it
generates a wide range of VCO frequencies. The VCO is
made of three differential delay cells which have full
output voltage swing and low output phase noise. A pair of
PMOS and NMOS transistors is added to the delay cell
to constitute CMOS latches. These latches give a short
on-time to the delay cells to exhibit low output phase noise.
A simple circuit of the CP in [7] is used.
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Analog Integr Circ Sig Process (2013) 74:193–201
4 Simulation results
Figure 11 shows the simulation results of the PLL of a
single capacitor LF and the proposed PLL of the single
250 pF capacitor LF with the FVC. It uses a 0.18 lm
CMOS process. The VCO has two designed gains of Kvco1
of 250 MHz/V and Kvco2 of 150 MHz/V for two inputs
from LF (VLF) and FVC (VFVC), respectively. It does not
require a large capacitor for low frequency zero in the
second-order LF of the conventional PLL. The PLL of a
single capacitor LF at VFVC = 0 V shows that it does not
lock (it is oscillating), but the proposed PLL with FVC
shows that it does lock as shown in Fig. 11(a)–(c). VFVC
moves to the opposite direction of VLF as shown in
Fig. 11(b), (c). Therefore, the effective VCO input voltage
can be assumed to be constant. It also proves that the FVC
works effectively as a resistor. Whenever the VCO output
frequency changes, the FVC works as a compensator.
5 Experimental results
Fig. 11 Simulation results. a without FVC, b VLF with FVC, and
c VFVC with FVC
Fig. 12 a Chip photograph, and
b layout of PLL with FVC
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The prototype single capacitor LF PLL with FVC is
implemented in 0.18 lm CMOS, and the chip photograph
is shown in Fig. 12. The lower layers of transistors and
capacitors are not seen because of the thick multi-intermetal layers. The die area is 860 lm 9 480 lm including
the capacitor of LF.
Analog Integr Circ Sig Process (2013) 74:193–201
199
Fig. 13 Measured VLF
Figure 13 shows the measured VLF as shown in Fig. 10.
It demonstrates process variations because the oscillating
frequency is different from the VLF in the Fig. 10(b).
Figure 14 shows the measured phase noise of proposed PLL
with the FVC. The measured phase noises are -88.3 and
-109 dBc/Hz at 1 and 10 MHz offset from the carrier
frequency of 752.7 MHz, respectively. The measured slope
is around 20 dB/dec from 100 kHz to 10 MHz and demonstrate almost the same slopes as shown in Fig. 4(a) which
is obtained by using Eq. (1). The measurement result shows
there are reference spurs. In fact, the large reference spurs
and the overall phase noise performance is not impressive.
The reference spur is assumed to be caused by the CP of [7]
which is very sensitive to current mismatch. A CP which
has a good current matching characteristic should improve
the reference spur.
Fig. 14 Measured phase noise
6 Merits of proposed single capacitor LF PLL
with FVC
The proposed single capacitor LF PLL with FVC is compared to the conventional second-order LF PLL to evaluate
the merits of the proposed PLL. The transfer functions of
each noise source in the conventional second-order LF PLL
are plotted in Fig. 15 by assuming that the magnitude of
each noise is the same. The parameters used here are same
as the ones of the proposed PLL except the LF parameters.
The LF parameters in the conventional second-order as
shown in Fig. 1(a) are Rz = 1 KX, Cz = 2.5 nF and
Cp = 250 pF. The parameters are determined to have a
Fig. 15 Frequency-domain noise analysis of the conventional secondorder LF PLL. Magnitude of each intrinsic noise sources is assumed to
be the same
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200
similar point of inflection in Figs. 8 and 15. Those two
figures show that the proposed PLL suppresses the VCO
noise, the largest noise source among the noise sources in
PLL, more than the conventional second-order LF PLL
does. The FVC and the VCO are connected to make a
negative feedback closed loop. Whenever the VCO output
frequency varies, the FVC works as a compensator and it
suppresses the largest VCO noise. The proposed PLL
reduces the largest VCO noise and the LF noise by
25–15 dB from 1 kHz to 100 kHz compared to the conventional second-order LF PLL as shown in Figs. 8 and 15.
The other noise sources, CP and divider noises, show no
suppression. The FVC noise is added as shown in Fig. 8,
but it is assumed to be much smaller than the VCO noise.
Therefore, the total noise of the proposed PLL would be
smaller than that of the conventional second-order LF PLL.
Furthermore, the size of the proposed PLL is much
smaller than the size of the conventional second-order LF
PLL because it does not require a low frequency zero
capacitor which is usually too large to be integrated into a
single chip. The capacitors used in FVC do not affect the
size of the proposed PLL as shown in Fig. 12. The proposed PLL is small enough to be integrated into a single
chip.
7 Conclusion
In this paper, we introduce a new architecture of secondorder PLL consisting of a single capacitor LF and an FVC.
The FVC works effectively as a resistor for stable operation of the proposed single capacitor LF PLL. The FVC
also changes the closed loop transfer function of the proposed PLL and shows the possibility of improving noise
characteristic unlike the previously published PLL which
has no resistor in LF. The noise characteristic would also
be better than that of the conventional second-order LF
PLL because the closed loop of VCO and FVC reduces the
largest VCO noise. Furthermore, the proposed PLL is small
enough to be integrated into a single chip. The measured
phase noise performance is not imposing, but we believe
that the proposed single capacitor LF PLL with the FVC
can be used as a frequency synthesizer or a clock generator.
Acknowledgments This work was supported by Basic Science
Research Program through the National Research Foundation of
Korea (NRF) funded by the Ministry of Education, Science and
Technology (2011-0007768).
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Analog Integr Circ Sig Process (2013) 74:193–201
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Jeong-hoon Nam received B.S.
degree in Electronics Engineering from Pukyong National
University in 2011, he is currently a graduate student in
Electronics Engineering from
Pukyong National University.
His current interests include
PLL and DLL design.
Young-Shig Choi received B.S.
degree in Electronics Engineering from Kyungpook National
University in 1982, M.S. degree
from Texas A&M University in
1986 and Ph.D. from Arizona
State University in Electrical
Engineering in 1993. From 1987
to 1999, he was with Hyundai
Electronics as a principal circuit
design Engineer where he has
been involved in the development of communication and
mixed signal chips. From 1999
to 2003, he was with Dongeui
University. In March 2003, he joined the faculty of Department of
Electronics Engineering, Pukyong National, where he is currently a
Professor. His current interests include PLL and DLL design.
Analog Integr Circ Sig Process (2013) 74:193–201
201
Moon G. Joo received the B.S.
degree in electronics and electric
engineering, the M.S. in computer
and communications engineering, and the Ph.D. in electrical
and computer engineering from
Pohang University of Science and
Technology, Pohang, Korea in
1992, 1994, and 2001, respectively. Dr. Joo was a senior
researcher at Research Institute of
Industrial Science and Technology, Pohang, Korea from 1996 to
2003. Since 2003, he has been a
professor of Pukyong National
University, Busan, Korea. His research interests include factory automation and intelligent control.
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