Introduction to
Phase Locked Loop
(PLL)
DIGITAVID, Inc.
Ahmed Abu-Hajar, Ph.D.
abuhajar@digitavid.net
Presentation Outline
What is Phase Locked Loop (PLL)
Basic PLL System
Problem of Lock Acquisition
Phase/Frequency Detector (PFD)
Charge Pump PLL
Application of PLL
What is Phase Locked Loop (PLL)
PLL is an Electronic Module (Circuit) that
locks the phase of the output to the input.
Vi(t)
Phase Locked
Loop
Vo(t)
Locked Vs. Unlocked Phase
Example of locked phase
Vi(t)
Vo(t)
Example of unlocked phase
Vo(t)
Vi(t)
Phase Error
( ∆φ)
Basic PLL System
PLL is a feedback system that detects the phase error ∆φ
and then adjusts the phase of the output.
Vi(t)
Phase Locked
Loop
Vo(t)
VI
∆φ
Phase
Detector
VCO
Vo
The Phase Detector (PD), detects ∆φ between the output
and the input through feedback system
Voltage Control Oscillator (VCO) adjusts the phase
difference
Implementation of PD
Phase Detector is an XOR gate
VI
V1
Vo
∆ϕ
Vo(t)
Vi(t)
Phase Error
( ∆φ)
∆φ
 1 VI ≠ Vo
= 
 0 VI = Vo
∆φ
Phase
Detector
VCO
Vo
What is VCO ?
VCO is a circuit module that oscillates at a
controlled frequency ω.
The Oscillating Frequency is controlled using
Voltage VControl.
–
That is why the module is called
Voltage Control Oscillator
VControl
VCO
ω
ω
ω0
VControl
ω = ωo + KVCO VControl
Vcontrol must be in the steady state for the VCO to
operate properly
Simple PLL
Structure
–
–
–
Phase Detector ( XOR ) that detects the phase error ∆φ
Low Pass Filter ( to smooth ∆φ )
Voltage Control Oscillator (VCO)
Basic Idea
–
If VI and Vout are out of phase (unlocked), then the PD module
detects the error and the LPF smoothes the error signal. The
control signal slows down or speeds up the VCO module; hence,
the phase is corrected (locked)
VI
Vout
∆φ
Phase
Detector
LPF
VControl
∆φ
VCO
Vout
Locked Condition
–
Locked Condition
d
(ϕin − ϕout ) = 0
dt
–
This implies that
ωin = ωout
VI
Vout
∆φ
Phase
Detector
LPF
VControl
∆φ
VCO
Vout
Example: In the UNLOCKED State
VI and Vout has ∆φ at the same
Vi(t)
frequency ω1
Vo(t)
The phase detector must
Phase Error
produce VI
( ∆φ)
Hence, VCO is dynamically
changing and PD is creating VControl
VControl to adjust for the phase
difference.
ω
ω1
The PLL is in the Locked state
VControl
V1
ω0
φ0
V1
VControl
In the UNLOCKED State
For Simplicity and by using Fourier Series
Let
Due to ∆φ, PD creates Vcontrol
VCO will change
VI = VA cos (ω1t )
Vout = VB cos (ω1t + ϕo )
ωout = ω1 + KVCO VControl
The output voltage becomes
Vout = VB cos (ω1t + ϕo − ∆ϕ (t ) )
Dynamics of Simple PLL
PLL is a feedback system
–
–
–
PD is a gain amplifier
LPF be first order filter ( as an example)
VCO is a unit step module
The transfer function of the feedback system is given as:
Φ out
ωout
ωn2
H ( s) =
( s) =
( s) = 2
ωin
s + 2ςωn s + ωn2
Φ in
H ( s) =
LPF
PD
φin
VCO
1
KPD
1+
s
ωLPF
KVCO
s
φout
K PD KVCOωLPF
s 2 + ωLPF s + K PD KVCOωLPF
Transient Response to PLL
The unit step response to second order system
–
–
–
Overdamped
Critically damped
Underdamped
ωi
Problems with this PLL
–
–
–
Settling time Vs. ripple of Vcontor
Stability of the system
Lacks performance in ICs
t
ωout
Φ out
ωout
ωn2
H ( s) =
( s) =
( s) = 2
ωin LPF s + 2ςωn s + ωn2
Φ in
PD
φin
VCO
1
KPD
1+
s
ωLPF
KVCO
s
t
φout
Problem of Lock Acquisition
When PLL is turned on, the output frequency is far from
the input frequency
It is possible that the PLL would never lock
Modern PLL uses FREQUENCY DEDECTOR (FD) in
addition to the PD.
PD
LPF1
Vin
ωin
VCO
FD
LPF2
Vout
ωout
Phase/Frequency Detector (PFD)
One Module that detects both frequency and phase differences
This module senses the transition in A or B
Initially
A leads B
Initially
B leads A
QB
QA
A
0
01
XX
A
0
00
0
1
B
0
00
01
QA
0
01
10
QB
0
00
00
B
0
0 1
XX
QA
0
00
00
QB
0
0 1
0 0
A
B
If A leads B, QA changes its state and QB remains unchanged
If B leads A, QB changes its state and QA remains unchanged
A
A
B
B
QB
QA
PFD
QA
QB
Hardware Implementation of PFD
Uses two Edge Triggering modules
using D-FF
If A leads to “1” QA = “1”
–
–
When B becomes “1”, QB = “1”
momentarily
The AND gate RESETs Both to Qs “0”
VDD
D
QA
Q
A
CK
VDD
D
If B leads to “1” QB = “1”
–
–
When A becomes “1”, QA = “1”
momentarily
The AND gate RESETs Both to Qs “0”
Q
B
CK
QB
Hardware Implementation of PFD
VDD
A
D
B
QA
Q
QB
A
CK
QA
VDD
RES
RES
D
A
Q
B
CK
QB
B
QB
QA
RES
The Vout is the average of (QA – QB)
is used to detect the phase and the
frequency difference
The Basic Block diagram
VDD
Structure
– PFD
– LPF
Vin
– Differential
φin
Amplifier
ωin
– VCO
– Negative Feedback V
DD
Disadvantage:
Sensitive to noise
and offset voltages,
ripple Vcontrol, ..
Use Charge Pump
PLL
D
Q
QA
CK
VCO
D
Q
Vout
φout
ωout
CK
QB
Charge Pump PLL
Structure
– PFD
– Two switches
controlled by QA
and QB
– Capacitor
d VC
dt
d VC
I
= C
dt
C
IC = C
–
–
–
VCO
Negative Feedback
It charges or
discharges the
capacitor
indefinitely
VDD
VDD
D
Vin
φin
ωin
Q
QA
CK
VDD
VCO
D
Q
Vout
φout
ωout
CK
QB
Charge Pump PLL
The capacitor is replaced
with a LPF (Cp and Rp) to
improve the phase margin
for stability
The transfer function of the
system is approximated as
follows:
I P KVCO
( RPCP s + 1)
2π CP
H (s) =
I
I K
s 2 + P KVCO RP s + P VCO KVCO
2π
2π CP
Rp slows down the system
VDD
VDD
D
Vin
φin
ωin
Q
QA
CK
VDD
VCO
CP
D
Q
Vout
φout
ωout
CK
RP
QB
Application of PLL
Frequency Multiplications
–
–
The feedback loop has frequency division
Frequency division is implemented using a counter
VI
PFD
∆φ
LPF
VControl
∆φ
Counter
(Frequency
Division)
Clock Skew Reduction
Buffers are used to distribute
the clock
Embed the buffer within the loop
VCO
Vout
Application of PLL
Clock Skew Reduction
–
–
Buffers are used to distribute the clock
Embed the buffer within the loop
VI
PFD
∆φ
Vout
Jitter Reduction
LPF
VControl
∆φ
VCO
Vout
Buffer