MachXO2 Hardware Checklist
April 2015
Technical Note TN1208
Introduction
When designing complex hardware using the MachXO2™ PLD, designers must pay special attention to critical
hardware configuration requirements. This technical note steps through these critical hardware requirements
related to the MachXO2 device. This document does not provide detailed step-by-step instructions but gives a
high-level summary checklist to assist in the design process.
The MachXO2 ultra-low power, instant-on, non-volatile PLDs are available in three versions – ultra low power (ZE)
and high performance (HC and HE) devices. HC devices have an internal linear voltage regulator which supports
external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only accept 1.2 V as the external VCC supply
voltage. With the exception of power supply voltage, all three types of devices (ZE, HC and HE) are functionally
and pin compatible with each other.
This technical note assumes that the reader is familiar with the MachXO2 device features as described in DS1035,
MachXO2 Family Data Sheet.
The critical hardware areas covered in this technical note include:
• Power supplies as they relate to the MachXO2 supply rails and how to connect them to the PCB and the associated system
• Configuration and how to connect the configuration mode selection for proper power up configuration
• Device I/O interface and critical signals
Important: Users should refer to the following documents for detailed recommendations.
• TN1068, Power Decoupling and Bypass Filtering for Programmable Devices
• TN1198, Power Estimation and Management for MachXO2 Devices
• TN1202, MachXO2 sysIO Usage Guide
• TN1203, Implementing High-Speed Interfaces with MachXO2 Devices
• TN1204, MachXO2 Programming and Configuration Usage Guide
• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
Power Supply
The VCC and VCCIO0 power supplies determine the MachXO2 internal “power good” condition. These supplies
need to be at a valid and stable level before the device can become operational. In addition, there are VCCIO1-5
supplies that power the remaining I/O banks. Table 1 shows the power supplies and the appropriate voltage levels
for each.
Refer to DS1035, MachXO2 Family Data Sheet for more information on the voltage levels.
Table 1. Power Supply Description and Voltage Levels
Supply
VCC
VCCIOx
Voltage (Nominal Value)
1.2 V
2.5 V/3.3 V
1.2 V to 3.3 V
Description
Core power supply for 1.2 V devices (ZE and HE)
Core power supply for 2.5 V/3.3 V devices (HC)
Power supply pins for I/O Bank x. There are up to five I/O banks.
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TN1208_1.7
MachXO2 Hardware Checklist
Power Estimation
Once the MachXO2 device density, package and logic implementation is decided, power estimation can be performed using the Power Calculator tool which is provided as part of the Lattice Diamond® design software. While
performing power estimation the user should keep two specific goals in mind.
1. Power supply budgeting should be considered based on the maximum of the power-up in- rush current, configuration current or maximum DC and AC current for a given system environmental condition.
2. The ability of the system environment and MachXO2 device packaging to support the specified maximum operating junction temperature.
By determining these two criteria, system design planning can take the MachXO2 power requirements into consideration early in the design phase.
This is explained in TN1198, Power Estimation and Management for MachXO2 Devices.
Configuration Considerations
MachXO2 devices contain two types of memory, SRAM and Flash. SRAM is volatile memory and contains the
active configuration. Flash is non-volatile memory that provides on-chip storage for the SRAM configuration data.
The MachXO2 includes multiple programming and configuration interfaces:
• 1149.1 JTAG
• Self download
• Slave SPI
• Master SPI
• Dual Boot
• I2C
• WISHBONE bus
For ease of prototype debugging it is recommended that every PCB should have easy access to the programming
and configuration pins.
The configuration logic arbitrates access from the interfaces by the following priority. When higher priority ports are
enabled, Flash Memory access by lower priority ports will be blocked.
1. JTAG Port
2. Slave SPI Port (SN low activates the SPI port)
3. I2C Primary Port
Note: Erased device have all programming and configuration ports enabled by default. When the device is erase
ensure SN and ProgramN are not driven low.
For a detailed description of the programming and configuration interfaces please refer to TN1204, MachXO2 Programming and Configuration Usage Guide.
The use of external resistors is always needed if the configuration signals are being used to handshake with other
devices. Pull-up and pull-down resistor (4.7K) recommendations on different configuration pins are listed below.
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MachXO2 Hardware Checklist
Table 2. Default State of the sysCONFIG Pins
Pin Name
PROGRAMN
Pin Function
(Configuration Mode)
PROGRAMN
Pin Direction
(Configuration Mode)
Default Function
(User Mode)
Input with weak pull-up, external pullup to VCCIO0.
PROGRAMN
INITN
I/O
I/O with weak pull-up
User-defined I/O
DONE
I/O
I/O with weak pull-up, external pullup to VCCIO0.
User-defined I/O
SSPI
Input with weak pull-up. MCLK function requires
external 1kOhm pull-up.
User-defined I/O
MCLK/CCLK
SN
SSPI
Input with weak pull-up, external pull-up to VCCIO2.
User-defined I/O
SI/SPISI
SSPI
Input
User-defined I/O
SO/SOSPI
SSPI
Output
User-defined I/O
CSSPIN
I/O
I/O with weak pull-up, external pullup to VCCIO2.
User-defined I/O
SCL
I2C
Bi-Directional open drain, external pull-up, noise filUser-defined I/O
ter (200 Ohm series/100pF to GND).
SDA
I2C
Bi-Directional open drain, external pull-up, noise filUser-defined I/O
ter (100 Ohm series/100pF to GND).
TDI
TDI
Input with weak pull-up
TDI
TDO
TDO
Output with weak pull-up
TDO
TCK
TCK
Input. Recommended 4.7kOhm pull down.
TCK
TMS
TMS
Input with weak pull-up
TMS
Input with weak pull-down
I/O
JTAGENB
I/O
Master SPI
When configuring from an external SPI Flash, ensure:
• The SPI Flash VCC and the MachXO2 VCCIO2 are at the same level.
• The SPI Flash VCC meets is at the vendor’s data sheet recommended operating level.
• The SPI Flash POR level is lower than the MachXO2 POR level.
— If the SPI Flash POR is higher than the MachXO2 POR refer to TN1204, MachXO2 Programming and Configuration Usage Guide.
PROGRAMN Initial Power Considerations
The MachXO2 PROGRAMN is permitted to become a general purpose I/O. The PROGRAMN only becomes a
general purpose I/O after the configuration bitstream is loaded. When power is applied to the MachXO2 the PROGRAMN input performs the PROGRAMN function. It is critical that any signal input to the PROGRAMN have a
high-to-low transition period that is longer than the VCC (min) to INITN rising edge time period. Transitions faster
than this time period prevent the MachXO2 from becoming operational. Refer to the description of PROGRAMN in
TN1204, MachXO2 Programming and Configuration Usage Guide.
Pin-out Considerations
The MachXO2 PLDs support many applications with high-speed interfaces. These include various rule-based pinouts that need to be understood prior to the implementation of the PCB design. The pin-out selection must be completed with an understanding of the interface building blocks of the FPGA fabric. These include IOLOGIC blocks
such as DDR, clock resource connectivity, and PLL usage. Refer to TN1203, Implementing High-Speed Interfaces
with MachXO2 Devices for rules pertaining to these interface types.
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MachXO2 Hardware Checklist
True-LVDS Output Pin Assignments
True-LVDS outputs are on the top bank (Bank 0) of the MachXO2-1200 and higher density devices. When using
the LVDS outputs, a 2.5 V or 3.3 V supply needs to be connected to the Bank 0 VCCIO supply rails. Refer to
TN1202, MachXO2 sysIO Usage Guide for more information on this.
HSTL, SSTL and Referenced LVCMOS Pin Assignments
The externally-referenced I/O standards (HSTL and SSTL) and internally referenced LVCMOS require an external
reference voltage. Each I/O bank supports one reference voltage (VREF). Any I/O in the bank can be configured as
the input reference voltage pin. This pin is a regular I/O if it is not used as a reference voltage input. The VREF
pin(s) should get the highest priority for pin assignment. The input reference voltage can also be generated internally from the VREF generator. Again, there is one VREF generator per bank and its programmable settings
include OFF, 45% of VCCIO, 50% of VCCIO, and 55% of VCCIO. Programming of the internal VREF generator and
the external VREF pin cannot be set at the same time for a particular bank since there is only one VREF per bank.
PCI Clamp Pin Assignment
PCI clamps are available on the bottom I/O bank (Bank 2) of the MachXO2-1200 and higher density devices. When
the system design calls for PCI clamp, these pins should be assigned to I/O Bank 2. For the clamp characteristic,
refer to the IBIS buffer models either on the Lattice web site or in the Lattice Diamond design software.
Checklist
MachXO2 Hardware Checklist Item
1
Power Supply
1.1
Core Supply VCC at 1.2 V
1.2
Core Supply VCC at 2.5 V or 3.3 V
1.3
I/O power supply VCCIO 0-5 at 1.2 V to 3.3 V
1.4
Power Estimation
2
Configuration
2.1
Configuration options
2.2
Pull-up on PROGRAMN, INITN, DONE
2.3
Pull-up on SPI mode pins
2.4
Pull-up on I2C mode pins
2.5
JTAG default logic levels
2.6
PROGRAMN high-to-low transition time period is larger than the VCC
(min) to INITN rising edge time period
3
I/O pin assignment
3.1
True LVDS pin assignment considerations
3.2
HSTL, SSTL and referenced LVCMOS pin assignment considerations
3.3
PCI clamp requirement considerations
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
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MachXO2 Hardware Checklist
Revision History
Date
Version
April 2015
1.7
Change Summary
Updated Master SPI section. Revised the third item to consider when
configuring from an external SPI Flash.
Updated Technical Support Assistance section.
June 2014
1.6
Updated Master SPI section.
January 2014
01.5
Updated Configuration Considerations section. Defined termination for
SN and ProgramN when the device is erased.
September 2013
01.4
Updated CSSPIN information in Default State of the sysCONFIG Pins
table.
August 2013
01.3
Added access priority information to the Configuration Considerations
section.
Added requirement of including a 1 kOhm pullup on SN.
Added information on configuring from an external SPI Flash.
Updated Technical Support Assistance information.
Updated the Default State of the sysCONFIG Pins table.
September 2012
01.2
Added PROGRAMN Initial Power Considerations section.
Added item 2.6 to the Checklist table.
June 2012
01.1
Updated document with new corporate logo.
Added external pull-up requirement on SPI signals and updated Configuration Considerations section.
April 2011
01.0
Initial release.
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