NOC: Networks on Chip
MPSoC:Multiprocessor System on Chip
EE8205: Embedded Computer Systems
http://www.ee.ryerson.ca/~courses/EE8205/
Dr. Gul N. Khan
http://www.ee.ryerson.ca/~gnkhan
Electrical and Computer Engineering
Ryerson University
Overview
• Introduction to SoC and MPSoC
• Networks on a Chip
• Bus-based and Point-to-point NoC Systems
• Regular and Application Specific NoC Topologies
• Routing and Switching Techniques
• NOC Topology Generation and Analysis
Introductory Articles on MPSoC and NoC available at the course webpage
System on a Chip
Systems-on-Chip (SoC)
• Advances in chip design and integration.
• Incorporate multiple components on a single chip.
• MPSoC has addressed ever-increasing performance
requirements.
Samsung S3C6400
Platform
NOC and SOC Design
2
Samsung S3C6410 Platform
NOC and SOC Design
3
S3C6410 System on Chip
• A 16/32-bit RISC low power, high performance micro-processor
• Applications include mobile phones, Portable Navigation
Devices and other general applications.
• Provide optimized H/W performance for the 2.5G and
3G communication services,
• Includes many powerful hardware accelerators for motion
video processing, display control and scaling. An
• Integrated Multi Format Codec (MFC) supports encoding and
decoding of MPEG4/H.263, H.264.
• Many hardware peripherals such as camera interface, TFT 24-bit
LCD controller, power management, etc.
NOC and SOC Design
4
ARM 11 (v6) based SOC
NOC and SOC Design
5
S3C6410 based Mobile Processor
Navigation
System
iPhone based
on
ARM1176JZ
S3C6410
NOC and SOC Design
6
System on Chip Design Flow
• Specify:
* What does the customer really want?
• Architect:
* Find the most cost and performance effective architecture
to implement it?
* What existing components can we adapt and re-use?
• Evaluate:
* What is the performance impact of a cheaper architecture?
• Implement:
* What can we generate automatically from libraries and
customization?
Use separate computation, communication and performance
NOC and SOC Design
7
System-on-Chip and NoC
System-on-Chip ---to--- Network-on-Chip
CPU
MPEG CORE
DSP
VGA CORE
Analog
ADC/DAC
NOC and SOC Design
Component
8
SoC Structure
NoC-based System on a Chip
A
A tile
tile of
of the
the chip
chip
Cache L2
Proc
control
control
p2
Proc
Proc
Switch
Fabric
p3
data
data
p1
Control
Logic
parity
parity
spare
spare
p0
p4
Network
Interface
Data $
Instr $
Switch
Fabric
Control
Logic
core
p0
Network
Interface
Data $
p1
bus
p3
Instr $
core
A communication link
A computational block
NOC and SOC Design
9
System on Chip Design Flow
1
System
Architecture
System
Behavior
Behavior
Simulation
2
Mapping
3
Performance
Simulation
Communication
Refinement
Flow To Implementation
NOC and SOC Design
4
10
System on Chip Design Flow
o
Performance
Simulation
behavior annotated with
architectural effects
p
Analyze / Visualize
Results
NOC and SOC Design
n
Annotation of
architectural timing and
Energy onto behavior
11
SoC Appl.- Wireless LAN Physical Layer
Protocol Stack
HiperLan/2
PicoRadio
Application
Ad Hoc Networks:
Low Rate: b/sec - kb/sec
Low Power: 100μW
Network
MAC
Multi-media Wireless
Networks;
High Rate: 10 Mb/sec
Low Power: 10-100 mW
OFDM Physical
Layer/Digital BB
OFDM RX
OFDM TX
Dynamic
Reconfiguration
NOC and SOC Design
12
Wireless LAN SoC
Analog front end
Analog front end
ASIC
FPGA
AD
Digital
Modem
AD
AD
AD
PA
sleep mode
mngmt
clock
manager
DA
bus
PA
DA
Microcontroller
Bloc
User
Interface
•
•
•
•
•
•
•
•
**-Main Points-**
Which micro-controller to use?
Do we need more FPGAs?
DSP or ASIC?
Which MAC?
Where will the MAC run?
Which other appls. can I add?
Is the chip reusable?
Is too much memory?
NOC and SOC Design
Protocol
Analog front end
f0
Turbo
Codec
f1
f2
FPGA
AD
AD
crossbar bus
PA
DA
Micro-controller
13
Wireless LAN Physical Layer Design Flow
Higher Layers
OFDM Physical
Layer
OFDM RX
OFDM TX
SystemC
Functional
IP Reuse
Functional
Partitioning
TX
RX
Application Specification
English (UML, SystemC…)
Algorithm Exploration
SystemC or C (Matlab/Simulink, …)
Functional Simulation
and Refinement
Coware (….)
Architecture Exploration:
Performance Simulation
Coware(, …)
Mapping
Mapping
Architecture Refinement
Implementation
NOC and SOC Design
14
Physical Layer SoC Architecture
FPGA
FFT FIR UART
BUFFER
XBAR
Interface
XBAR
FPGA
config. mem.
Int. bridge
DPR2/SPS2
Bridge
Processor bus
Interface
Processor bus
Ck, reset
-
I/D
Micro
caches
Jtag
Interface
Reset CK2 CK1
NOC and SOC Design
Clock
gen.
Datapath
SPS2
(instruction/
data RAM)
MCK VDD VSS TEST(0..2)
15
Multiple Processor/Core System-onChip
Inter-node communication between CPU/cores can be performed
by message passing or shared memory. Number of processors in
the same chip-die increases at each node (CMP and MPSoC).
• Memory sharing will require: SHARED BUS
* Large Multiplexers
* Cache coherence techniques
* Not Scalable
• Message Passing: NOC
* Scalable
* Require data transfer transactions
* Has overhead of extra communication
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16
NOC: Network-on-Chip
System Bus
Shared bus is not a
long-term solution
• It has poor scalability
On-Chip micro-networks suit the
demand of scalability and performance
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17
NOC and Off-Chip Networks
NOC
Off-Chip Networks
Š Sensitive to cost:
ƒ area and power
Š Wires are relatively cheap
Š Latency is critical
Š Traffic is known a-priori
Š Design time specialization
Š Custom NoCs are possible
Š Cost is in the links
NOC and SOC Design
Š Latency is tolerable
Š Traffic/applications
unknown
Š Changes at runtime
Š Adherence to networking
standards
18
On-Chip Communication Structures
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19
On-Chip Bus Interconnection
For highly connected multi-core system
„
Communication bottleneck
For multi-master buses
„
Arbitration will become a complex problem
Power grows for each communication event as
more units attached will increase the capacitive
load.
A crossbar switch can overcome some of these
problems and limitations of the buses
„
Crossbar is not scalable
NOC and SOC Design
20
SOC Communication Structures
Dedicated Point-to-Point
• Advantages
„ Optimal in terms of bandwidth, availability,
latency and power usage
„ Simple to design and verify as well as easier to
model
• Disadvantages
„ Number of links may increase exponentially
with the increase in number of cores
„ Hardware Area
„ Routing Problems
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21
SOC Communication Structures
Network on Chip
• Advantages
„
„
„
„
Structured architecture – Lower complexity and cost
of SOC design
Reuse of components, architectures, design methods
and tools
Efficient and high performance interconnect.
Scalability of communication architecture
• Disadvantages
„
„
„
Internal network contention can cause a latency
Bus oriented IPs need smart wrapping hardware
Software needs clear synchronization in
multiprocessor systems
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22
Networks-on-Chip
• Interconnect for SoCs, CMPs, MPSoC and
FPGAs
„ Multi-hop, packet-based communication
„ Efficient resource sharing
• Scalable communication infrastructure
provides scalable performance/efficiency in
„ Power
„ Hardware Area
„ Design productivity
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23
Networks-on-Chip
• Interconnect for SoCs, CMPs, MPSoC and
FPGAs
„ Multi-hop, packet-based communication
„ Efficient resource sharing
• Scalable communication infrastructure
provides scalable performance/efficiency in
„ Power
„ Hardware Area
„ Design productivity
NOC and SOC Design
24
NoC ?
A chip-wide network: Processing Elements (PEs) are interconnected via a packet-based network in NoC Architecture
Packetized Message
ROUTER
ROUTER
ROUTER
ROUTER
MSG
PE 1
text
text
PE 2
text
PE 3
text
PE 4
ROUTER
ROUTER
ROUTER
ROUTER
text
PE 5
text
PE 6
text
PE 7
text
PE 8
ROUTER
ROUTER
ROUTER
ROUTER
text
PE 9
text
PE 10
text
PE 11
text
PE 12
ROUTER
ROUTER
ROUTER
ROUTER
text
PE 13
text
PE 14
text
PE 15
PE 16
MSG
text
Decoded Message
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25
Network-on-Chip vs. Bus Interconnection
• Total bandwidth grows
• Link speed unaffected
• Concurrent spatial reuse
• Pipelining is built-in
• Distributed arbitration
• Separate abstraction layers
However
• No performance guarantee
• Extra delay in routers
• Area and power overhead?
• Modules need NI
• Unfamiliar methodology
NOC and SOC Design
BUS inter-connection is fairly
simple and familiar
However
• Bandwidth is limited, shared
• Speed goes down as N grows
• No concurrency
• Pipelining is tough
• Central arbitration
• No layers of abstraction
(communication and
computation are coupled)
26
On-Chip Buses
• Ad hoc Buses
Traditional Data/Address Buses
• ARM AMBA Bus
Advanced Micro controller Bus Architecture
• IBM Core Connect Bus
CoreConnect Bus Architecture
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27
AMBA On-Chip Bus
AMBA evolved from ARM’s internal bus development:
• ASB/AHB: Advance System Bus/High Performance bus
with support for pipelining, burst transfer and multiple
bus masters
• APB: Advance Periphral Bus with all slave devices
• Bridge: A slave on ASB that connect it to APB
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28
AMBA based Single Chip GPS Controller
■ Suitable for handheld
and personal navigation
systems
■ ARM7TDMI 16/32 bit
RISC CPU based host
■ Complete embedded
memory system: Flash
256 KB, RAM 64 KB.
■ 12 channel GPS
correlation DSP
■ 4 channels A/D
■ 4 serial communication
interfaces
■ One serial peripheral
interfaces (SPI)
■ Real-time clock module
■ 16-bit watchdog timer
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29
IBM CoreConnect On-Chip Bus
CoreConnect is an SOC Bus proposed by IBM having:
• PLB: Processor Local Bus, PLB Arbiter, PLB to OPB Bridge
• OPB: On-Chip Peripheral Bus, OPB Arbiter
• DCR: Device Control Register Bus and a Bridge
NOC and SOC Design
30
CoreConnect Advance Features
IBM CoreConnect Bus with 32-, 64-, and 128-bit versions to
support a variety of applications
• PLB: Fully synchronous, supports up to 8 masters
- Separate read/write data buses
- Burst transfers, variable and fixed-length, Pipelining
- DMA transfers and No on-chip tri-states required
- Overlapped arbitration, programmable priority fairness
• OPB: Fully synchronous, 32-bit address and data buses
- Support 1-cycle data transfers between master and slaves
- Arbitration for up to 4 OPB master peripherals
- Bridge function can be master on PLB or OPB
• DCR: Provides fully synchronous movement of GPR data
between CPU and slave logic
NOC and SOC Design
31
CoreConnect Bus based SoC
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32
Comparing AMBA and
CoreConnect SoC Buses
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33
NoC: Buses to Networks
Original Bus Features
•
•
•
•
•
One transaction at a time
Central Arbiter
Limited bandwidth
Synchronous
Low cost
Shared Bus to Segmented Bus
S
S
NOC and SOC Design
34
Advanced Bus
Segmented Bus
•
•
•
•
•
•
More General/Versatile
bus architecture
Pipelining capability
Burst transfer
Split transactions
Overlapped arbitration
Transaction preemption,
resumption & reordering
Shared Bus to Segmented Bus
S
S
NOC and SOC Design
35
Buses to Networks
• Architectural paradigm shift: Replace wire spaghetti by network
• Usage paradigm shift: Pack everything in packets
• Organizational paradigm shift
ƒ Confiscate communications from logic designers
ƒ Create a new discipline, a new infrastructure responsibility
NOC and SOC Design
36
NoC Related Main Problems
Global interconnect design problems:
• Delay
• Power
• Noise
• Scalability
• Reliability
System integration
Productivity problem
Chip Multi Processors
For power-efficient computing
NOC and SOC Design
37
NoC and Global Connections Delay
Long wiring delay is dominated by Resistance
•
•
•
Add repeaters
Repeaters will become latches
(with clock frequency scaling)
Latches can become NoC routers
NoC
router
NOC and SOC Design
NoC
router
NoC
router
38
NoC: Long Wiring Delays
Long wiring delay is dominated by Resistance
•
•
•
Add repeaters
Repeaters will become latches
(with clock frequency scaling)
Latches can become NoC routers
NoC
router
NOC and SOC Design
NoC
router
NoC
router
39
NoC Wiring Design
• NoC links:
–
–
–
–
Regular
Point-to-point -- no fan-out tree (problem)
Can use transmission-line layout
Well-defined current return path
• Can be optimized for noise / speed / power
– Low swing, current mode, ….
NOC and SOC Design
40
NoC Scalability
Compare the wire-area for same performance
d
d
n
d
d
NoC:
O ( n)
n
n
Bus
O n3 n
(
)
n
d
n
d
Pt-to-Pt:
O n2 n
(
)
NOC and SOC Design
Segmented
Bus:
2
O n n
(
)
n
41
NoC a Platform
Š System modules may use
different clocks/voltages.
Š NoC can take care of
synchronization.
Š NoC design may be
asynchronous.
Š No waste of power when
NoC platform for System
Integration, Testing and
Debugging
links/routers are idle.
Š It eliminates ad-hoc global
wire engineering.
Š It separates computation
from communication.
Š It supports modularity &
reuse of cores.
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42
CMP and NoC
• Uniprocessors cannot provide
Power-efficient performance growth
ƒ Interconnect dominates dynamic power
ƒ Global wire delay doesn’t scale
ƒ Instruction-level parallelism is limited
• Power-efficiency requires many parallel
local computations
ƒ
ƒ
Chip Multi Processors (CMP)
Thread-Level Parallelism (TLP)
Uni-processor
dynamic power
(Magen et al., SLIP 2004)
Gate
Interconnect
Diff.
Uni-processor Performance
Network is another choice for CMP
“Pollack’s rule”
(F. Pollack. Micro 32, 1999)
NOC and SOC Design
Die Area (or Power)
43
Network-on-Chip Topologies
Application Specific Irregular Topologies
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44
Irregular NoC Topologies
• Based on the concept of using only what is
necessary.
• Application-specific topologies.
• Eliminate unneeded resources and bandwidth
from the system.
• Leads to reduced power and area use.
• Requires additional design work.
NOC and SOC Design
45
NOC Topology
1
2
3
4
1
2
3
4
5
6
7
8
5
6
7
8
9
10
11
12
9
10
11
12
13
14
15
16
13
14
15
16
Mesh
NOC and SOC Design
Physical implementation
46
NOC Torus Topology
1
2
4
3
13
14
16
15
1
2
3
4
5
6
7
8
9
10
11
12
5
6
8
7
13
14
15
16
9
10
12
11
Torus
NOC and SOC Design
Physical implementation
47
NOC Abstraction Layers Network Modeling
Software Layers
ƒ
O/S, application
Network and Transport Layers
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Network topology e.g. crossbar, ring, mesh, torus, fat tree,…
Switching Circuit / packet switching: VCT, wormhole
Addressing Logical/physical, source/destination, flow, transaction
Routing
Static/dynamic, distributed/source, deadlock avoidance
Quality of Service e.g. guaranteed-throughput, best-effort
Congestion control, end-to-end flow control
Data Link Layer
ƒ
ƒ
ƒ
Flow control (handshake)
Handling of contention
Correction of transmission errors
Physical Layer
ƒ
Wires, drivers, receivers, repeaters, signaling, circuits,..
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48
Definitions and Terminology
Switch: The component of the network that is in charge
of flit routing.
Flit Latency: The time needed for a FLIT to reach its
target PE from its source PE.
Packet Latency: The time needed for a PACKET to
reach its target PE from its source PE.
Packet Spread: The time from the reception of the first
flit of a packet to the reception of the last one.
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49
Message Abstraction
Packet: An element of information that a processing element
(PE) sends to another PE. A packet may consist of a variable
number of flits.”
Flit: The elementary unit of information exchanged in the
communication network in a clock cycle.
Message
Header
Payload
Packet
NOC and SOC Design
Tail
Type
VC
Body
Type
VC
Flit
Type
VC
Dest.
50
Switching Techniques
Circuit Switching
Packet Switching – Routing Protocols
Store and Forward: Router cost is packet based. Packet size
also affects latency and buffering requirements. Stalling happens
at two nodes and the link between them.
Wormhole: Router cost is based on header. Header can effect
latency and buffering at the router is based on the header size.
Stalling can happen at all the nodes and links spanned by the
packet..
Virtual Cut-through: Router cost depends on header and
packet size. Stalling at local nodes level.
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51
Relevant Parameters: Routing
ƒ Minimum latency is of paramount importance in
NOC/SOC (inter-process communication).
ƒ Ideally: 1 clock latency per switch/router (flit enters
at time t and exits at t+1)
ƒ Maximum switch clock frequency (technology +
routing logic limits)
ƒ Deadlock free
ƒ No flits are ever lost; once a flit is injected in the
NOC, it must reach its destination may be after a long
time.
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52
Fixed Shortest Path Routing
Suitable for Regular Topologies
e.g. Mesh, Torus, Tree, etc.
X-Y routing (fist x then y
direction.
ƒ Simple Router
ƒ No deadlock scenario
ƒ No retransmission
ƒ No reordering of messages
ƒ Power-efficient
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53
Wormhole Routing
In wormhole routing a header flit “digs” the
path and hold.
Successive flits are routed to the same path or
direction
In case of blocks and loss-less NoC we need:
Buffers
A back-pressure mechanism if we don’t have
infinite size FIFOs…
‰
‰
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54
Wormhole
Src
Dest
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55
Wormhole
T F FF
Src
F 4 3 2
H
F
Dest
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56
Wormhole
T F F F
Src
F 4 3 2
H
F
Dest
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57
Wormhole
T F F
Src
F 4 3
F
2
HF
Dest
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58
Wormhole
T F
SrcF 4
F
3
F2
HF
Dest
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59
Wormhole
T
Src F
F F
4 3
F2
HF
Dest
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60
Wormhole
T
Src F
F F
4 3
F2
HF
Dest
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Wormhole
T
Src F
F
4
F3
F2
Dest
HF
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Wormhole
Src
T
F
F4
F3
Dest
F2
HF
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Wormhole
Src
TF
F4
F3
Dest
F2
HF
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Wormhole
Src
TF
F4
F3
Dest
F2
HF
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65
Wormhole
Src
TF
F4
F3
Dest
F2
HF
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66
Deflection Routing
Hot Potato – Deadlock Free Routing
Every flit can be routed to different directions
(no packet notion at the switch level)
If the optimal direction is blocked, the flit is “deflected” to
another direction
Switch latency of 1 clock cycle whatever the level of congestion
Minimum buffer requirements
Packets reordering
z Adaptive routing
z No buffering
z No back pressure
z Works with Torus/Mesh
z
NOC and SOC Design
Wormhole Routing
z No packets reordering
z Static routing
z Buffering ( ≥ 2 flits/port)
z Back pressure
z XY routing needs mesh
67
Hot-Potato
Src
Dest
Hot-Potato
H
T
F3
F2
Src
F
F
Dest
Hot-Potato
T
F3 F2
Src
F
H
F
Dest
Hot-Potato
T
Src F3
F
H
F
F2
Dest
Hot-Potato
Src
T
F
F3
F2
Dest
HF
Hot-Potato
T
F
Src
F3
F2
Dest
HF
Hot-Potato
Src
TF
Dest
F3
F2
H
F
Hot-Potato
Src
TF
Dest
HF
F2
F3
Hot-Potato
Src
TF
Dest
HF
F2
F3
Hot-Potato
Src
F3
TF
Dest
HF
F2
Network-on-Chip
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78
Core to Network Connection
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79
NOC Switch/Router
Generic
Router/Switch
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80
Another Generic Router
with Virtual Channels
VCID
Demux
VC0
Input 0
(From West)
VC(V-1)
Input 1
(From North)
VC0
Full Crossbar
(5x5)
VC(V-1)
Input N
(From PE)
Flit_in
VC0
VC(V-1)
Mux
Switch Allocater
(SA)
Credit_out
Scheduling
VC Allocater
(VA)
Credit_in, Output VC Resv_State
Routing Logic
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81
A Typical Router Pipeline
FLIT
OUT
FLIT
IN
ROUTING
& BUFFERS
NOC and SOC Design
VC
ALLOCATION
ARBITRATION
SWITCH
TRAVERSAL
82
VC: Virtual-Channels
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83
CAD Problems for NOC
ƒ Application Mapping (map tasks to cores)
ƒ Floorplanning/Placement (within the network)
ƒ Routing (of messages)
ƒ Buffer Sizing (size of FIFO queues in the routers)
ƒ Timing Closure (Link bandwidth capacity allocation)
ƒ Simulation (Network simulation for traffic, delay, power
modeling)
ƒ Testing … Combined with problems of designing NOC itself
(topology synthesis, switching, virtual channels, arbitration,
flow control,……)
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84
Topology Generation and Analysis
• Aim:
ƒ Generate a viable network topology.
ƒ Analyze the generated topology.
• Targeted Network:
ƒ Best-effort, wormhole switched.
ƒ Lookup table based source routing.
ƒ No virtual channel support.
ƒ Round Robin switch output arbitration.
ƒ One NI per component master or slave interface.
ƒ All transactions converted to packets of the same length (flit
count).
ƒ Burst beats converted to separate packets.
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85
System Input and Output
• Input:
ƒ Core Graph
ƒ Network Parameters
• Output:
ƒ Topology Graph
ƒ Route tables
ƒ Recommended
Operating Clock
Frequency
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86
Topology Generation
• Aims:
ƒ Provide physical links.
ƒ Minimize latency on select
paths.
ƒ Use a minimum of
resources.
• Two algorithms are used.
ƒ ALG1: Point-to-Point
Oriented Topologies.
ƒ ALG2: Partitioned
Crossbar Topologies.
• Heuristic approach.
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87
Point-to-Point Oriented
Topologies
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88
Partitioned Crossbar Topologies
• Initial topology: FullyConnected Crossbar
(single switch).
• Ideal latency situation.
• May violate maximum
port requirement.
• Partitioning process.
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89
Topology Analysis
• Aim:
ƒ Estimate achievable performance.
ƒ Account for interference in the system.
• Use of Petri Nets.
• Partitioned analysis.
ƒ Analyze components in isolation.
ƒ Sum contention effects across paths.
• Two Stages:
ƒ Frequency selection.
ƒ Path verification.
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90
Verification Process
• Verify all path
latencies.
ƒ Write packet latency.
ƒ Read packet latency.
• Adjust delays based
on contention.
• Contention Areas:
ƒ Switch output.
ƒ Destination NI.
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91
Contention Estimation
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92
Frequency Selection
• Cyclical relation between contention and
frequency.
• Frequency is fixed before contention is analyzed.
• To find minimum valid frequency:
ƒ Interval halving process.
ƒ Large number of frequency points.
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93
Simulation Environment
• SystemC based.
• Collection of models:
ƒ Generators and Sinks.
ƒ Master and Slave NIs.
ƒ Various Switches.
ƒ AMBA AXI protocol implemented.
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94
Results
• Applications and generated topologies.
• Comparative results.
• Resource Usage.
• Accuracy tests.
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95
MPEG4 - Decoder
A)
B)
Clock Frequency:
3.43 GHz
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96
MWD Application
A)
B)
Clock Frequency:
573.4 MHz
NOC and SOC Design
97
AV Benchmark
NOC and SOC Design
98
AV Topologies
A)
B)
Clock Frequency:
2.31 GHz
NOC and SOC Design
99
Comparative Results I
NOC and SOC Design
100
Comparative Results II
NOC and SOC Design
101
Resource Usage
Topology
NOC and SOC Design
Mesh
Fat
Tree
Custom 1
Custom 2
MPEG4
Decoder
46
44
22
14
MWD
Applicatio
n
59
47
13
17
Av
Benchmar
k
87
67
25
102
Accuracy Test Results I
NOC and SOC Design
103
Accuracy Test Results II
NOC and SOC Design
104