EE 459/500 – HDL Based Digital
Design with Programmable Logic
Lecture 16
Timing and Clock Issues
1
Overview




Sequential system timing requirements
Impact of clock skew on timing
Impact of clock jitter on timing
Clock distribution
2
1
Clocked Synchronous State Machine
Flip-Flop Timing Parameters
2
Latch Timing Parameters
State Machine Timing
3
Satisfying Timing Requirements
 The period must be long enough for the data to propagate
through the registers and logic and to be set up at the
destination register before the next rising edge of the clock.
Satisfied by making T long enough. Cycle time:
 TCLK > tc-q + tlogic + tsu
 The hold time at the destination register must be shorter than
the minimum propagation delay through the logic network.
This requirement is independent of system clock;
manufacturer’s minimum delay specifications are needed.
Guarantee that minimum combinational logic delay is larger
than hold time. Race margin:
 thold < tc-q,cd + tlogic,cd
Clock Uncertainties
4 Power Supply
3 Interconnect
Devices
2
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
4
Clock Nonidealities
 Clock Skew
•
•
Spatial variations in equivalent clock edges
Mostly deterministic
 Clock Jitter
•
•
Temporal variations in consecutive clock edges
Mostly random
 Pulse Width Variation
Clock Skew and Clock Jitter
Clk
tSK
Clk
tJS
 Clock skew and jitter can affect the cycle times
 Clock skew can cause race conditions
5
Overview




Sequential system timing requirements
Impact of clock skew on timing
Impact of clock jitter on timing
Clock distribution
Clock Skew
Bad design
6
Clock Skew
Clock Skew
In
CLK
R1
D
Q
Combinational
Logic
tCLK1
tc - q
tc - q, cd
tsu, thold
R2
D
Q
tCLK2
tlogic
tlogic, cd
 Assume the following timing parameters are available:
 Contamination or minimum delay (tc-q,cd) and maximum
propagation delay (tc-q) of the register
 Setup (tsu) and Hold (thold) times for registers
 Contamination delay (tlogic,cd) and maximum delay (tlogic) of the
combinational logic
 The positions of the rising edges of clocks CLK1 and CLK2 (t CLK1
and tCLK2) relative to a global reference. Ideally tCLK1 = tCLK2.
7
Positive Clock Skew
 Launching edge arrives before the
receiving edge
 Minimum clock cycle:
T+  tc-q + tlogic + tsu
R1
In
D
Combinational
Logic
Q
R2
D
Q
tCLK1
CLK
tc - q
tc - q, cd
tsu, thold
tCLK2
tlogic
tlogic, cd
Negative Clock Skew
 Receiving edge arrives before the
In
launching edge
 Minimum clock cycle:
T+  tc-q + tlogic + tsu
R1
D
Q
Combinational
Logic
tCLK1
tc - q
tc - q, cd
tsu, thold
R2
D
Q
tCLK2
tlogic
tlogic, cd
CLK
8
Positive and Negative Clock Skew
Impact of Clock Skew on Timing:
Cycle Time (Long Path)
9
Impact of Clock Skew on Timing:
Race Margin (Short Path)
Overview




Sequential system timing requirements
Impact of clock skew on timing
Impact of clock jitter on timing
Clock distribution
10
Clock Jitter

CLK

TC LK



t j itter
-tji tte r 
In
Combinational
Logic
REGS
CLK
tc-q , tc-q,
ts u, thold
tjitter
cd
t log ic
t log ic, cd
TCLK - 2tjitter  tc-q + tlogic + tsu
2tjitter+ thold < tc-q,cd + tlogic,cd
Impact of Clock Jitter on Timing:
Cycle Time (Late-Early Problem)
11
Impact of Clock Jitter on Timing
Impact of Clock Skew and Jitter:
Cycle Time (Late-Early Problem)
12
Impact of Clock Skew and Jitter:
Race Margin (Early-Late Problem)
Combined Impact of Clock Skew and Jitter
 Minimum clock cycle (cycle time)
•
TCLK > tc-q + tlogic + tsu -  + 2tjitter
 Positive skew improves performance
 Negative skew reduces performance
 Jitter reduces performance
 Minimum logic delay (race)
•
tlogic,cd + tc-q,cd > thold +  + 2tjitter
 Skew reduces race margin
 Jitter reduces acceptable skew
 Notes:
 Absolute delay through a clock distribution path is not important
 What matters is the relative arrival time at the register points at
the end of each path
13
Overview




Sequential system timing requirements
Impact of clock skew on timing
Impact of clock jitter on timing
Clock distribution
Dealing with Clock Skew and Jitter
 Balance clock paths (tree distribution)
 Don’t use gated clocks
 Use negative skew to eliminate race conditions
(at the cost of performance):
• Add up the components that result in the time
budget - the period must be greater than this value
TCLK > tc-q + tlogic + tsu -  ( <0)
14
Clock Distribution
Clock Distribution
 Distribute clock in a tree fashion
 H-Tree
CLK
15
More Realistic H-Trees
Example: EV6 (Alpha 21264) Clocking
600 MHz – 0.35 micron CMOS
16
Spartan-6 FPGA
Spartan-6 FPGA Global Clock Network
17
Spartan-6 FPGA I/O Clock Network
Spartan-6 FPGA Clock Management Tile (CMT)
18
Digital Clock Manager (DCM)
Eliminating Clock Skew
19
Eliminating Clock Skew
Quadrant Phase Shifting
20
Fine Phase Shifting
Summary
 Clock skew and clock jitter – increasingly
important issues with technology downscaling
 CAD tools (e.g., ISE WebPack) take care of
many issues automatically
21
References and Credits
 Chapter 10 of:
• Jan M. Rabaey, Anantha Chandrakasan, Borivoje
Nikolic, Digital Integrated Circuits, 2nd Edition,
Prentice Hall, 2003.
 Spartan-6 FPGA Clocking Resources:
• http://www.xilinx.com/support/documentation/user
_guides/ug382.pdf
Appendix A: Asynchronous Inputs
22
Asynchronous Inputs: Multiple
Synchronizers
23