Fabrication Technology for Efficient
High Power Silicon Carbide Bipolar
Junction Transistors
Reza Ghandi
Doctoral Thesis
KTH, Royal Institute of Technology
Department of Integrated Devices and Circuits
Stockholm, Sweden 2011
Cover illustration:
Top) Cross section and top view of fabricated 4H-SiC BJT
Bottom) Schematic demonstration of small area multi-finger vertical BJT
Fabrication Technology for Efficient High Power Silicon
Carbide Bipolar Junction Transistors
A dissertation submitted to Kungliga Tekniska Högskolan (KTH), Stockholm,
Sweden, in partial fulfillment of the requirements for the degree of Teknologie
Doktor (Ph.D)
TRITA-ICT/MAP AVH Report 2011:01
ISSN 1653-7610
ISRN KTH/ICT-MAP/AVH-2011:01-SE
ISBN 978-91-7415-861-8
©2011 Reza Ghandi
Abstract
The superior characteristics of Silicon Carbide as a wide band gap semiconductor have motivated
many industrial and non-industrial research groups to consider SiC for the next generations of
high power semiconductor devices. The SiC Bipolar Junction Transistor (BJT) is one candidate
for high power applications due to its low on-state power loss and fast switching capability.
However, to compete with other switching devices such as Field Effect Transistors (FETs) or
IGBTs, it is necessary for a power SiC BJT to provide a high current gain to reduce the power
required from the drive circuit. In this thesis implantation free 4H-SiC BJTs with linearly graded
base layer have been demonstrated with common-emitter current gain of 50 and open-base
breakdown voltage of 2700 V. Also an efficient junction termination extension (JTE) with 80%
of theoretical parallel-plane breakdown voltage was analyzed by fabrication of high voltage PiN
diodes to achieve an optimum dose of remaining JTE charge. Surface passivation of 4H-SiC BJT
is an essential factor for efficient power BJTs. Therefore different passivation techniques were
compared and showed that around 60% higher maximum current gain can be achieved by a new
surface passivation layer with low interface trap density that consists of PECVD oxide followed
by post-deposition oxide anneal in N2O ambient. This surface passivation along with doublezone JTE were used for fabrication of high power BJTs that result in successful demonstration of
2800 V breakdown voltage for small area (0.3 × 0.3 mm) and large area (1.8 × 1.8 mm) BJTs with
a maximum dc current gain of 55 and 52, respectively. The small area BJT showed RON =
4mΩcm2, while for the large are BJT RON = 6.8 mΩcm2. Finally, a Darlington transistor with a
maximum current gain of 2900 at room temperature and 640 at 200 °C is reported. The high
current gain of the Darlington transistor is achieved by optimum design for the ratio of the active
area of the driver BJT to the output BJT.
iii
Table of Contents
Abstract ......................................................................................................................................................... iii
Table of Contents ........................................................................................................................................ iv
List of Appended Papers ............................................................................................................................ vi
Summary of Appended papers .................................................................................................................. ix
Acknowledgments ...................................................................................................................................... xii
List of Symbols and Acronyms ............................................................................................................... xiv
1
Introduction ......................................................................................................................................... 1
2
Power Devices; Current Technology and Challenges .................................................................... 3
2.1 Si vs. SiC ............................................................................................................................................. 3
2.2 Power Rectifiers ................................................................................................................................. 5
2.2.3. JBS and MPS .................................................................................................................................. 7
2.3 Power Field Effect Switches ............................................................................................................ 8
2.3.1. SiC MOSFET................................................................................................................................. 8
2.3.2. SiC JFET....................................................................................................................................... 10
2.4 IGBT ................................................................................................................................................. 12
2.5 GTO .................................................................................................................................................. 13
2.6 Power Bipolar Junction Transistors.............................................................................................. 13
3
Fabrication of SiC devices................................................................................................................ 29
3.1 Bulk and Epitaxial Growth of SiC ................................................................................................ 29
3.2 Surface Preparation ......................................................................................................................... 33
3.3 Etching .............................................................................................................................................. 34
iv
R.Ghandi
Table of Contents
3.4 Lithography ...................................................................................................................................... 35
3.5 Ion Implantation.............................................................................................................................. 36
3.6 Surface Passivation .......................................................................................................................... 37
3.7 Metallization ..................................................................................................................................... 39
4
Bipolar Junction Transistors in 4H-SiC, Fabrication and Characterization ............................. 41
4.1 Design of 4H-SiC BJTs .................................................................................................................. 41
4.2 Bipolar Transistors with regrown extrinsic base and etched JTE ............................................ 45
4.3 Bipolar Transistors with linearly graded base layer and epitaxial JTE ..................................... 45
4.4 Etched Junction Termination Extension for High Power Devices ......................................... 47
4.5 Surface Passivation Influence on the Performance of 4H-SiC BJTs ....................................... 53
4.6 Influence of Crystal Orientation on the Current Gain of 4H-SiC BJTs ................................. 57
4.7 2.8 kV Bipolar Transistors with Improved Junction Termination ........................................... 58
4.7.1. Degradation .................................................................................................................................. 61
4.7.2. Switching Characteristics ............................................................................................................ 61
4.8 Monolithic Darlington Transistors ............................................................................................... 63
4.9 High Temperature Characteristics ................................................................................................ 65
5
Summary and Future Outlook ........................................................................................................ 67
Bibliography ................................................................................................................................................ 71
v
List of Appended Papers
I.
Fabrication of 2700-V 12-mΩcm2 non ion-implanted 4H-SiC BJTs with
common-emitter current gain of 50
R. Ghandi, H.-S. Lee, M. Domeij, B. Buono, C.-M. Zetterling, M. Ostling,
IEEE Electron Device Letters, v 29, n 10, p 1135-1137, 2008.
II.
High Voltage 4H-SiC PiN Diodes with Etched Junction Termination
Extension
R. Ghandi, B. Buono, M. Domeij, G. Malm , C.-M. Zetterling, M. Ostling
IEEE Electron Device Letters, v 30, n 11, p 1170-1172, 2009.
III.
High Current Gain Implantation-free 4H-SiC Monolithic Darlington
Transistor
R. Ghandi, B. Buono, M. Domeij and M. Östling,
IEEE Electron Device Letters, v 32, n 2, p 188-190, 2011.
IV.
Surface Passivation Effects on the Performance of 4H-SiC BJTs
R. Ghandi, B. Buono, M. Domeij, R. Esteve, A. Schöner, J. Han, S. Dimitrijev, S.A.
Reshanov, C.-M. Zetterling, M. Östling,
IEEE Transactions on Electron Devices, v 58, n 1, p 259-265, 2011.
V.
Removal of Crystal Orientation Effects on the Current Gain of 4H-SiC BJTs
using Surface Passivation
R. Ghandi, B. Buono, M. Domeij, S. Shayestehaminzadeh, C-M. Zetterling, and M.
Östling,
Submitted to IEEE Electron Device Letters.
VI.
High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-Term
Stability of the Current Gain
R. Ghandi, B. Buono, M. Domeij, C.-M. Zetterling, M. Ostling
Submitted to IEEE Transaction on Electron Devices.
VII.
High-current-gain SiC BJTs with regrown extrinsic base and etched JTE
H.-S. Lee, M. Domeij, R. Ghandi, C.-M. Zetterling, M. Ostling,
IEEE Transactions on Electron Devices, v 55, n 8, p 1894-1898, 2008.
vi
Related work and other work not included in the thesis
1. B. Buono, R. Ghandi, M. Domeij, G. Malm, C.-M Zetterling, M. Östling, “Modeling and
Characterization of Current Gain versus Temperature in 4H-SiC Power BJTs” IEEE
Transactions on Electron Devices, v 57, n 3, p 704-11, 2010.
2. B. Buono, R. Ghandi, M. Domeij, G. Malm, C.-M Zetterling, M. Östling, ” Influence of
Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs”
IEEE Transactions on Electron Devices, v 57, n 10, p 2664-2670, 2010.
3. K. Buchholt, R. Ghandi, M. Domeij, C-M. Zetterling, J. Lu, P. Eklund, L. Hultman and
A. Lloyd Spetz, “Ohmic contact properties of magnetron sputtered Ti3SiC2 on n- and ptype 4H-silicon carbide”, Accepted for publication in Applied Physics Letters, 2011.
4. R.Ghandi , H.-S.Lee, M.Domeij, B.Buono, C.-M.Zetterling and M.Östling,
“Implantation-Free Low on-resistance 4H-SiC BJTs with Common-Emitter Current Gain
of 50 and High Blocking Capability” Materials Science Forum, v 615-617, p 833-836,
2009.
5. M. Östling, M. Domeij, C. Zaring, A. Konstantinov, R. Ghandi, B. Buono, A. Hallen, C.M Zetterling, “SiC Bipolar Power Transistors - Design and Technology Issues for
Ultimate Performance” Materials Research Society Symposium Proceedings, v 1246, p
175-186, 2010.
6. M. Usman, A. Hallén, R. Ghandi and M. Domeij, “Effect of 3.0 MeV helium
implantation on electrical characteristics of 4H-SiC BJTs” Physica. Scripta. T141 014012,
2010.
7. Lee, H.-S. Domeij, M.; Zetterling, C.-M.; Ghandi, R.; Ostling, M.; Allerstam, F., “1200 V
4H-SiC BJTs with a common emitter current gain of 60 and low on-resistance” Materials
Science Forum, v 600-603, p 1151-1154, 2009.
8. Ghandi, R. Lee, H-S.; Domeij, M.; Zetterling, C.-M.; Ostling, M. ” Backside nickel based
ohmic contacts to n-type silicon carbide” Materials Science Forum, v 600-603, p 635-638,
2009.
9. Ghandi, R.; Lee, H.-S.; Domeij, M.; Zetterling, C.-M.; Ostling, M. “Simultaneous study
of nickel based ohmic contacts to Si-face and C-face of n-type silicon carbide”
Proceedings of International Semiconductor Device Research Symposium, ISDRS, 2007.
10. R. Ghandi, B. Buono, M. Domeij, R. Esteve, A. Schöner, J. Han, S. Dimitrijev, S.A.
Reshanov, C.-M. Zetterling and M. Östling, “ Experimental evaluation of different
passivation layers on the performance of 3kV 4H-SiC BJTs” Materials Science Forum, v
645-648, p 661-664, 2010.
11. B. Buono, R. Ghandi, M. Domeij, G. Malm, ,C.-M Zetterling and M. Östling, ”
Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs”
Materials Science Forum, v 645-648, p 1061-1064, 2010.
vii
R.Ghandi
Table of Contents
12. R.Ghandi, B.Buono, M.Domeij, C.-M.Zetterling, and M.Östling, “High Voltage, Low
On-resistance 4H-SiC BJTs with Improved Junction Termination Extension”, To be
published in Material Science Forum, 2011.
13. L. Lanni, R. Ghandi, M. Domeij, C.-M. Zetterling, B. G. Malm, M. Östling,
“Measurements and simulations of lateral PNP transistor in a SiC NPN BJT technology
for high temperature integrated circuits” To be published in Material Science Forum,
2011.
14. B. Buono, R. Ghandi, M. Domeij, G. Malm, ,C.-M Zetterling and M. Östling, ”Current
Gain Degradation in 4H-SiC Power Bipolar Junction Transistors” To be published in
Material Science Forum, 2011.
15. J Hållstedt, R Ghandi, M Kolahdouz, M Östling and H H Radamson, “Integration of
HCl chemical vapor etching and SiGe:B selective epitaxy for source/drain application in
MOSFETs”, Semicond. Sci. Technol. v 22, S123–S126, 2007.
16. R. Ghandi, M. Kolahdouz, J. Hållstedt, Jun Lu, R. Wise, H. Wejtmans, M. Östling and
H.H. Radamson, “High boron incorporation in selective epitaxial growth of SiGe layers”,
Journal of Materials Science: Materials in Electronics, v 18, n 7, p 747-751(5), 2007.
17. M Kolahdouz, R Ghandi, J Hållstedt, R Wise, Hans Wejtmans, and H H Radamson,
“The influence of Si coverage in a chip on layer profile of selectively grown Si1-xGex layers
using RPCVD technique”, Thin Solid Films, v 517, n 1, p 257-258, 2008.
18. R Ghandi, M Kolahdouz, J Hållstedt, R Wise, Hans Wejtmans, and H H Radamson,
“Effect of strain, substrate surface and growth rate on B-doping in selectively grown
SiGe layers”, Thin Solid Films, v 517, n 1, p 334-336, 2008.
19. H. H. Radamson, M. Kolahdouz, R. Ghandi, and J. Hallstedt, “Selective epitaxial growth
of B-doped SiGe and HCl etch of Si for the formation of SiGe:B recessed sources and
drains (pMOS transistors)”, Thin Solid Films, v 517, n 1, p 84-86, 2008.
20. J. Hållstedt, M. Kolahdouz, R. Ghandi, R. Wise, J. W. Weijtmans and H. H. Radamson,
“Pattern dependency in selective epitaxy of B-doped SiGe layers for advanced metal
oxide semiconductor field effect transistors”, Journal of Applied Physics, v 103, 054907,
2008.
21. H. H. Radamson, M. Kolahdouz, R. Ghandi, and M. Ostling, “High strain amount in
recessed junctions induced by selectively deposited B-doped SiGe layers”, Materials
Science and Engineering: B, v 154-155, p 106-109, 2008.
viii
Summary of Appended papers
Paper I.
This paper reports high blocking (2.7 kV) implantation-free Bipolar Junction Transistors with
low on-state resistance (12 mΩcm2) and high common-emitter gain of 50 that are fabricated by
design and implementation of graded base doping to provide low resistive base contacts. In this
design, the base layer is fully depleted close to the breakdown voltage providing an efficient JTE
without ion implantation. Eliminating the implantation step in this approach can be beneficial for
avoiding high temperature annealing needed for activation of dopants and also for avoiding
generation of life-time reducing defects that can affect high current gain and blocking capability.
The author performed all the device processing and the electrical characterization and
wrote the manuscript.
Paper II.
This paper presents implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal
breakdown voltage of 4.3 kV (about 80% of the theoretical value). The key step in achieving a
high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to
reach an optimum dopant dose of ~1.2×1013 cm-2 in the junction termination extension (JTE).
Electroluminescence revealed a localized avalanche breakdown in good agreement with device
simulation. A comparison of diodes with single-zone and two-zone etched JTE show a higher
breakdown voltage and a smaller sensitivity to variation in processing conditions for diodes with
a two-zone JTE. The author performed all the device processing and the electrical
characterization and wrote the manuscript.
Paper III.
An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 (JC = 970
A/cm2 and VCE = 6V) at room temperature is reported in this paper. The device demonstrates a
record maximum current gain of 640 at 200 °C offering an attractive solution for high
temperature applications and exhibits an open-base breakdown voltage of 1kV that is less than
optimum bulk breakdown due to isolation trench between the driver and the output BJT. On the
same wafer a monolithic Darlington pair with a non-isolated base layer was also fabricated. At
room temperature, this device shows a maximum current gain of 1000 and open-base breakdown
voltage of 2.8 kV which is 75% of the parallel-plane breakdown voltage. The author performed
all the device processing and the electrical characterization and wrote the manuscript.
ix
R.Ghandi
Summary of Appended Papers
Paper IV.
In this paper, the electrical performance in terms of maximum current gain and blocking
capability has been compared theoretically and experimentally for 4H-SiC BJTs passivated with
different surface passivation layers. Variation in BJT performance has been correlated to densities
of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different
methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer.
The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O
ambient at 1100 °C during 3 hours. Variations in breakdown voltage for different surface
passivations were also found, and this is attributed to differences in fixed oxide charge that can
affect the optimum dose of the high voltage junction termination extension (JTE). The
dependence of breakdown voltage on the dose was also evaluated through non-implanted BJTs
with etched-JTE. The author performed all the device processing and most of the electrical
characterization and wrote the manuscript.
Paper V.
In this study, the dependence of the current gain and the base resistance on the crystal
orientation for single finger 4H-SiC BJTs are analyzed. Statistical evaluation techniques were also
applied to study the effect of surface passivation and mobility on the performance of the devices
and it is showed that the BJTs with emitter edge aligned to the [1210] direction shows lower
current gain before surface passivation and higher base resistance after contact formation
compared to other investigated crystal directions. However the devices show similar current gain
independent of the crystal orientation after surface passivation. The author performed all the
device processing and most of the electrical characterization and wrote the manuscript.
Paper VI.
In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been
fabricated utilizing a controlled two-step etched junction termination extension (JTE). The small
area devices show a maximum dc current gain of 55 and VCESAT = 1.05 V at Ic = 0.107 A that
corresponds to a low ON-resistance of 4 mΩ·cm2. The large area device have a maximum dc
current gain of 52 and VCESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8
mΩ·cm2. Also these devices demonstrate a negative temperature coefficient of the current gain
(β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2
mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain
degradation after 150 Hrs stress of the base-emitter diode with current level of 0.2A (JE=500
A/cm2). Also, large area BJT shows a VCE fall time of 18 ns during turn-on and a VCE rise time of
10 ns during turn-off for 400 V switching characteristics. The author performed all the device
processing and all of the electrical characterization and wrote the manuscript.
x
R.Ghandi
Summary of Appended Papers
Paper VII.
This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a
regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4HSiC BJTs measuring 1.8 × 1.8 mm (with an active area of 3.24 mm2) showed a common emitter
current gain β of 42, specific on-resistance RSP_ON of 9 mΩcm2, and open-base breakdown voltage
BVCEO of 1.75 kV at room temperature. The key to successful fabrication of high-current-gain
SiC BJTs with a regrown extrinsic base is efficient removal of the p+ regrown layer from the
surface of the emitter–base junction. The BJT with p+ regrown layer has the advantage of lower
base contact resistivity and current gain that is less sensitive to the distance between the emitter
edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs
without ion implantation means less lifetime-reducing defects, and in addition, the surface
morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flatsurface junction termination that combine etched regrown layers show about 250 V higher
breakdown voltage than BJTs with only etched flat-surface JTE. The author contributed with
device processing and electrical characterization.
xi
Acknowledgments
My four years PhD study that is summarized in this thesis is indebted to guidance, assistance and
encouragement of several individuals at Royal Institute of Technology (KTH). First and
foremost, I would like to express my sincere gratitude to my principal supervisor, Dr. Martin
Domeij for his continuous support, motivation and immense knowledge in semiconductor
technology. He was indeed the true master mind behind this thesis and all of our successful
results are based on his accurate design and analysis.
Prof. Mikael Östling, head of the device technology department, dean of the ICT School at KTH
and my second supervisor is deeply appreciated for giving me the opportunity to study in the
field of SiC device technology and also for fruitful guidance and motivation in the research and in
the daily life.
I am indeed grateful to Dr. Henry Radamson as a supervisor in my master project and also as a
supporting friend in my academic and personal life. His true passion along with broad knowledge
had indeed an enormous influence on my research and study.
My deep gratitude goes to Prof. Carl-Mikael Zetterling for his scientific guidance and insightful
discussions. I also enjoyed his advanced student-centered teaching methods. Bread-baking design
of experiment (DOE) was one of my sweetest memories at KTH.
I am also indebted to Dr. Hyung-Seok Lee for teaching me the SiC process technology and also
for his support and encouragement. Jan-Olov Svedberg and Krister Gumaelius at TranSiC are
also thanked for their assistance and solutions in problematic processing issues.
Dr. Gunnar Malm, Prof. Anders Hallen and Dr. Per-Erik Hellström are deeply appreciated for
their kind scientific support and assistance.
During these years, I spent many hours with my very nice friends at the ICT school.
Mohammadreza Kolahdouz (Mreza) is indeed my oldest friend for more than 20 years and I have
many sweet memories with him. His energetic character along with scientific collaboration was
enormous help for me passing through the tough moments during study and research. I am also
grateful to Sohrab Redjai Sani for continuous support and motivation during these years and also
for wonderful morning chats and coffee times.
xii
R.Ghandi
Acknowledgment
The other people at SiC group have kindly helped me and this thesis would not have been
finished without their continuous support. Special thanks go to Benedetto Buono for his
theoretical knowledge in semiconductor physics and also for his unique simulation techniques
that was essential for my research activity. I am also grateful to him for the afternoon Italian
coffee that helped me to work in dark winter days of Stockholm. My officemate, Luigia Lanni is
appreciated for her kind support and patience during my stressful times writing the thesis. I am
also thankful to Romain Esteve for his accurate recipes that were crucial for my devices and his
assistance during measurements. Muhammad Usman is also appreciated for very nice scientific
and non-scientific discussions.
Also Timo Söderqvist , Christian Ridder, Dr. YongBin Wang, Dr. Julius Hållstedt, Dr Zhen
Zhang, Dr. Jun Luo, Dr. Jiantong Li, Valur Gudmundsson, Sam Vaziri, Arash Salemi, Mahdi
Moeen, Oscar Gustafsson, Eugenio Dentoni Litta at EKT and my other friends, Ana Lopez,
Majid Mohseni, Mahdi Darab, Nader Nikkam, Reza Sanatinia and Ali Khatibi are thanked and
appreciated for the encouragement, assistance and motivation during my study.
This thesis in also indebted to vary kind people at the Electrum Lab. Foremost; I would like to
thank Reza Nikpars, for his generous help with the lab machines and also for his kind and
cheerful attitude that made me enjoy the annoying times in the clean room. Magnus Lindberg and
all other staff at the lab are deeply appreciated for their help and nonstop assistance.
A special thank to Gunilla Gabrielsson and Zandra Lundberg for their warm kindness and help
in bureaucratic administrative issues.
Last but not least I would like to send my gratitude to all members of my family. My parents are
deeply appreciated for always supporting me and believing in me. Also my deep gratitude and
appreciation go to my wife, Zeinab, for her patient companionship throughout these years and
for her true love in the life. This thesis is dedicated to you.
Thank you all!
Reza Ghandi
January-2011
xiii
List of Symbols and Acronyms
µn
Electron Mobility
µp
Hole Mobility
A
Ampere
AFM
Atomic force Microscopy
Al
Aluminum
Al2O3
Aluminum Oxide
AlN
Aluminum Nitride
B
Boron
BJT
Bipolar Junction Transistor
BPD
Basal Plane Dislocation
BVCBO
Open emitter breakdown voltage
BVCEO
Open base breakdown voltage
C
Carbon
CO
Carbon monoxide
CO2
Carbon dioxide
C-V
Capacitance-Voltage
CVD
Chemical Vapor Deposition
DB
Base minority carrier diffusion coefficient
DB
Base minority carrier diffusion coefficient
DE
Emitter minority carrier diffusion coefficient
DI water
De-Ionized water
DIMOSFET Double-Implanted MOSFET
Dit
Interface Trap Density
E
Electric field
EC
Critical electric field
Eg
Energy Bandgap
FET
Field Effect Transistor
GTO
Gate turn-off Thyristor
G-V
Conductance-Voltage
HF
Hydrofluoric acid
xiv
R.Ghandi
List of Symbols and Acronyms
HTCVD
High Temperature Chemical Vapor Deposition
IB
Base current
IC
Collector current
IC0
Reverse saturation current at base-collector junction
ICP
Inductively coupled Plasma
IE
Emitter current
IGBT
Insulated Gate Bipolar Transistor
InE
Electron current in Emitter
IpE
Hole current in Emitter
IR
Recombination current
I-V
Current-Voltage measurement
JBS
Junction Barrier Schottky
JFET
Junction FET
JTE
Junction Termination Extension
Ln
Electron diffusion length in emitter
MJTE
Multistep Junction Termination Extension
MOS
Metal Oxide Semiconductor
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
MPS
Merged PiN/Schottky
n
Electron concentration
N2O
Nitrous oxide
NB
Base doping concentration
NC
Effective conduction band density of states
NE
Emitter doping concentration
ni
Intrinsic carrier concentration
Ni
Nickel
NIT
Near Interface Traps
NO
Nitric oxide
p
Hole concentration
PECVD
Plasma Enhanced Chemical Vapor Deposition
POCl3
Phosphoryl Chloride
q
Electron charge
Qeff
Effective Charge
RIE
Reactive Ion Etching
RON
ON-Resistance
RTA
Rapid Thermal Annealing
xv
R.Ghandi
List of Symbols and Acronyms
SBD
Schottky Barrier Diode
SCR
Space Charge Region
Si
Silicon
SiC
Silicon Carbide
SiO2
Silicon dioxide
SSF
Shockley Stacking Fault
Ti
Titanium
TLM
Transfer Length Method
TMA
Trimethylaluminum
UMOSFET U-shaped groove MOSFET
V
Voltage
Vbr
Breakdown Voltage
VCE
Collector-emitter voltage
VF
Forward Voltage Drop
vsat
Saturated Velocity
WB
Base region width
WE
Emitter region width
α
Common-base current gain
αT
Base transport factor
β
Common-emitter current gain
γC
Collector efficiency
γE
Emitter injection efficiency
εr
Relative Permittivity
λ
Thermal Conductivity
ρc
Specific contact resistance
Chapter 1
1 Introduction
Based on the United Nations report, development and climate change are among the major
global issues in this century that affect millions of people throughout the world [1]. Development
includes higher standards of living, full employment, and conditions of economic progress while
human influence of the climate change is attributed to increase of atmospheric CO2
concentration due to emission of fossil fuel combustion. Power electronic devices have a great
impact on economy and environment due to the widespread use in many industrial and nonindustrial applications. More efficient power devices can provide cost effective and environment
friendly tools for higher energy efficiency that is a required solution factor for the global issues.
Silicon based power devices with capability of handling significant current and voltages are
commercially available from 1950s and have been extensively developed since then. But, the
performance of these devices is limited for high power applications and also for high temperature
environment. However Silicon Carbide as a wide band gap semiconductor has the potential to
replace Si in high power devices due to its superior electrical and physical properties. Similar to
Si, there are a wide range of unipolar and bipolar devices that have the potential to be adopted
for different power ratings. The SiC bipolar junction transistor (BJT) is a candidate for the next
generation of high voltage switches especially for high power and harsh environment
1
R.Ghandi
List of Symbols and Acronyms
applications.
This thesis is focused on design, fabrication and characterization of high voltage 4H-SiC BJTs
and demonstrates significant progresses in SiC BJT performance in terms of current gain and
breakdown voltage. Implementing graded base doping profile and new surface passivation along
with efficient etched junction termination result in successful fabrication of implantation-free
BJTs with current gain of 55 and breakdown voltage of 2800. The second chapter of this thesis
briefly discusses basic operation, current technology and challenges for fabrication technology
and performance of Si and SiC power devices with the main focus on bipolar transistors. Chapter
3 covers the basic process steps for fabrication of SiC devices and Chapter 4 discusses design
parameters of 4H-SiC BJTs and also demonstrates new techniques and results from fabrication
of high voltage transistors. Conclusion and summary are finally covered in Chapter 5.
Chapter 2
2 Power Devices; Current Technology and
Challenges
In this section, the current technology of different power devices as well as progress and
challenges are briefly discussed. In each section, the main challenges for Si power devices are
highlighted but the main focus will be on 4H-SiC power devices.
2.1 Si vs. SiC
Silicon based high power electronic devices have been commercially available for more than 50
years and are regarded as the key components of nearly all power electronic systems. However,
the performance of Si based power devices is limited at high power density and high temperature
environments. The superior characteristics of SiC as a wide band gap semiconductor and also
important progress in fabrication of high quality crystalline SiC has motivated many groups to
consider SiC as the main candidate to replace Si in next generations of high power devices [2].
Therefore it is important to discuss material and electrical properties of SiC and compare them
with Si.
Due to different stacking order of silicon and carbon atoms, silicon carbide possesses more
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
than one crystal structure. This characteristic which is known as polytypism has brought different
polytypes for SiC crystalline structure. 3C-, 4H- and 6H-SiC are three stable single crystalline
polytypes for device purposes (Fig. ‎2.1).
Electrical properties of Si, 3C-, 6H-, 4H-SiC are compared in Table ‎2-1. The higher bandgap of
SiC compared to Si is regarded as the main advantage for high power devices that results in larger
critical electric field and higher temperature capability. These superior properties enable the use
of thinner drift layers with lower resistance and less leakage current at elevated temperatures for a
desired breakdown voltage. 3C-SiC shows the highest electron mobility compared to other
polytypes of SiC and the lowest critical electric field. This polytype, which is also known as cubic
crystalline SiC, has been successfully grown on Si substrate but it still suffers from low material
quality. 2-4 inches 4H and 6H-SiC substrates are commercially available today and many 4H and
6H high power devices have been reported. However, 4H-SiC is the preferred polytype
compared to 6H due to a higher electron and hole mobilities which are essential for achieving
low on-resistances and also due to higher critical electric field for high voltage applications.
Fig. ‎2.1 Three stable polytypes of SiC [3]
Chapter 2
Table ‎2-1 Electrical properties of Si and different polytypes of SiC
Material Properties
Si
3C-SiC
6H-SiC
4H-SiC
Bandgap (eV at 300K)
Eg
1.12
2.4
3.0
3.2
Critical Electric Field (V/cm)
Ec
2.5×105
2×106
2.5×106
2.2×106
Thermal Conductivity (W/cmK at 300K)
λ
1.5
3-4
3-4
3-4
Saturated Electron Drift Velocity (cm/s)
vsat
1×107
2.5×107
2×107
2×107
Electron Mobility (cm2/V·s)
μn
1350
1000
500
950
Hole Mobility (cm2/V·s)
μp
480
40
80
120
Relative Permittivity
εr
11.9
9.7
10
10
The specific on-resistance (RON) of the drift layer can be calculated as [4]:
‎2-1
in which VB is the breakdown voltage. Therefore higher critical electric field in SiC compare to Si
not only provides higher breakdown voltage but also results in lower resistance which is required
for high power applications.
2.2 Power Rectifiers
High voltage Si power rectifiers are widely used in power electronic applications. An efficient
power rectifier should demonstrate a required high voltage capability in the blocking mode with
low leakage current as well as a low ON-resistance in the forward conduction mode. In power
circuits, rectifiers are continuously switched between the ON and OFF states. These devices are
also required to demonstrate low power loss switching characteristics especially for high
frequency applications. The main power rectifiers are PiN diodes and Schottky diodes. The
advent of SiC with one order of magnitude higher critical electric field has made it possible to
implement thinner drift layer with higher doping and lower ON-resistance compared to Si. Also
these devices have demonstrated higher temperature capability compared to Si based devices. In
this section, structure, characteristics and challenges of these devices are shortly discussed and
recent breakthroughs of SiC rectifiers are highlighted.
2.2.1. PiN Rectifiers
Si PiN rectifier consists of a highly doped p and n layers with an intermediate lowly doped layer
(normally n) that is equivalent to an intrinsic region (i). This rectifier behaves as a normal high
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
voltage p-n diode except that at high current density, the lowly doped layer is flooded with high
concentration of holes and electrons that exceed the doping concentration. This phenomenon
which is also known as conductivity modulation results in a very low resistance of the layer and
allows the diode to carry relatively higher current density during forward conduction. However
the main disadvantage of the PiN diode is its poor switching performance that results in high
power loss. During turn-on and before conductivity modulation, due to the high resistive iregion, high magnitude forward voltage overshoot occurs which is not desirable in power circuit
design. During turn-off the presence of a large concentration of stored carriers must be removed
from the layer, and the device shows a poor reverse recovery characteristic that causes significant
switching power losses. Therefore, optimum performance of the Si PiN diode is limited by the
maximum switching frequency and a trade-off between forward voltage drop and switching
speed is needed. 4H-SiC PiN diodes can provide higher switching speed and lower voltage drop
compared to Si PiN diodes because of a thinner drift layer. These diodes have also shown hightemperature operation that is desired in many high power applications. The main concern for
fabrication of high voltage 4H-SiC PiN diodes is high quality growth of a lowly doped thick
epitaxial layer with high minority carrier life-time for optimum conductivity modulation.
However, the performance of the SiC PiN diode can be degraded under forward voltage stress
resulting in an increasing forward voltage drop. This phenomenon which is known as bipolar
degradation is due to Shockley stacking faults (SSFs) that originate from basal plane dislocations
and this is discussed in more detail in sections ‎2.6.2.2 and ‎3.1.3.2. Table ‎2-2 summarizes recent
reported high voltage SiC PiN diodes in terms of breakdown voltage, ON-resistance and forward
voltage drop at 100 Acm-2.
Table ‎2-2 Recent reported high voltage 4H-SiC PiN diodes
Number
Vbr (kV)
RON (mΩcm2)
VF @100 Acm-2
Ref.
1
3.3
1.7
3.3
[5]
2
4.5
1.7
3.3
[6]
3
6.5
34
3.4
[7]
4
10
38
3.9
[8]
5
12-19
65
4.4-7.5
[9]
2.2.2. Schottky Barrier Diode (SBD)
Si Schottky barrier diodes are composed of a rectifying metal contact deposited on a
semiconductor substrate and demonstrate a unipolar current transport due to the potential
Chapter 2
barrier at the interface between the metal and the semiconductor. The main advantage of these
devices is the possibility of achieving minimum ON-resistance during forward conduction by
proper choice of metal with desired work function for the lowest potential barrier. However,
decreasing the potential barrier increases the leakage current in the blocking mode and that
requires a trade-off between forward voltage drop and reverse leakage current especially at higher
temperatures. Also because of the absence of minority carriers in the current transport, SBDs
show no reverse recovery and the switching is instead governed by the diode space charge
capacitance. Si SBDs are therefore widely used for high frequency low power electronics
applications. High voltage 4H-SiC SBDs have been introduced to the market since 2001.
Compared to Si diodes, these rectifiers show faster switching due to the thinner drift layer at the
expense of higher forward voltage drop across the junction. Therefore, SiC SBDs are interesting
devices particularly when the switching power losses are dominant. At the moment, 300V/30A1700V/25A SiC SBDs are commercially available and there is potential for fabrication of higher
power rectifiers as the material quality improves further.
2.2.3. JBS and MPS
To utilize the properties of the PiN diode and Schottky diodes, JBS and MPS have been
introduced as monolithic combinations of both devices. Junction barrier controlled Schottky
(JBS) is a Schottky diode with an integrated P+-N junction grid into the drift region. During
reverse bias, the integrated P layer, extend the depletion layer, shield the Schottky barrier and
reduce the leakage current compared to conventional Schottky rectifiers. Merged PiN/Schottky
(MPS) rectifiers employ the same approach for combining two conventional rectifiers and act like
JBS in the blocking mode. However, the integrated P+ layers are forward biased at high current
levels and inject high concentration of minority carriers into the lowly doped n-layer that results
in conductivity modulation, thereby protecting the diode from overheating under surge current
conditions. Due to the presence of Schottky contact, the total charge required for conductivity
modulation is less compared to the PiN diode that results in better recovery during turn-off. SiC
JBS diodes are regarded as an interesting candidate to replace SBDs in the relatively high voltage
range. However material quality and process complexity are still the main concern for fabrication
of these types of devices. Fig. ‎2.2 shows an example of high voltage 4H-SiC JBS diode and Table
‎2-3 demonstrate
recent reported JBS rectifiers.
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Fig. ‎2.2 Schematic cross-section of a 10 kV 4H-SiC JBS diode [10].
Table ‎2-3 Recent reported high voltage 4H-SiC JBS diodes
Number
Vbr (kV)
RON (mΩcm2)
VF
Ref.
1
1.6
7.5
1.4 V @100 Acm-2
[11]
2
5
25.2
3.5 V @108 Acm-2
[12]
3
10
100
3.37 V @20 Acm-2
[10]
2.3 Power Field Effect Switches
Silicon power field effect transistors became widely popular and have replaced power bipolar
transistors in most applications. These devices have the potential for high frequency switching as
well as simpler driver circuitry through voltage controlled drivers. However the performance of
Si power switches at high voltage ranges are limited in the maximum current capability due to
lightly doped high resistance drift layers. For medium range blocking voltages (up to 800 V), Si
power MOSFETs such as CoolMOS by Infineon [13] demonstrate superior characteristics and
are available in the market. The advent of SiC paved the way for thinner drift layer for the desired
breakdown voltage compared to Si and demonstrates the potential of faster switching speed and
lower switching loss using SiC FETs. In this section, the main features of SiC MOSFETs and
JFETs are shortly discussed and recent reported values are demonstrated.
2.3.1. SiC MOSFET
The first SiC power metal-oxide-semiconductor field-effect-transistor (power MOSFET) was
Chapter 2
developed by Palmour et al. [14] and called SiC UMOS. This structure which was developed by
other groups in the following years, includes a U-shaped trench inside the epitaxially grown pdoped layer (grown on the lowly doped drift layer) followed by thermal oxidation for isolation,
and deposition of polysilicon as the gate (Fig. ‎2.3a). However, this structure suffered from poor
quality of the SiC/SiO2 interface especially at the rough sidewalls of the trench that resulted in
low inversion layer mobility. Also the high electric field accumulation at the corners of the trench
was intensified at the gate oxide and caused long term oxide reliability issues for the devices.
Fig. ‎2.3 Cross section view of a)UMOS and b)DIMOSFET SiC power transistors [15].
The other structure is called double implant MOSFET (DIMOSFET) which includes separate
implantation of p-well and n+ sources has the advantage of higher inversion channel mobility and
high voltage capability (Fig. ‎2.3b). However, this structure requires high temperature anneal after
ion implantation that can degrade the performance of the device. Also a high interface state
density at the SiC/SiO2 interface still limits the effective electron mobility in the channel and
improved oxidation techniques are required (see section ‎3.6). Table ‎2-4 summarizes the recent
reported values for 4H-SiC MOSFETs.
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Table ‎2-4 Recent reported 4H-SiC MOSFETs
Number
Vbr (kV)
RON (mΩcm2)
Ref.
1
0,95
8,4
[16]
2
1,2
9
[17]
3
1,4
15,7
[18]
4
1,6
40
[19]
5
2,4
42
[20]
6
10
123
[21]
2.3.2. SiC JFET
The SiC junction field effect transistor (JFET) is another type of field effect switch that is free
from the gate oxide and therefore does not suffer from oxide reliability and mobility reduction by
interface states. Therefore JFETs are regarded as reliable high power switches especially at higher
temperatures. In this configuration, the n-channel is controlled by the space charge region
between the gate and the source through a voltage on the gate (Fig. ‎2.4). The requirement of the
negative voltage for turning off the device makes the JFET as a normally-on switch which is not
preferred in power electronics applications. This problem is solved by a cascade configuration of
Si MOSFET and SiC JFET (Fig. ‎2.5) in which turning off the triggering MOSFET provides a
negative bias to the gate of the JFET and turns it off. The other approach is to make a normallyoff JFET with a channel pinched off at zero gate bias (Fig. ‎2.6). The complexity of ion
implantation control especially at the sidewall and limitation of operational threshold voltage
margin are regarded the main practical issues for these devices. Some recent reported SiC JFETs
are shown in Table ‎2-5.
Fig. ‎2.4 Schematic illustration of vertical SiC JFET [22]
Chapter 2
Fig. ‎2.5 Cascade configuration of Si MOSFET and SIC JFET
Fig. ‎2.6 Schematic demonstration on normally off JFET with (left) [23] and without (right) [24] source-mesa sidewall implantation
Table ‎2-5 Recent reported 4H-SiC JFETs
Number
Vbr (kV)
RON (mΩcm2)
Ref.
1
0,6
2,6
[25]
2
0,8
6,5
[26]
3
1,65
1,8
[27]
4
1,68
5,5
[28]
5
1,7
2,77
[29]
6
1,9
2,8
[23]
7
2,055
5,7
[30]
8
3,5
390
[31]
9
11
130
[32]
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
2.4 IGBT
Insulated Gate Bipolar Transistor is a monolithic combination of power bipolar transistor and
MOSFET that provides attractive characteristics of high input impedance of the voltage
controlled MOSFET as well as low forward voltage drop at high current densities due to
conductivity modulation. Si IGBTs, as a commercially successful power device, replaced bipolar
transistors in medium power applications that require high switching frequency and excellent onstate characteristics However, performance of Si IGBTs are limited by high switching losses due
to presence of minority carriers. High critical electric field as well as high temperature capability
of SiC has urged different groups to consider fabrication of high voltage SiC IGBTs as a
potential candidate for higher power applications. n-channel IGBT which is composed of nchannel MOS and a PNP transistor is a preferred structure compared to p-channel IGBT due to
the improved n-channel MOS process conditions with low interface states (Fig. ‎2.7). However,
an n-channel IGBT requires a p-type substrate. P-type substrates are not available in large
dimensions and production volumes and they also introduce high resistance in series to the
device. Recently 13 kV, 22 mΩcm2 n-IGBT have been reported [33]. This device shows
conductivity modulation during forward conduction that corresponds to higher current capability
compared to a 10kV SiC DMOSFET. High quality thick epitaxial growth with a long carrier life
time is still a major challenge for development of SiC IGBTs.
Fig. ‎2.7 Schematic view of SiC IGBTs for p-channel (left) and n-channel (right) [34]
Chapter 2
2.5 GTO
Gate Turn-Off thyristors are specific thyristors with possibility of reverse gate drive current for
turning off the device which is required in high power DC applications. Si GTOs suffer from
large switching loss especially during turn-off due to the large current tails. The SiC GTO with
high voltage capability is considered as an interesting device due to better thermal conductivity
and larger breakdown field. However, the requirement of a large gate drive current for turn-off
and also material quality are regarded as the main challenges of SiC GTO for high power
applications [34].
2.6 Power Bipolar Junction Transistors
Si bipolar power transistors are available since 40 years. The potential of operating at relatively
high current densities with low power loss and high voltage capability was regarded as the
distinguished features of power BJTs. However, due to low current gain of power BJTs at typical
operating current levels, they have been replaced with insulated gate bipolar transistors (IGBT)
and power MOSFETs in many power electronics applications. Interesting properties of SiC as a
wide band gap semiconductor and robustness to harsh environments has made it possible to
consider the SiC BJTs as one candidate for high power applications due to its low power on-state
loss and fast switching capability. In this section basic characteristics of power bipolar transistors
along with recent advances and challenges of SiC BJTs are discussed.
2.6.1. Structure and Operation of BJT
The bipolar junction transistor is a three terminal electronic device that consists of two joined
back-to-back p-n junctions. In this configuration npn BJT is preferred to pnp BJTs due to higher
electron mobility compared to hole mobility. Unlike unipolar devices where majority carriers
constitute the current conduction, both minority and majority carriers comprise the current
conduction for bipolar devices. As it can be seen in Fig. ‎2.8, in the forward-active mode of the
npn BJT when the emitter-base diode is forward-biased, electrons are injected from the highly
doped n-terminal (emitter) to the intermediate p-terminal (base). Some of these electrons
recombine in the base but most of them are swept out through the reverse-biased base-collector
diode and reach the collector region of the device, thereby producing a collector current.
Therefore it is possible to control carrier transport and hence the electric current by the voltage
bias of the emitter-base diode. Generally the total currents between emitter, base and collector
can be related as:
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
2-2
In the common-emitter mode in which the base current (IB) is an input variable while the
collector current (IC) is the output variable, β (common-emitter current gain) is defined as the
ratio of IC/IB. For the common-base mode, α is defined as the ratio between IC/IE and called
common-base current gain. It can be shown that
2-3
For an efficient switch, it is desired to achieve high common-emitter current gain (β) that requires
common-base current gain (α) close to 1. Emitter, base and collector currents are composed of
majority and minority carriers in each layer and they can be described as follows (Fig. ‎2.8) :
2-4
2-5
2-6
in which InE and IpE are emitter currents due to electron and hole injections into the base and
emitter respectively. IR is recombination current in the space-charge region of emitter-base diode,
IRS is surface recombination current due to the defects at the interface with passivation layer and
IRB is bulk recombination current in the base. The reverse saturation current of the base-collector
junction is defined as IC0 that is also negligible at collector biases below avalanche breakdown.
IE
Emitter
IpE
InE
IR
IB
IRS
IRB
Base
InC
Collector
IC0
IC
Fig. ‎2.8 Schematic demonstration of current components in an npn bipolar transistor in forward-active mode.
Chapter 2
The common-base current gain can be written as:
2-7
where γE, αT, γC are called emitter injection efficiency, base transport factor and collector
efficiency, respectively. Emitter injection efficiency illustrates the ability of the emitter to inject
electrons into the base region. Since the injection of the holes into the emitter does not
contribute to the collector current, emitter injection efficiency is less than one. The emitter
efficiency is dependent on the design of emitter and base regions. It can be shown that if the
emitter thickness is significantly shorter than hole diffusion length in the emitter, then
2-8
in which N is doping concentration, D is minority carrier diffusion constant and W is thickness
of corresponding base and emitter regions. Therefore designing the BJT with highly doped
emitter layer and lowly doped thin base layer is advantageous for achieving an emitter efficiency
closer to 1 and consequently higher current gain (β). However, a lowly-doped base layer can
result in a low punch-through breakdown voltage (described later), which is not desired. The base
transport factor (αT) is a measure of the ability of injected electrons from the emitter to diffuse to
the base without recombining, and αT therefore depends on the recombination rate in the base
region. This factor can be calculated using the following formula:
2-9
where Ln is electron diffusion length in the base and WB is the base thickness. For a lowly doped
thin base layer where the electron diffusion length is much larger than the base thickness, the
base transport factor can be estimated as:
2-10
Since the base-collector is reversed biased most of the electrons that reach the SCR region are
swept out and the collector efficiency can be assumed to be 1.
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Ic A
C
B
IB
VCE
Fig. ‎2.9 The output characteristics of BJT in common emitter mode. A, B and C are saturation, quasi saturation and active
regions.
A typical output characteristic (IC-VCE) of the BJT in common emitter mode is illustrated in Fig.
‎2.9.
This curve can be divided in three sections. For low VCE voltages, both base-emitter and
base-collector diodes are forward biased which results in injection of majority carriers (electrons)
and minority carriers (holes) into the drift (collector) region. In this mode, which is called
saturation mode (A), if the concentration of injected carriers exceeds the background doping of
the lowly doped drift layer, then the collector region is conductivity modulated and a low ONresistance (lower than for a unipolar device) can be reached. However, if obtaining conductivity
modulation is difficult (like in SiC) then the ON-resistance in the BJT will be dominated by the
drift resistance. For higher collector voltages, the transistor enters the quasi saturation region (B)
in which the injected carrier concentration remains higher than the collector doping
concentration only in a fraction of the drift layer and that results in higher ON-resistance,
compared to the saturation region. Finally for even higher collector voltages, transistor enters the
active mode (C) in which base-emitter diode is forward biased and base-collector diode is reverse
biased. In this mode, due to the reverse-biased base-collector junction, the injection of minority
carriers into the drift layer is negligible and the current gain is higher compared to other bias
points in A and B. However, the IV characteristics in the active mode is not constant and it
shows a slight increase of the collector current with increasing collector-emitter voltage that
results in intersection of I-V curves extensions at a negative voltage (Early voltage). This behavior
is due to a decreasing effective base width with increasing reverse bias of the base-collector
junction (Fig. ‎2.10).
Chapter 2
Electric Field
V1 < V2
tB1 > tB2
V1
V2
tB2
tB1
n+
Distance
p (Base)
n+
n (Collector)
Fig. ‎2.10 Schematic demonstration of decreasing the effective base width with increasing collector-emitter voltage.
At high collector current densities and high collector-emitter voltages, the majority carrier
concentration in the drift layer (electrons) exceeds the doping concentration of the layer. In this
case, which is known as base widening effect (or Kirk effect), the polarity of the net charge in the
drift layer is changed from positive to negative and it results in a change in the gradient of the
electric field distribution and in the position of the maximum electric field from p-n junction to
n-n+ junction (Fig. ‎2.11). Therefore, high current densities can increase the effective base
thickness and result in decreased current gain. For the extreme cases, this base widening effect
can be destructive for high base currents that generate positive feedback in the collector current
and cause second breakdown [35].
Electric Field
J4
J1
J1 < J2 < J3 < J4
tB1 < tB4
J3
J2
tB1
tB4
n+
p (Base)
Distance
n (Collector)
n+
Fig. ‎2.11 Base widening effect at high collector current densities for npn BJTs with content collector voltages.
The BJT is also limited to a maximum collector-emitter voltage, due to avalanche breakdown at
the base-collector junction or punch-through breakdown. For the open-emitter case, increasing
the collector voltage followed by multiplication of the generated carriers results in sharp increase
of the collector current and demonstrates the avalanche breakdown (BVCBO) as a conventional p-
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
n junction. However, in the case of open-base, avalanche breakdown (BVCEO) starts at lower
voltages due to transistor action in which the collector current is the avalanche current amplified
by the current gain. It can be shown that:
2-11
where n is an empirical constant with a value between 3 and 5 in Si. Therefore, increasing the
current gain can limit the maximum collector emitter voltage. However for the SiC BJTs,
prediction of the BVCEO is difficult and the reported values ranged from 40% [36] to 60% [37] of
the ideal breakdown voltage of the collector layer. However in this thesis, the open-base and
open-emitter breakdown voltages were measured in the same range that can be correlated to the
small current gain at low leakage currents. Another limiting phenomenon is punch-through
breakdown in which the depletion regions between the base-collector and the base-emitter diodes
reach each other. In this situation, the base-emitter junction becomes forward biased and
breakdown occurs. However, punch-through breakdown can be avoided if the total base has
sufficient doping dose (concentration × thickness).
Normally, vertical power transistors apply mesa edges for isolation of the layers. At the mesa
edges, and close to the surface of the device, the critical electric field can be increased due to the
curvature of the electric field profile. Therefore junction termination has to be adopted to locally
reduce the electric field. There are different junction termination techniques for power BJTs that
can be adopted singularly or in combination with each other. The most common technique for
BJTs is an implanted Junction Termination Extension (JTE) in which the collector layer is locally
implanted by p-dopants with lower doping than the base layer close to the base mesa. The other
technique is field ring (guard ring) termination that includes implanting p-type field rings
surrounding the entire base mesa. This technique can be combined with implanted JTE and
called guard ring assisted JTE [38]. Another junction termination is mesa-etched JTE that
requires etching of single or multiple zones in the implanted [39] or in the epitaxial p-base layer
(Paper I) close to the main isolation to the collector. All of these terminations should be designed
in a way to achieve an accurate dose of charge that becomes completely depleted to the surface
close to the desired breakdown voltage, thereby reducing the maximum electric field in the edge
region.
Chapter 2
2.6.2. SiC BJT
The first SiC bipolar transistor was reported at IEDM in 1977 [40]. In this work, emitter and base
layers were epitaxially grown followed by dry etching for layers isolation and metallization. This
BJT showed common emitter current gain of 4 and breakdown voltage of 50 V for an emitter
area of 200 × 200 µm2 (Fig. ‎2.12). However it took more than 10 years until Palmour et al.
reported the first power BJT in 6H-SiC in 1993 [41]. This device exhibited the current gain of
10.4 and 200 V breakdown voltage with high temperature capability.
Fig. ‎2.12 The first SiC BJT with the current gain of 4 and breakdown voltage of 50V [40].
In 2000, Ryu et al. demonstrated 1800 V, 3.8 A 4H-SiC BJT with epitaxial base and emitter layers
[42] (Fig. ‎2.13). However in the same year, Tang et al. showed the first BJT with implanted
emitter and claimed this process offered the flexibility of controlling the base width by varying
the emitter implantation [43]. This device showed a high current gain of 36 and low breakdown
voltage of 40V due to the punch through effect. In [44], punch through was suppressed by
increasing the base width thereby achieving 500 V breakdown voltage, but the common emitter
current gain decreased to 9 due to implantation-induced defects at the emitter-base p-n junction,
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
that reduced the emitter injection efficiency (Fig. ‎2.13). Consequently, 4H-SiC BJTs with epitaxial
and implanted emitter were compared and it was confirmed that epitaxially formed p-n junctions
provide better charge injection compared to the implanted p-n junctions and are therefore
preferred in BJT process technology [45].
Fig. ‎2.13 Cross sectional view of 1800 V epitaxial emitter (top) [42] and implanted emitter (bottom) [44] 4H-SiC BJTs.
It was also shown that interface traps between surface passivation layer and SiC can affect
electron transport and thereby decrease the current gain. Improvement in 4H-SiC surface
passivation lead to demonstration of power 4H-SiC BJTs with current gain of >50 using thermal
oxidation instead of deposited oxide [46] and 35 using thermal oxide followed by nitric oxide
annealing [47]. Further improvement of the current gain for power SiC BJTs was reported by
Krishnaswami et.al with optimized continuous epitaxial growth of the base and emitter layers at
lower temperature. This technique demonstrated an increase in the minority carrier lifetime in the
Chapter 2
emitter and base layers by reducing point defects and impurities while maintaining stoichiometry
of the highly doped SiC layers [48]. Also due to the relatively low hole mobility and lack of
shallow acceptor levels, the base resistance of the 4H-SiC BJTs is relatively high. Therefore
achieving optimum ohmic contact for lowest ON-resistance device is important. 1677 V, 5.7
mΩcm2 [49] and 757 V, 2.9 mΩcm2 4H-SiC BJTs [50] were reported with Ni–AlTi–Ni as the
improved base contacts followed by Al/AlTi as a thick overlay metal on the base and emitter.
fingers to improve the voltage and current distribution. However these devices suffered from low
current gains of 7.1 and 18.8 respectively. Lee et al. demonstrated 1200 V, 5.2 mΩcm2 4H-SiC
BJTs with high current gain of 60 using a triple layer of Ni/Ti/Al for the base contacts and
surface passivation by thermal oxidation in N2O ambient that results in reduced surface
recombination [51]. It was also shown that design of the power BJTs can affect the performance
of the devices. Domeij et al. demonstrated a clear emitter size effect indicating the significant
influence of surface recombination on the maximum current gain and also revealed the minimum
requirement distance of 2-3 µm between the emitter edge and base contact implant to avoid the
effect of implantation–induced defects for the optimum performance [52]. 4H-SiC BJTs using a
base contact without implantation [53] and regrown extrinsic base layer (Paper VII) showed the
possibility of fabricating implantation-free BJTs. Zhang et al. reported a 1300 V 4H-SiC BJT with
a common–emitter current gain up to 31 using double base epilayers (Fig. ‎2.14) in a completely
implantation-free process [54].
Fig. ‎2.14 1300 V 4H-SiC BJT with a common–emitter current gain up to 31 using double base epilayers.
In Paper I, we reported a 2700 V, 12 mΩcm2 implantation-free SiC bipolar junction transistors
with common-emitter current gain of 50 using a graded-base doping (see section ‎4.3). This design
21
22
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
was optimized in terms of junction termination extension and contact metallization and resulted
in 2800 V, 4 mΩcm2 implantation-free BJT in Paper VI (see section ‎4.7). Fabrication of these
devices in an implantation-free process can be beneficial for avoiding life-time killing defects that
are generated during implantation. This also provides the possibility of placing the base contact
closer to the emitter mesa to reduce the cell pitch for reducing the specific on-resistance. Table
‎2-6
summarizes the recent reported values for 4H-SiC BJTs and Fig. ‎2.15 compares recent high
power transistors in terms of breakdown voltage vs. on-resistance.
Table ‎2-6 Recent reported 4H-SiC BJTs
RON
Current
(mΩcm2)
Gain
0.95
3.2
134
[55]
2
1
2.9
33
[56]
3
1.2
6.3
70
[57]
4
1.2
5.2
60
[51]
5
1.5
3.4
40
[58]
6
1.6
5.1
70
[59]
7
1.8
4.4
40
[60]
8
2.2
4.5
35
[58]
9
2.7
12
50
Paper I
10
2.8
4.5
55
11
6
28
[61]
12
9.2
49
[62]
Number
Vbr (kV)
1
Ref.
Paper
VI
Chapter 2
MOSFET-6
JFET-8
On-Resitance (mΩ.cm2)
100
Si Unipolar
Limit
MOSFET-4
BJT-12
MOSFET-5
BJT-11
MOSFET-3
BJT-9
MOSFET-1MOSFET-2
10
BJT-4
JFET-4 JFET-7
BJT-10
BJT-3 BJT-6
BJT-8
BJT-7
BJT-1
BJT-5
BJT-2 JFET-5 JFET-6
JFET-2
JFET-1
4H-SiC Unipolar
Limit
JFET-3
1
100
1000
10000
Breakdown Voltage (V)
Fig. ‎2.15 Comparison of recent high power 4H-SiC transistors.
2.6.2.1. Advantages of 4H-SiC BJTs
Operation of Si power bipolar transistors is limited by two major destructive effects that are
known as thermal runaway and second breakdown. The thermal runaway, in which the total
current increases with a positive feedback mechanism, occurs at elevated temperatures. This
phenomenon, can occur due to the positive temperature coefficient of the forward voltage drop
in a Si BJTs, and is caused by an increasing carrier lifetime in the device at elevated temperatures.
This leads to a higher carrier concentration, higher current density and even more local increase
in the temperature which is escalated by more increase in the total current. However, a SiC BJT
shows negative temperature coefficient of the current gain in which, the current gain of the
device is significantly decreased at higher temperatures due to the activation of deep level
acceptors in the base that limit the emitter injection efficiency. Also the specific ON-resistance of
the device is increased at elevated temperatures due to the decreasing electron mobility which
causes an increase in the resistance of the collector layer (an example of high temperature
performance is shown in Fig. ‎2.16). These characteristics are desired for parallel connection of
BJTs for high temperature applications.
23
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
0,4
T=25
IB=1mA/step
0,35
T=200
0,3
0,25
Ic (A)
24
0,2
0,15
0,1
0,05
0
0
1
2
3
4
5
6
7
8
9
VCE (V)
Fig. ‎2.16 IC-VCE characteristics of 4H-SiC BJT at room and elevated temperature (Paper VI).
The other destructive mechanism which was described earlier is second breakdown. The high
critical field strength of SiC made it possible to use higher doping in the collector layer. For this
reason second breakdown occurs at a very high current density which is well outside the normal
operation area of the device [63].
2.6.2.2. Challenges for SiC BJTs
Along with many advantages of the SiC BJT, still some main challenges for these devices should
be addressed. Since the BJT is a current controlled device, for more efficient power switching,
even higher current gain is desired. As discussed earlier, state of the art technology shows a
current gain of less than 100 for the power BJTs with more than 1 kV blocking capability. To
compete with other switching devices, it is necessary to provide higher current gain which can be
reached with better epitaxial growth conditions and optimum surface passivation.
For high frequency application, minimal conductivity modulation is desired for an efficient
switching; however, for high voltage switches, the power BJT should demonstrate conductivity
modulation in the saturation region for the lowest ON-resistance. This condition, which is
regarded as the main advantage of bipolar devices compared to unipolar devices, has not been
shown in 4H-SiC BJTs. Low carrier lifetime which are due to the various defects in the SiC
structure and also higher doping of the drift layer compared to Si power BJTs are factors behind
the absence of conductivity modulation. Therefore, optimum growth condition in terms of less
defects and higher carrier life time not only improves the current gain but it can be advantageous
also for achieving conductivity modulation. The other challenge which is the main obstacle for
Chapter 2
commercialization of 4H-SiC BJTs is degradation of the forward voltage drop (VCESAT) and
degradation of the current gain, under forward bias stress at high current density. Like the PiN
diodes, degradation of VCESAT is mainly attributed to carrier trapping and recombination in the
base and/or collector due to the SSFs (see section ‎3.1.3.2 and Fig. ‎2.17).
Emitter
InE
Base
Collector
IC
Fig. ‎2.17 Schematic demonstration of stacking fault effects on the current transport in the base and collector regions.
However a current gain degradation mechanism with no significant decrease on the on-resistance
has been observed for BJTs on BPD-free substrate, and for small-area BJTs on standard
substrates. The reason for this gain degradation is not clear and three possible mechanisms have
been proposed:
1. an increase of the interface trap density along the SiC/SiO2 interface
2. recombination enhanced defect generation in the base emitter region
3. small size stacking faults in the base-emitter region [64].
Fig. ‎2.18 shows examples of bipolar degradation and current gain degradation in a 4H-SiC BJT.
25
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
10
Before
9
Ib0.3AIc4A_30min
Ib0,3AIc4A_10Hrs
8
7
Ic (A)
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
VCE (V)
0,35
Before Stress
0,3
Ib200mA_40Hrs
0,25
Ic (A)
26
Ib200mA_150Hrs
0,2
0,15
0,1
0,05
0
0
1
2
3
4
5
6
7
8
9
VCE (V)
Fig. ‎2.18 Example of bipolar degradation (Top) and current gain degradation (Bottom) after base-emitter stress of 4H-SiC BJTs
(Paper VI).
2.6.2.3. Darlington Configuration
As discussed earlier, it is important to improve the common-emitter current gain (β) to reduce
the power required by the drive circuit. Increasing the current gain by two cascaded BJTs in a
Darlington configuration is a potential solution for high power applications at the expense of a
higher forward voltage drop. The optimally-designed Darlington can provide higher current gain
(β
Darlington
=β
(Driver BJT)
×β
(Output BJT)
) compared to a single BJT along with high voltage blocking
characteristics. Hybrid SiC Darlington transistors with 500 V and current gain of 430 [65] and
10kV with current gain of 440 [66] have been previously reported. However, monolithic
Darlington design is more preferred due to simpler design, better control in fabrication process
Chapter 2
and reproducibility. Recently Zhang et al. demonstrated a 10 kV monolithic Darlington BJT with
current gain of 1200 [67]. Fig. ‎2.19 shows structure and photographic images of 10 kV hybrid and
monolithic Darlington BJTs .
Fig. ‎2.19 Structure and photographic image of co-packed hybrid (Top) [66] and monolithic (Bottom) 4H-SiC Darlington BJTs
[67].
The dependence of the maximum current gain in a 4H-SiC BJT on the collector current,
emphasizes the importance of the ratio between the area of the driver and the output BJTs. For
the maximum current gain, the driver BJT should be designed in a way that it is not only biased
for the maximum gain but also provides the required current for the highest gain to the output
BJT. In Paper III an implantation free monolithic Darlington with a maximum current gain of
2900 at room temperature is reported and it is shown that the high current gain is related to an
optimum design for the ratio of the active area of the driver BJT to the output BJT
(approximately 1:10).
27
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Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Chapter 3
3 Fabrication of SiC devices
This chapter describes process technology for fabrication of SiC devices with more emphasis on
bipolar transistors and PiN diodes. It begins with a short introduction to bulk and epitaxial
growth of SiC that follows the outline of [68] and discusses surface preparation techniques,
etching, lithography, ion implantation and metallization as the main processing steps for
fabrication of devices. Most of the process steps are similar to Si technology, however due to the
different properties of SiC some modifications are required and these are highlighted in each
section.
3.1 Bulk and Epitaxial Growth of SiC
Single crystalline structure is considered as one of the main requirements for fabrication of
regular semiconductor devices. Therefore, in this section bulk and epitaxial growth of SiC crystal
structures as well as challenges and related issues are discussed.
3.1.1. Bulk Growth
After Jönas Jacob Berzelius, the Swedish chemist who discovered Si and most likely synthesized
29
30
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
the chemical bond between silicon and carbon in 1824, Edward Goodrich Acheson, an American
chemist, found a crystalline compound of silicon and carbon in 1893 and called it
“carborundum” with the formula of SiC. He mixed silica sand and petroleum coke in the furnace
with a graphite core as the heating element. At high temperatures (>2100 °C) hexagonal SiC was
made close to the graphite and was grinded to powder for abrasive applications. However his
method was slow and difficult to control in achieving pure crystalline material for semiconductor
applications. Around 50 years later, in 1955, J.A. Lely reported a sublimation technique for SiC
crystal growth with better control in the purity and properties of the material [69]. He deployed a
cylindrical graphite crucible and heated it to the process temperature of 2500 °C to evaporate SiC species and formed SiC crystals platelets.
Fig. ‎3.1 Schematic demonstration of the Lely process for hexagonal SiC crystals [70]
However, his method suffered from difficulty in control of the SiC poly-type that was solved
with a modified Lely growth with seeded sublimation growth invented by Tairov and Tsvetkov in
1978 [71]. In this technique, they used seed crystal and controlled thermal gradient, to increase
growth rate and improve the material quality (Fig. ‎3.2). They produced SiC boules, sliced and
polished it to create the first SiC wafer.
Chapter 3
Fig. ‎3.2 The seeded sublimation growth or modified Lely growth invented by Tairov and Tsvetkov [68].
The seeded sublimation growth technique has been optimized and today, most SiC substrates
are grown by this method. For a better control of the desired poly-type and also for high-quality
epitaxial growth, it is preferred to use off-axis substrates (8° or 4° for 4H and 3.5° for 6H polytypes). However, for large diameter wafers, more material from the boule is lost using this
technique which emphasizes the requirement for studying the possibility of on-axis growth.
During recent years, high temperature chemical vapor deposition (HTCVD) technique is
introduced for high quality bulk and epitaxial growth of SiC crystals [72]. In this method high
concentrations of the precursor gases silane and ethylene are decomposed, sublimed at high
temperature and condensed on the seed at the end of the reactor. Compared to seeded
sublimation growth, this method has higher growth rate (1mm/hr), higher crystalline quality due
to purity of the gases and better growth yield. However for commercial applications, even higher
growth rate and lower cost is required.
3.1.2. Epitaxial Growth
For commercial applications of SiC, chemical vapor deposition (CVD) is considered as the main
technique for epitaxial growth of high quality crystalline layers with controlled doping and
thickness. Among different CVD reactors, hot-wall reactor [73] and Chimney reactor [74] are
preferred to grow lowly doped high quality thick epitaxial layers for high voltage applications.
Also multi-wafer reactors have shown good uniformity and high material quality for large scale
production. In these methods, silane and C- precursors along with nitrogen (for n-type layers)
and trimethylaluminum (TMA) (for p-type layers) are introduced to the chamber to grow
different epitaxial layers with various doping profiles.
31
32
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
3.1.3. Defects
The presence of structural defects in the crystal structure is an important issue for
commercialization of SiC devices. Quality of the SiC bulk growth and defects introduced during
epitaxial growth are among the major limiting issues in the performance of SiC power devices.
Many different types of SiC crystal defects have been reported to be reduced in density by better
control in the growth techniques. However there are still two major types of defects that require
extra attention for fabrication of SiC devices. In this section micropipes and stacking faults are
highlighted and summarized.
3.1.3.1. Micropipes
Micropipes are regarded as an important defect present in SiC. They are giant screw dislocations
that are originated from clustering several screw dislocations or contamination during the growth.
These types of defects represent an energetically favorable growth site that open up a hollow core
in the center and form spiral growth on the surface. The presence of these defects in the devices,
strongly influence the performance of the device and in most cases cause failure of the voltage
blocking capability. Therefore it is desired to reduce the distribution density of the micropipes in
the SiC bulk growth. During recent years, there has been important progress in reducing these
types of defects. Recently 100 mm SiC substrates with zero micropipe density has been released
and 150 mm substrate with 8 mp/cm2 has been demonstrated by CREE [75] and this is a
breakthrough for wide scale commercialization of SiC technology.
3.1.3.2. Stacking Faults
Another important type of defects in SiC are stacking faults. These defects that have been
characterized in [76], are nucleated from basal plane dislocations (BPDs) in the SiC substrate and
propagate with a triangular shape in the active region of the device (Fig. ‎3.3). Stacking faults can
act as recombination centers that reduce the carrier life time and therefore degrade the device
performance, for instance current gain of a SiC BJT. Additionally, the stacking faults can block
the carrier transport in regions of a device thereby increasing the forward voltage drop. For that
reason, they are regarded as one of the limiting factors for long term stability of bipolar devices in
SiC such as PiN diodes and BJTs.
Chapter 3
Fig. ‎3.3 Photoluminescence imaging at 450 ± 10nm, showing evolution of stacking faults during an
1h electrical stress sequence of a 4h-SiC BJT [77].
3.2 Surface Preparation
Fabrication yield of SiC devices is strongly dependent on proper surface preparation techniques.
This process includes the removal of organic and non-organic contaminations prior to the
oxidation, and etching for avoiding a native oxide layer prior to the metallization. Surface
cleaning techniques are divided in dry and wet cleaning methods. In the dry cleaning technique,
normally hydrogen or ozone-plasma treatments are preferred for physical removal of the
contaminations or other process related residuals (e.g. hardened photo-resist). In wet cleaning
techniques, which involve chemical removal of the contaminations and native oxide layer,
standard solutions are used that are summarized in Table ‎3-1. In fabrication of 4H-SiC BJTs in
this thesis, Seven-up and IMEC solution were applied for surface cleaning before thermal
oxidation or oxide deposition and BHF for removing native oxide layer before metallization.
Also acetone bath followed by propanol and DI water were applied between each process step to
remove any process residues.
33
34
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Table ‎3-1 Description of standard chemical solution for surface preparation of SiC substrates
Description
Chemicals
Temp./ Time
Removal
RCA SC1
H2O:NH4OH:H2O2 (5:1: 1)
80-90°C /10 min
Organic
RCA SC2
H2O:HCl:H2O2 (5:1:1)
80-90°C /10 min
Ionic/ Metal
Seven-up
H2SO4:H2O2 (2.5:1)
90-110°C/ 5min
Organic / Metal
IMEC
H2O:HF:CH3CH(OH)CH3(100:1:1)
25°C /100 s
Oxide
Aqua regia
HCl:HNO3 (3:1)
50°C /5min
Metal
Dilute HF
HF:H2O(1:10)
25°C
Oxide
BHF
HF:NH4F (1:7)
25°C
Oxide
3.3 Etching
SiC is often used for abrasive application due to the strong bond between Si and C atoms. This
property makes it difficult to etch SiC substrate and complicates fabrication of epitaxially based
vertical power devices that require deep trenches. Therefore, unlike other semiconductors, high
quality anisotropic etching that preserves the morphology of the surface and also has a high etch
rate requires more aggressive techniques. Wet etching of SiC is not a common technique in
fabrication process due to its isotropic property and also requirement of elevated temperatures
that makes it difficult to control [78]. For higher etch rate and better uniformity, fluorine-based
dry etching of SiC in high density plasma reactors such as Reactive Ion Etching (RIE) and
Inductively Coupled Plasma (ICP) are desired. However, compared to conventional RIE, ICP has
the advantage of using separate RF-source for biasing the platen and for plasma generation that
avoids high self-bias on the wafer. Therefore, the etched surface is less damaged through high
energy ions and also better selectivity to the mask material is achieved.
Fig. ‎3.4 Scanning electron microscopy (SEM) image of the trenching effect using metal mask
Chapter 3
The main problem with ICP etching of SiC is trenching effects on the sidewall of the etched
mesa (Fig. ‎3.4) that depends on the plasma condition and the type of mask material. Better
control of the plasma and also avoiding metal masks that affect high energetic ions in the plasma
can reduce the amount of trenching.
In this thesis, STS ICP [79] (Fig. ‎3.5) was used in SF6/Ar environment with 30 W of platen
power was used to make BJT emitter fingers, base mesas and also etched junction terminations
with masking layers of deposited silicon dioxide. The SiC etch rate was 135 nm/min with etch
selectivity (SiC/SiO2) of 1.4.
Fig. ‎3.5 Schematic view of STS ICP [79].
3.4 Lithography
Similar to other electronic devices, fabrication of SiC-based components needs different
lithography steps. Since high voltage devices have fairly large features compared to integrated
circuits, standard high precision stepper lithography with resolution of 1µm can be applied for
these types of devices. In this work, 6-9 lithography steps were used for fabrication of high
voltage BJTs and PiN diodes using either a Karl Suss MA6/BA6 1:1 mask aligner [80], a DSW
8500/2035 g-line 5:1 stepper or an ALS 2035 G-line stepper (Fig. ‎3.6). However, in most cases,
since the stepper lithography machine was calibrated to 4-inch Si process technology, 2 inch SiC
substrates were placed on a Si carrier wafers that required extra alignment steps for higher
accuracy. Based on the process step, different photo-resists such as positive 1813, 1818 and 712
and negative resist AZ5214 [81] were applied.
35
36
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Fig. ‎3.6 Karl Suss MA6/BA6 1:1 mask aligner (left) and DSW 8500/2035 g-line 5:1 stepper (right) [82]
3.5 Ion Implantation
In standard fabrication process of electronic devices, ion implantation or thermal diffusion with
appropriate masking films are used for selective-area doping of the material. However for SiC
structures, due to the high thermal stability, extremely high temperatures are required for
diffusion of the dopant elements. Therefore, ion implantation is the only viable option for
introducing dopants into the SiC substrates. This technique involves irradiation of high energetic
ions into the SiC material followed by high temperature anneal for activation of the implanted
ions and reducing implantation-induced lattice damage. Unlike Si, which has a mature fabrication
technology, ion implantation and specifically optimized post implantation anneal in SiC is a major
scientific challenge to avoid structural defects while preserving surface morphology. Nitrogen (N)
and phosphorous (P) are the typical donors for n–type doping of the SiC substrate while
aluminum (Al) and boron (B) are used as p-type acceptors. High temperature anneal (~1400°C ~1800°C) is needed for activation of implanted atoms and annealing of implantation induced
crystal damage. However during high temperature anneal and due to evaporation of Si, the
surface morphology can deteriorate. It has been shown that graphite [83] (Fig. ‎3.7) or AlN [84]
capping layers can effectively protect the morphology of the surface during post-implantation
anneal.
Chapter 3
Fig. ‎3.7 Surface morphology of SiC before annealing (left), after annealing without surface protection (center) and after annealing
using a graphite cap (right) [84]
For fabrication of SiC PiN diodes and bipolar transistors, ion implantation can be used for
formation of P-N junctions, highly doped layers for ohmic contacts [85] [86] and junction
terminations [87] - [88]. However complete dopant activation is difficult to achieve even after
high temperature annealing and additionally ion implantation induced lifetime-killing defects are
not fully annealed out and can affect the performance of the device. Therefore in this thesis, SiC
bipolar transistors and PiN diodes in SiC are fabricated in an implantation-free process (Papers I,
II, VI) in which a linearly graded base layer and etched Junction termination extension (JTE) are
used for achieving a highly doped layer for ohmic contacts and terminations respectively (see ‎4.3
and ‎4.4).
3.6 Surface Passivation
Inherited from Si technology, silicon dioxide (SiO2) is an attractive dielectric for passivation of
SiC surfaces, for the gate dielectric layer of MOS structures and also as the masking layer for
etching and ion implantation. This layer can be thermally grown in diffusion furnaces in dry or
wet ambient or deposited on the surface. Due to the strong bond between Si and C, thermal
oxidation of SiC needs higher temperature and shows lower oxidation growth rate. The oxidation
process involves in-diffusion of oxygen atom through the already formed oxide layer and outdiffusion of C in form of CO or CO2 from the oxide [89]. However, unlike Si, this process can
leave C atoms at the interface between the oxide and SiC which complicates the situation and
affects the properties of the interface between the SiC and the SiO2 layers [90]. Carbon clusters
along with dangling bonds and near interface traps (NITs) [91] compose interface state defects
between SiO2 and SiC and affect the electron transport through field termination, carrier trapping
and Coulomb scattering. Compared to Si thermal oxidation (with trap density of 1010 cm-2) the
interface trap density in SiC is in the order of 1012-1013 cm-2 and that leads to poor field effect
mobility values. These interface defects have been characterized with an energy level of 2.9 eV
above the valence band in 4H- and 6H-SiC [92] and they can significantly affect the electron
transport in 4H-SiC (with Eg = 3.3 eV) while 6H-SiC (with Eg = 3 eV) is less affected due to
37
38
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
smaller bandgap.
During recent years significant progress has been made on improving the quality of the SiC/SiO2
interface, but interface trap density and also fixed oxide charge are still main challenges for
fabrication of SiC devices. It has been shown that incorporation of nitrogen (N) at the interface
between oxide and SiC can improve interface trap density through passivation of interface traps.
N incorporation can be through oxidation or post-oxidation anneal in NO [93]- [94] or N2O
ambient [95]- [96] and deposited oxide combined with N2O anneal [97]. Also it has been shown
that high temperature anneal in hydrogen [98] or phosphoryl chloride (POCl3) [99] can further
reduce the SiC/SiO2 interface state density in 4H-SiC. The recent reported values for interface
trap densities are summarized in Table ‎3-2. Epitaxial growth of AlN [100] and atomic layer
deposited Al2O3 layer (CVD) over nitrided oxide [101] have recently been pointed out as possible
alternative for SiC devices that require further improvement on the growth and characterization.
As discussed earlier, improving the SiC/SiO2 interface is one of the main objectives for
fabrication of 4H-SiC MOSFETs with improved channel mobility. For 4H-SiC BJTs, it is
expected that oxidation technologies that give good results for MOSFETs can also lead to
improved interface properties and thereby BJTs with higher current gain. Therefore in 4H-SiC
BJTs, thermal oxidation in N2O or post oxide anneal in N2O are used to form state-of-the-art
surface passivation. An improved passivation layer in terms of lower interface state density can
decrease surface recombination current at the exposed base surface and along base-emitter
junction sidewall thus resulting in higher current gain. However, the passivation layer can affect
the blocking performance of the BJT through introducing additional charge in the junction
termination region. In Paper IV different surface passivation for 4H-SiC BJTs have been
compared and optimized etched JTEs have been discussed.
Table ‎3-2 Summery of recent reported interface trap densities for 4H-SiC under different process conditions.
Process condition
Interface trap density (cm-2/eV)
Ref
Dry Oxidation
1.3 × 1013
Paper IV
Dry + NO anneal
3.5 × 1012
[102]
TEOS+N2O anneal
2.8 × 1012
Paper IV
Growth in N2O
2.3 × 1012
Paper IV
Dry + H2 anneal
1.0 × 1012
[98]
PECVD+N2O anneal
4.25 × 1011
Paper IV
Growth in NO
3 × 1011
[103]
Dry + POCl3 anneal
9 × 1010
[99]
Chapter 3
3.7 Metallization
Based on the application of SiC devices, different metallization approaches are adopted for metal
contacts in SiC process technology. These processes are divided into three types; Metallization
for Schottky and ohmic contacts and overlayer metallization. Generally, the metallization process
involves cleaning of the surface and deposition of the metal followed by patterning, or patterning
followed by etching and deposition (in a lift-off process). High temperature annealing is
necessary for the ohmic contact formation. For the optimum contact, it is desired that the metal
is placed in intimate contact with the semiconductor. Therefore the surface of the semiconductor
should be free from organic and metal contaminations, photoresist residues and native oxide
layer. Also the roughness of the surface can affect the performance of the contact. Sacrificial
oxidation, cleaning the surface using standard surface preparation techniques (see section ‎3.2) and
HF dip followed by in-situ pre-deposition etch can level the surface, remove the contaminations
or other residual and remove the native oxide layer respectively. There are different deposition
techniques for metallization process. Sputtering is the most common way of metallization that
shows a good adhesion of the metal to the substrate and provides the possibility of compound
metallization. However this technique can be problematic for patterning the contact in the lift-off
process. Thermal or electron beam evaporation is another technique that provides higher
deposition rate in an ultra-clean vacuum system. But in some cases, evaporation suffers from
poor adhesion of the metal to the substrate. The other technique is CVD that provides the
possibility of epitaxial growth of different metallic compounds for better contacts to SiC.
However the deposition is lower compared to other techniques and maintaining the quality of the
layer is difficult. Lift-off and metal etch are regarded as the main techniques for patterning the
metal contacts. In SiC, Schottky contacts are annealed at moderate temperatures (~500°C) for
breaking-up of oxide leftover at the interface and passivation of interface states to improve the
ideality factor and reduce the leakage current. However, ohmic contacts are normally annealed at
higher temperatures (~800°C - ~1000°C) in oxygen free ambient to form a reaction between the
metal and SiC forming silicide for the case of Ni contacts to SiC. But high temperature annealing
of the ohmic contacts can cause roughening of the layer that may be problematic for reliability of
the contact and adhesion of overlay metal. Also high temperature annealing can affect the
passivation layer of the device. Therefore it is desired to decrease the annealing temperature as
low as possible and also divide the metallization into two steps: first, a thin metal film is
deposited on the SiC substrate and annealed to form a silicide layer. Then an additional thick
metal overlayer (normally Al) is deposited after annealing to reduce the metallization series
39
40
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
resistance and to provide an appropriate condition for wire-bonding. The quality of the ohmic
contact is strongly important in the device performance and total power loss, and it is normally
evaluated by specific contact resistance (ρC) and measured in Ωcm2. This value is strongly
dependent on the doping level of the semiconductor, metal type and annealing condition.
Different metals have reported for n- and p-type SiC devices. For n-type 4H-SiC, Ni is the most
commonly used metal that has showed the specific contact resistance in the range of ~10 -5 - 10-6
Ωcm2 [51]- [104]. For p–type 4H-SiC, Ti [105], Ti/Al [47] and Ni/Ti/Al [53] have been reported
with specific contact resistances in the range of ~10-4-10-5 Ωcm2.
Chapter 4
4 Bipolar Junction Transistors in 4H-SiC,
Fabrication and Characterization
In this chapter, design, fabrication and characterization of different types of 4H-SiC bipolar
junction transistors are discussed. Also optimizations of the design and process in terms of
junction termination extension (in correlation with fabrication of 4H-SiC PiN diodes) and surface
passivation effects on the performance of devices are described. Monolithic Darlington
configurations based on the BJT technology are also demonstrated as a potential solution for the
fairly low current gain of 4H-SiC BJTs. Finally, high temperature measurements, tests of longterm stability and switching characteristics are shown and discussed.
4.1 Design of 4H-SiC BJTs
As discussed earlier, epitaxial 4H-SiC, npn BJTs are the preferred structure of bipolar transistors
for high power applications. The epitaxial growth of different layers of the device is normally
carried out in high temperature CVD reactors on 2-4 inch 4H-SiC substrates. The quality of the
41
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
substrate and the epitaxial growth has important effects on the performance of transistors. The
devices discussed in this chapter are fabricated on 2-inch 4H-SiC substrates fabricated by CREE
[75] with epitaxy grown by Acreo [106] or CREE. In this part, some design issues for optimum
performance of the SiC BJT in terms of doping and thickness of the epitaxial layers are discussed.
4.1.1. Collector layer
The collector layer plays an important role in the performance of the bipolar transistors. During
blocking mode, the breakdown voltage is supported by the collector layer while the resistance of
the collector layer determines the on-resistance of the BJT in the forward mode. Unlike Si, and
due to the absence of conductivity modulation in the lightly doped collector layer, the onresistance of the BJT is close to the unipolar drift resistance. Therefore it is desired to design the
collector layer in a way that not only supports the desired breakdown voltage but also provides as
low resistance as possible for the optimum performance. Fig. ‎4.1 shows the electric field
distribution for a punch-through collector design. It has been shown that for this design, the
optimum thickness of the collector layer (toptimum) for a desired breakdown voltage with minimum
resistance can be calculated as:
4-1
where BVCBO is open-emitter breakdown voltage and EC is the critical electric field of 4H-SiC
[68]. Therefore, the drift layer for high breakdown voltage (>3 kV) SiC BJTs in this thesis were
designed with more than 20 µm in thickness.
EC
Electric Field
42
1/3EC
t
Distance
n+
p (Base)
n (Collector)
n+
Fig. ‎4.1 Electric field distribution during blocking mode for punch-through collector design
Chapter 4
The minimum value of the specific on-resistance of the collector for this case is given by:
4-2
where µn is the bulk electron mobility and εs is permittivity of SiC. Also it can be seen that in this
design, the specific on-resistance is 15% less than the non-punch through design (sequation 2-1).
4.1.2. Base layer
The doping profile and thickness of the base layer affect the current gain of 4H-SiC BJT through
the emitter injection efficiency and base transport factor. A lightly doped thin base layer improves
the emitter injection efficiency and a thin base improves the base transport factor of the BJT.
However, during the blocking mode, the base layer should be designed to provide the required
charge to avoid emitter-collector punch-through in which the depletion regions of reverse biased
emitter-base and collector-base diodes reach each other. This minimum sheet charge density
depends on the required breakdown voltage and the collector doping.
In this work implantation free BJTs were fabricated with a linearly graded base layer (see section
‎4.3).
This design provides a p-doped layer with sufficiently high surface doping concentration for
ohmic contacts to the base. Also high voltage BJTs in this work were terminated with etchedJTE, that requires optimum charge density in the base layer during blocking mode for an
efficient etched JTE (see section ‎4.4.2).
4.1.3. Emitter Layer
The emitter layer of the 4H-SiC BJT should be highly n-doped to obtain low contact resistance.
However, the emitter injection efficiency can be degraded by a too highly doped emitter layer due
to doping induced bandgap narrowing [107]. For the optimum injection efficiency, the emitter
layer is designed with doping concentration of ~mid 1018 -1019 cm-3 followed by a thin n+ cap
layer with higher doping of 3×1019 cm-3 for improved contact resistance.
4.1.4. BJT Layout
To fully implement the performance of power BJTs, special care must be taken for designing the
layout of these devices. For vertical BJTs and due to the emitter current crowding, the current
capability does not scale with increasing emitter area and instead it scales with increase in emitter
periphery (for the fixed collector doping profile) [52]. Therefore, the emitter and base contacts
are designed inter-digitated for the maximum emitter periphery (Fig 4.2)
43
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Emitter
Base
Fig. ‎4.2 Example of inter-digitated emitter and base contacts to avoid the emitter size effect for the maximum current capability.
Also it has been shown that minimum distance of 2-3 µm is required between the emitter mesa
and the base contact implant (Wp+) to avoid the effect of implantation-induced defects on the
maximum current gain [52] (see Fig. ‎4.3).
Emitter Contact
Emitter
Base Contact
Base
WP+
Collector
Collector Contact
Fig. ‎4.3 Schematic view of minimum distance (Wp+) between the base contact and base-emitter junction (paper I)
In Paper I we have shown that for non-implanted BJTs the base contact can be placed closer to
the emitter edge with smaller reduction of the maximum current gain compared to the case with
base contact implantation (Fig. ‎4.4). This approach can reduce the base resistance significantly.
Normalized Current Gain β/βmax
44
1
0,8
0,6
Non Ion-Implanetd
0,4
Ion-Impanted
0,2
0
1
2
3
4
Emitter Base distance WP+ (μm)
Fig. ‎4.4 Normalized value of the maximum current gain versus emitter base distance for implanted and non-implanted transistors
(Paper I).
Chapter 4
4.2 Bipolar Transistors with regrown extrinsic base and etched JTE
One problem with ion implantation in SiC is that complete dopant activation is difficult to
achieve even after high-temperature annealing. As discussed earlier, ion implantation generates
lifetime-killing defects that can decrease the current gain and this enforces a design limitation in
the minimum distance (Wp+) between the base contact implant and the base–emitter junction
[52]. To avoid these effects, SiC BJTs with a p+ epitaxially regrown extrinsic base layer has
previously been reported [108], [59]. However, the current gain of SiC BJTs with epitaxially
regrown base has been relatively low, which is associated with the difficulty of removal of the p +
regrown layer from the base–emitter junction. Efficient removal of the remaining p+ regrown
layer from the surface of the emitter–base junction using combined dry etching and thermal
oxidation can increase the maximum current gain (Paper VII). A cross section view and I-V
characteristics of a large bipolar transistor 1.8 × 1.8 mm (with an active area of 3.24 mm2,
including metal pads) with regrown extrinsic base and etched JTE is shown in Fig. ‎4.5. A
maximum current gain of 42 was measured at Jc = 258 A/cm2 and VCE = 3.7 V. The specific onresistance is also recorded as RSP_ON =9 mΩcm2. A stable open-base breakdown of 1750 V at Jc =
2.5 mA/cm2 was obtained. However, there is an isolation trenching which is about 170 nm deep
in this structure, due to over-etching of the p+ regrown layer. This trenching increases the base
resistance; furthermore, process optimization is necessary to reduce the isolation trench depth.
Fig. ‎4.5 Cross Section view and IV characteristics of 4H-SiC BJT with regrown extrinsic base and etched JTE (paper VII)
4.3 Bipolar Transistors with linearly graded base layer and epitaxial JTE
To avoid problems related to the regrown base layer, implantation free 4H-SiC BJTs with linearly
graded base layer have been demonstrated (Paper I). Fig. ‎4.6 displays the cross section view and
SIMS profile of the base layer that is 730 nm linearly graded Al doped with a peak concentration
45
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
of 3.5×1017 cm−3 at the interface to the emitter. This design provides a p-doped layer with
sufficiently high surface doping concentration for ohmic contacts to the base [109] and a sheet
charge density of about 1.6×1013 cm−2 remaining after emitter mesa etching to form an efficient
JTE. Room temperature I-V characteristics of a small area BJT (Fig. ‎4.7) shows a commonemitter current gain as high as 50, an open-base breakdown voltage of 2700 V and an onresistance of 12 mΩcm2. Also, this design shows improvement in a reduced emitter-size effect
and allows placing the base contact closer to the emitter edge, resulting in a lower base resistance.
This structure provides high breakdown voltage utilizing a simple type of etched JTE without
additional mask steps. However achieving an optimum dose of remaining JTE charge using
additional mask steps to obtain a number of etched-steps for a fully efficient JTE needs more
analysis.
Fig. ‎4.6 Cross section view of and Al SIMS profile of the base epilayer indicating the position of the base
contact and the dose of the etched epitaxial JTE (The JTE length is not to scale) (paper I)
0
0,12
500
1000
β=50
Ron= 12 mΩ‎cm2
0,1
1500
2000
2500
3000
80
IB=0.5 mA/Step
BVCEO= 2.7 kV
0,06
40
Ic(μA)
60
0,08
Ic(A)
46
0,04
20
0,02
0
0
0
5
10
15
20
Collector-emitter Voltage VCE(V)
Fig. ‎4.7 Room-temperature IC versus VCE characteristics and open base blocking characteristics of the SiC BJTs with graded
profile base layer (Paper I).
Chapter 4
4.4 Etched Junction Termination Extension for High Power Devices
To utilize the high breakdown field in a high-voltage device, an efficient junction termination is
needed. Among different high-voltage junction termination techniques, multistep junction
termination extensions (MJTEs) and mesa-JTE termination provided by ion implantation have
been considered as applicable methods due to their simple design and processing techniques [88],
[110]. The key step is to achieve an accurate dose of implanted charge that becomes completely
depleted close to the surface at the desired breakdown voltage, thereby reducing the maximum
electric field in the edge region. However, any implantation step is strongly dependent on the
activation of implanted dopants that can differ with annealing temperature and time.
Furthermore, defect generation during implantation and surface degradation during post
implantation anneal affect the device performance. In the following sections, two types of high
power devices (PiN diode and BJT) are reported utilizing single and double etched JTEs. Also to
study the effect of different JTE doses on breakdown voltage and to optimize the design, 2-D
device simulations were carried out (using Sentaurus TCAD) and compared with experimental
results.
4.4.1. High-Voltage 4H-SiC PiN Diodes with Etched JTE
In this design, mesa-etched single- and double-zone JTEs with different doses have been formed
by controlled etching into the epitaxially grown p-doped layer as a modification to the implanted
etched JTE termination. This method is based on a precise etch-depth control and it is therefore
affected by variation in thickness and doping profile of the base epitaxial layer. This sensitivity
can, however, be significantly reduced by introducing a double-zone JTE that can act as a
controlling tool for compensation of possible variations in processing conditions (Paper II). Fig.
‎4.8
shows a cross-sectional view and the I–V characteristics of a fabricated circular PiN diode
with a 200-μm diameter anode contact. Inductively coupled plasma etching with an oxide mask
was used to isolate the devices and to define the JTE zones. Different depths (D1 = D2) for a
single-zone JTE and D1 (JTE1) < D2 (JTE2) for a double-zone JTE with the same JTE length of
100 μm were etched into the p-doped epilayer to find an optimum dose of the remaining dopants
for maximizing the breakdown voltage. I–V curves of this diode show a forward-voltage drop of
3.25 V at 100 A/cm2 and a breakdown voltage of 4.3 kV for the optimized double-zone JTE
structure.
47
48
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Fig. ‎4.8 Cross-sectional view (top) and measured I–V characteristics (bottom) of a fabricated circular optimally dosed doublezone JTE PiN diode BJT (Paper II)
Fig. ‎4.9 shows simulated and measured breakdown voltage of fabricated PiN diodes as a function
of remaining dose in the etched p-doped layer. In this figure, the x-axis refers to the dose for
single-zone JTE and to the dose in the JTE1 (the inner JTE zone) for the double-zone JTE. Our
results indicate that the dose of ~1.2×1013 cm-2 is an optimum point for the single-zone JTE,
which yields a stable breakdown voltage of 4.0 kV. However the optimum dose range is very
narrow since the single-zone JTE suffers from an abrupt reduction of breakdown voltage for
doses higher than optimum. Being in good agreement with simulation and comparing to singlezone JTE, improved and more stable breakdown performance is achieved by applying a doublezone JTE. In this design, the dose in JTE2 was tuned in the range of 30-70% of JTE1 with step-
Chapter 4
by-step etching of D2 while keeping the total JTE length constant. Although this design does not
improve the breakdown voltage for lower doses in JTE1, it improves the breakdown voltage to
4.3 kV for higher doses (indicated by the arrows in the picture). This breakdown voltage is 80%
of the theoretical value and corresponds to a JTE1 dose of 1.5×1013 cm-2 (D1= 1.2 µm) and a
JTE2 dose of 1×1013 cm-2 (D2= 1.35 µm). The results in Fig. ‎4.9 indicate that a double-zone JTE
can decrease the sensitivity of the breakdown voltage to the dose of remaining dopants compared
to a single-zone JTE while keeping the total JTE length constant. Therefore, the introduction of
a second JTE zone reduces the sensitivity to variations in processing conditions such as RIE
etch-rate as well for a non-uniform thickness and doping profile in the epitaxial layer.
6
Upper Bound
BV (kV)
5
Simulation (Single-JTE)
Simulation (Double-JTE)
4
Measurement (Single-JTE)
Measurement (Double-JTE)
3
2
1
× 1013
0
0
0,5
1
1,5
Dose in JTE
2
2,5
(cm-2)
Fig. ‎4.9 Simulated and experimental breakdown voltage as a function of remaining dose in the JTE. The x-axis refers to the dose
for single-zone JTE and the dose in JTE1 for the double-zone JTE (Paper II).
Fig. ‎4.10 shows a localized avalanche breakdown that is visible as a bright spot in
electroluminescence. There is a transfer of the maximum electric field from the outer edge of the
single-zone JTE with a high dose of 2.2×1013 cm-2 to the inner edge with lower dose of 5×1012
cm-2. The location of the electric field peak was also confirmed by device simulation. Electric
field distributions were simulated for the different JTE doses in Fig. ‎4.11. It can be shown that
for the optimum dose of dopants, the single-zone JTE is fully depleted at avalanche breakdown
and acts as a highly resistive layer. Compared with non-optimum doses, this case provides a
balanced electric field distribution both at the inner and outer edge of the diode which results in a
stable breakdown voltage of 4 kV. For the double-zone JTE, where the JTE2 is fully depleted at
lower voltage compared to JTE1, the electric field peak at the outer JTE edge was reduced and a
higher breakdown voltage of 4.3 kV was obtained.
49
50
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Fig. ‎4.10 Electroluminescence (visible and near infrared wavelength) for single-zone JTE at low breakdown of 1.5 kV (Paper II).
a)
b)
Fig. ‎4.11 Electric field distribution for a) single-zone JTE at breakdown. The high, optimum and low doses were 2.2x1013,
1.2x1013 and 5x1012 cm-2 respectively. (b) A comparison of the electric field distribution for single-zone JTE (D1=D2=1.2 µm) and
double-zone JTE (D1=1.2 µm and D2=1.33 µm) at 3kV (Paper II).
Chapter 4
4.4.2. High Voltage 4H-SiC BJT with Etched JTE
After successful demonstration of implantation free PiN diodes with etched-JTE, the same type
of termination was implemented in bipolar transistors. Therefore, in this step BJTs with etched
JTE were fabricated and simulated to determine the optimum dose of dopants in the etched JTE
area and optimize the open-base breakdown voltage. Fig. ‎4.12 shows a cross sectional view of the
fabricated 4H-SiC BJTs with the etched JTE. In this work, inductively coupled plasma (ICP)
etching with an oxide mask was used to form emitter and base mesas. Step-height controlled ICP
etching into the p-doped base layer with different etch depths corresponding to different doses
of dopants in the JTE for each die was applied on the same wafer using 100µm JTE length.
200 nm
ND = 3 . 10 19 cm -3
1300 nm
ND = 1 . 10 19 cm -3
600 nm
25μm
Etched-JTE
NA ≈‎9‎. 10 17 cm -3 (graded)
ND = 3 . 10 15 cm -3
N+ Substrate
Fig. ‎4.12 Cross sectional view of the fabricated 4H-SiC BJTs with etched-JTE.
Simulated and measured open-base breakdown voltage of non-passivated 4H-SiC BJTs with
etched JTE as function of remaining dose in the etched p-doped layer is shown in Fig. ‎4.13. Our
experimental results that are in agreement with simulation indicate that the dose of 1.2-1.3×1013
cm-2 is an optimum point for the single-zone JTE, which yields a stable breakdown voltage of 3.2
kV which is 67% of theoretical value of 4.8 kV. However an abrupt reduction of breakdown
voltage for non-optimum doses was observed that can be explained by a non-uniform electric
field distribution in the JTE area during blocking.
An overlay of electroluminescence and un-biased optical imaging of BJTs with etched JTE at the
breakdown are shown in Fig. ‎4.14 (a-b). These images illustrate the transfer of maximum electric
field, that is confirmed by localized luminescence, from the outer edge of the JTE with a high
dose of 1.65×1013 cm-2 to the inner edge with the lower dose of 1×1013 cm-2. This transfer is also
confirmed from an un-balanced electric field distribution at the edges for non-optimum JTE
doses in device simulation (Fig. ‎4.14c).
51
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
5
Simulation
Measurement
4,5
4
BV (kV)
3,5
3
2,5
2
1,5
0,90
1,00
1,10
1,20
1,30
1,40
1,50
1,60
1,70
Dose ( x1013 cm -2)
Fig. ‎4.13 The simulated and measured open-base breakdown voltage of fabricated 4H-SiC BJTs with etched JTE as a function of
remaining dose of dopants in the etched p-doped layer.
(a)
(b)
(c)
4,0
3,5
Electric Field (MV/cm)
52
high dose
low dose
3,0
2,5
2,0
1,5
1,0
0,5
0,0
N
P
N
Fig. ‎4.14 An overlay of electroluminescence and un-biased optical imaging of a) low-dose (1×1013 cm-2) and b) high-dose
(1.65×1013 cm-2) BJTs with etched-JTE at avalanche breakdown. c) Simulation of electric field distribution at the edges for nonoptimum JTE doses (Paper IV).
Chapter 4
4.5 Surface Passivation Influence on the Performance of 4H-SiC BJTs
It was discussed earlier that since BJTs are current controlled devices, achieving high current gain
(β = IC/IB) while maintaining the high voltage blocking capability is a critical issue for practical
applications. Minimizing the surface recombination current by improving the surface passivation
is a key step for improving the maximum current gain [52]. The surface recombination current
can be correlated with the interface trap density that depends on the quality of the SiC/SiO 2
interface in the base-emitter region [111]. It has been experimentally shown that oxidation or
post-oxidation anneal in NO or N2O ambient can improve the quality of the SiO2/SiC interface
and thereby decrease the trap density at the base-emitter junction sidewall [112] - [113] and along
the exposed base surface between the emitter edge and the base contact. However a comparative
study of the influence of different passivation layers on the performance of 4H-SiC BJTs
fabricated from the same wafer is still missing. Investigations performed on the same wafer
strengthen the experimental study because the carrier lifetime can vary considerably for wafers
with different epitaxial material quality, and this, together with variations in base and emitter
doping and thickness, can influence the current gain. In this part the electrical performance of the
BJTs with SiO2 surface passivation layers fabricated under different conditions are analyzed. In
order to understand the effective influence of the interface traps on electrical performance of
4H-SiC BJTs including the maximum current gain and breakdown voltage, two dimensional
device simulations have been performed and compared with experimental results. Interface trap
charges and fixed oxide charges were evaluated through MOS structures on n-type 4H-SiC
substrate that have the same passivation as the SiC BJTs. The process conditions for different
surface passivations aiming for 50 nm oxide thickness are summarized in Table ‎4-1.
Table ‎4-1 Processing parameters of passivation layers fabricated with different oxidation processes.
Oxidation/Deposition
Sample
gas species
T(°C)
1
N2O
N2O
2
NO
3
Annealing
Time
gas species
T(°C)
1250
-
-
-
NO
1200
-
-
-
O2
O2
1100
-
-
-
4
TEOS-N2O
Si(OC2H5)4
680
N2O
1100
3
5
TEOS-Wet
Si(OC2H5)4
680
H2O:O2
950
3
6
PECVD-N2O
SiH4:N2O
300
N2O
1100
3
(Hours)
53
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Fig. ‎4.15 shows forward and reverse normalized C-V and G-V curves for n-type 4H-SiC MOS
capacitors passivated with oxide layers fabricated under four different process conditions. The
solid gray curve represents the ideal MOS capacitor with no interface or oxide charges. It can be
seen that in comparison of different passivation layers, the PECVD-N2O sample has no
hysteresis behaviour and a small flat-band voltage shift. The G-V plot displays a sharp and low
intensity peak that corresponds to minimal surface potential fluctuations and a low Dit value at
the SiO2/SiC interface (Table ‎4-2). The TEOS-N2O sample with more flat-band voltage shift and
the N2O sample with hysteresis behaviour indicate higher values of interface trap densities
compared to the PECVD-N2O sample, as confirmed also from larger conductance peaks. The O2
sample has a pronounced stretched out C-V curve, a larger flat-band voltage and an intense
conductance peak resulting in higher effective oxide charge and higher interface traps. Table ‎4-2
summarizes the extracted values of oxide charge (Qeff/q), and interface trap density (Dit) for
different layers. It can be seen that the PECVD-N2O sample has the lowest interface trap density
Norm. Conductance G/(Cox)
of 4.25×1011 cm-2 as determined at 0.35 eV below the conduction band.
Norm. Capacitance C/C ox
54
PECVD-N2O
1,0
N2O
TEOS-N2O
0,8
O2
Ideal curve
0,6
0,4
T = 295 K
 = 10 kHz
0,2
0,0
-20
-10
0
10
PECVD-N2O
0,8
N2O
TEOS-N2O
0,6
0,4
O2
T = 295 K
 = 10 kHz
0,2
0,0
-20
-10
0
10
Voltage (V)
Voltage (V)
Fig. ‎4.15 Forward and reverse normalized C-V (a) and G-V (b) curves taken on n-type 4H-SiC MOS capacitors fabricated by
different processing conditions (Paper IV).
Table ‎4-2 Effective oxide charge (Qeff/q), and interface traps density (Dit) of selected passivation layers fabricated with
different oxidation processes using C-G-V method.
Qeff/q
Dit*
sample
(1011 cm-2)
(1011 cm-2eV-1)
N2O
-7.5
23.1
O2
-26.7
129.2
TEOS-N2O
-9.1
28.7
PECVD-N2O
4.6
4.25
Chapter 4
A statistical comparison of maximum current gain for the fabricated 4H-SiC BJTs passivated
with different layers is shown in Fig. ‎4.16. The provided data has been extracted from ten
transistors for each type of passivation to enable an accurate comparison. It can be seen that the
PECVD-N2O sample has the highest current gain of 40 in comparison with other passivation
layers such as TEOS-N2O, TEOS-Wet, N2O, NO and O2 with average current gains of 30, 26,
24, 23 and 17 respectively. This higher value is likely related to a higher quality of the surface
passivation with a lower interface trap density near the conduction band resulting in less surface
recombination current at the base-emitter junction sidewall and along the exposed base surface.
Therefore, our results indicate that the new type of BJT surface passivation layer consisting of a
PECVD deposited oxide layer followed by post-deposition anneal in N2O ambient can offer 60%
increase in the maximum current gain compared to silicon dioxide layers that are thermally grown
in N2O or NO ambient.
45
40
Gain
35
30
25
20
15
TEOS-N2O
TEOS-Wet
N2O
O2
NO
PECVD-N2O
Fig. ‎4.16 Statistical comparison of maximum measured current gain for 4H-SiC BJTs passivated with SiO2 layers fabricated using
different techniques (Paper IV).
The average open-base breakdown voltage values in Fig. ‎4.17 demonstrate a pronounced
dependence of the breakdown voltage on the type of surface passivation layer. The O2 and
PECVD-N2O samples show the lowest breakdown voltage of 2kV and 2.3kV compared to N2O
and TEOS-Wet samples with a breakdown voltage of 3kV. It is suggested that breakdown
voltage variation depends on variation in surface charge for the different passivation layers that
changes the optimum dose of implanted and activated dopants in the JTE area.
55
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
4
Open Base Breakdown (kV)
3,5
3
2,5
2
1,5
1
0,5
0
TEOS-N2O
TEOS-Wet
N2O
O2
NO
PECVD-N2O
Fig. ‎4.17 Measured average open-base breakdown voltage values for five BJTs with different passivation layers (Paper IV).
The effect of passivation oxide charge on the optimum dose of the JTE according to device
simulation is shown in Fig. ‎4.18. This simulation was based on extracted charge data in Table ‎4-2
and indicates a pronounced variation in the optimum JTE dose when the oxide charge is
significant compared to the JTE dose (>10%). Therefore, the reduction of breakdown voltage
for the PECVD-N2O and the O2 passivation oxides can be attributed to a different effective
oxide charge that affects the optimum JTE dose in the implanted transistors. Consequently,
applying new surface passivation layers can reduce the interface state density but potentially
degrade the blocking performance if the junction termination is not re-designed.
14
Optimum JTE dose ( ×1012 cm-2)
56
PECVD-N2O
13
12
N2O
11
O2
10
9
8
-3
-2
-1
0
1
Effective Oxide charge (×1012 cm-2)
Fig. ‎4.18 Simulated optimum dose of the etched JTE vs. effective oxide charge. Simulations were performed using the extracted
values of surface charge for the different passivation layers as specified in Table ‎4-2 (Paper IV).
Chapter 4
4.6 Influence of Crystal Orientation on the Current Gain of 4H-SiC BJTs
Conventionally, vertical 4H-SiC BJTs are fabricated along the [1100] or [1120] direction on
(0001) Si-face. However due to anisotropic properties of 8° off-axis 4H-SiC, different
orientations on Si-face can also affect the base current of the BJT through variation of mobility
and interface traps density distribution along each direction. Therefore single finger BJTs with
emitter fingers oriented the [1210], [0110], [1120] and [1100] directions were fabricated in the
same processing steps and compared before and after surface passivation (Paper V). Fig. ‎4.19
shows a perspective view of fabricated BJTs with different orientations that were labeled from 0°
to 180° relative to the conventional [1100] direction.
Fig. ‎4.19 Perspective view of single-finger BJTs along with different directions
Fig. ‎4.20 shows a comparison of the maximum current gain of BJTs with different orientations
relative to the [1100] direction (0°) before and after surface passivation and contact metallization.
The results indicate that the maximum current gain before passivation is orientation-dependent
and has a maximum value for BJTs with the emitter edge aligned to the [1120] direction (90°) and
shows the lowest value for the BJTs with emitter edge aligned to the [1210] direction (30°).
However, after surface passivation the current gain is improved to a similar value for all
directions. The variation of the current gain for different directions before surface passivation
could be caused by a different distribution of interface traps between the native oxide and emitter
sidewall for each direction. However uniform behavior of the current gain in all directions
indicates that surface passivation minimizes the interface traps on the area between base contact
and the emitter mesa sidewall and improves the current gain to higher values.
57
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
(a)
70
Current Gain
60
50
40
30
20
10
Max
Avg+σ
Avg.
Avg-σ
Min
120
150
0
0
30
60
90
180
Degree
(b)
70
60
Current Gain
58
50
40
30
20
10
Max
Avg+σ
Avg.
Avg-σ
Min
0
0
30
60
90
120
150
180
Degree
Fig. ‎4.20 Comparison of the maximum current gain for different orientations a) before and b) after surface passivation (9
transistors measured per direction) (Paper V).
Based on the these results we can speculate that similar to small area BJTs, the performance of
large area multi-finger BJTs in term of maximum current gain is not orientation dependant and
designers can align emitter fingers to any direction on 4H-SiC substrates.
4.7 2.8 kV Bipolar Transistors with Improved Junction Termination
In section ‎4.3 the bipolar transistor with graded base layer was reported. In this section the
modified version of this type of transistor aiming for higher breakdown voltage and improved
performance of large area devices is revealed. A cross sectional view of a fabricated 4H-SiC BJT
with four epitaxial layers grown in one continuous run on is shown in Fig. ‎4.21.
Chapter 4
N D = 2 . 1019 cm-3, 0.2 μm
JTE2
N D = 8 . 1018 cm-3 , 1.35 μm
JTE1
JTE1
N A = 4.3 . 10 17 cm -3, 0.65 μm
JTE2
N D = 6 . 10 15 cm -3, 25 μm
N + Substrate
Fig. ‎4.21 A cross-sectional view of 2.8kV 4H-SiC BJTs with two-zone JTE (Paper VI).
Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base
mesas and also a well controlled two-zone etched JTE. It was previously reported that two-zone
JTE can improve the blocking performance of the PiN diode to 75% of the parallel-plane
breakdown voltage, and the optimum remaining dose in JTE for the maximum breakdown is
around 1.2-1.3×1013 cm-2. Also the passivation layer introduces extra charge close to the interface
and this charge can affect the optimum dose in the JTE. Therefore the performance of the device
in the blocking mode with and without additional charges from the surface passivation layer was
simulated using physical device simulation software Sentaurus TCAD (Fig. ‎4.22). The simulation
shows that for the passivated surface without extra charges and for the single-JTE, the
breakdown voltage is optimal for the dose of 1.45×1013 cm-2 in the JTE while the passivated
layer with the extra charge shows an optimum breakdown for the dose of 1.5×1013 cm-2.
Implementation of a two-zone etched-JTE has the advantage of showing less sensitivity for the
breakdown voltage to the JTE dose. Therefore in this design, the devices were terminated with
controlled etching into the base layer aiming for two-zone etched JTE with the dose of 1.5×1013
cm-2 in the JTE1 and dose of 9 ×1012 cm-2 in JTE2 to obtain maximum blocking capability.
4000
Breakdown Voltage (V)
3500
3000
2500
2000
Single JTE No extra Charge
1500
Single JTE, Extra Charge
1000
Double JTE, Extra Charge
500
0
1,2
1,3
1,4
Dose (
1,5
1013
cm
1,6
1,7
-2 )
Fig. ‎4.22 Simulation of breakdown voltage vs. remaining dose in the etched JTE1 (Paper VI).
59
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
The surface passivation was fabricated by 50 nm PEVCD SiO2 followed by a post deposition
anneal in N2O ambient at 1100 °C for 3 hours to minimize the interface charges at the SiC/SiO 2
interface. Also a 2µm-thick oxide layer was deposited to protect the passivation layer. Ni was
used for emitter and collector contacts while a triple layer of Ni/Ti/Al was deposited for the base
contacts. The metals were annealed in Ar ambient at 950 °C and 800 °C respectively, to provide
low resistive ohmic contacts to the emitter and base layers. The fabrication process of the devices
was then followed by two layers Al metallization to connect the interdigitated emitter and base
fingers to overlying pads for wire bonding.
a)
0
300
600
900
0,4
Ron= 4 mΩ‎cm2
β=55
0,35
1200 1500 1800 2100 2400 2700 3000
80
IB=1 mA/Step
BVCEO= 2,8 kV
60
0,3
40
0,2
Ic(uA)
Ic(A)
0,25
0,15
20
0,1
0,05
0
0
0
5
10
15
20
Collector-emitter Voltage VCE(V)
b)
0
300
600
900
10
1200 1500 1800 2100 2400 2700 3000
120
9
β=52 RON=6.8 mΩ·cm2
8
IB=20 mA/Step
100
BVCEO= 2,8 kV
7
80
6
60
5
4
Ic(uA)
Ic(A)
60
40
3
2
20
1
0
0
0
5
10
15
20
Collector-emitter Voltage VCE(V)
Fig. ‎4.23 Room temperature IV characteristics of a) 0.04 mm2 and b) 3.0 mm2 BJT (Paper VI).
Room temperature IV characteristics using Tektronix 370B curve tracer for small and large area
devices are shown in Fig. ‎4.23. The small area BJT with the die size of 0.3 × 0.3 mm and active
Chapter 4
area of 0.04 mm2 (excluding the contact pads) shows a maximum dc current gain of 55 and RON
= 4 mΩcm2. The large area device with the die size of 1.8 × 1.8 mm and active area of 3.0 mm2
shows a maximum dc current gain of 52 and RON = 6.8 mΩcm2. The open-base breakdown
voltages for both small and large area devices are 2.8 kV which is 75% of the parallel-plane
breakdown voltage. The high breakdown voltage is achieved utilizing a controlled two-zone
etched JTE that provides an accurate dose in the base layer that becomes completely depleted
close to the surface for higher breakdown voltages, thereby reducing the maximum electric field
in the edge region.
4.7.1. Degradation
As discussed earlier, bipolar degradation and current gain degradation are regarded as major
challenges for the commercialization of 4H-SiC BJTs. Fig. ‎4.24 is the I-V characteristics of small
and large are BJTs (see section ‎4.7). The small area BJT shows low current gain degradation after
150 Hrs stress of the base-emitter diode with a current level of 0.2A while the large are BJT
shows significant bipolar and current gain degradation after 10 Hrs of stress (Ib=0.2 A and
Ic=4A). These results indicate the possibility of reducing bipolar degradation for smaller area
BJTs that can be due to the lower chance of presence of basal plane dislocations (BPDs) in the
substrate and epitaxial layers while for large area BJTs, the probability of presence of BPDs is
higher.
10
0,35
Before Stress
9
Ib200mA_40Hrs
8
Ib200mA_150Hrs
7
Before
Ib0.3AIc4A_30min
0,3
0,25
Ib0,3AIc4A_10Hrs
6
Ic
Ic
0,2
0,15
5
4
3
0,1
2
0,05
1
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
VCE
VCE
Fig. ‎4.24 I-V characteristics of 4H-SiC BJTs before and after stress a)small are BJT (stress of Ib= 0.2 A) and b) large area BJT
(stress of Ib=0.2A and Ic=4A)
4.7.2. Switching Characteristics
Switching measurement for a large area BJT with active area of 3 mm2 was carried out with a
driver circuit that is schematically demonstrated in Fig. ‎4.25. In this topology the passive network
composed of a resistance R2 for DC biasing and a series connection of R1 and C1 for dynamic
61
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
overshoot of the base current during turn on and off. A double pulse is fed to the gate driver of
IXDN509 to ramp up the inductor current. The BJT acts as a switch for a 5 mH inductive load
with a 1200V 8A Schottky diode from Infineon (IDH08S120) as a freewheeling diode.
Fig. ‎4.25 Schematic of the test circuit for switching high voltage BJT.
The turn-on and turn-off transients for 400V switching are shown in Fig. ‎4.26. The large area
BJT shows a VCE fall time of 18 ns during turn-on and a VCE rise time of 10 ns during turn-off.
The fast switching without the current tail shows the potential for significantly smaller power
losses compared to a Si IGBT.
a)
14
500
12
400
10
Ic (A)
Ic
6
200
Vce
4
V CE (V)
300
8
100
2
0
0
-2
-100
-0,1
-0,05
0
0,05
0,1
Time(µS)
b)
12
500
10
400
Vce
6
300
4
200
V CE (V)
Ic
8
Ic (A)
62
2
100
0
-2
0
-0,1
-0,05
0
0,05
0,1
Time(µS)
Fig. ‎4.26 Transient characteristics of large area BJT for 400V switch during a) Turn-on and b) Turn-off
Chapter 4
4.8 Monolithic Darlington Transistors
As discussed earlier, increasing the current gain by two cascaded BJTs in Darlington
configuration is a potential solution for high power applications at the expense of higher forward
voltage drop. In this section, implantation-free Darlington transistors in two configurations are
reported. Cross section views of a fabricated Darlington with isolated (D1) and non-isolated base
layers (D2) are shown in Fig. ‎4.27. The non-isolated base layer affects the forward conduction by
higher base resistance that decreases the maximum current gain and it also introduces a base
current-offset for triggering the driver BJT. Fig. ‎4.28.a is room temperature I-V characteristics of
the Darlington transistor with isolated base layer (D1). The device shows a maximum current
gain of 2900 and on-resistance of 20 mΩcm2 at 3.5 V in forward conduction. The high current
gain is attributed to a well- designed ratio of the active area of the driver BJT to the output BJT
(1:10). The measured open-base breakdown voltage of 1kV is well below the ideal value and this
is due to the absence of junction termination. Fabrication of a junction termination is more
complicated for the isolated Darlington due to its isolation trench between driver and output BJT
that can result in electric field crowding at the trench corner.
The forward characteristic of the Darlington transistor with non-isolated base layer (D2) is
shown in Fig. ‎4.28.b. This device shows a maximum current gain of 1000 (at JC = 475 A/cm2 and
VCE = 10V). In this design, the non-isolated base layer can be modeled as a resistance between
the base and emitter of the driver BJT that consumes some percentage of the base current.
Therefore the maximum current gain is lower than D1 and 1mA is aquired as threshold base
current to forward bias the base-emitter diode of the driver BJT. However, this device shows
higher open-base breakdown voltage of 2.8 kV which is 75% of the parallel–plane breakdown
voltage. Increasing the resistance between base and emitter by increasing the distance between
driver and output BJT or by making a narrower connection can be beneficial to achieve higher
current gain and reduced threshold base current.
The forward characteristic of the Darlington transistor with non-isolated base layer (D2) is
shown in Fig. ‎4.28.b. This device shows a maximum current gain of 1000 (at JC = 475 A/cm2 and
VCE = 10V). In this design, the non-isolated base layer can be modeled as a resistance between
the base and emitter of the driver BJT that consumes some percentage of the base current.
Therefore the maximum current gain is lower than D1 and 1mA is aquired as threshold base
current to forward bias the base-emitter diode of the driver BJT. However, this device shows
63
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
a)
Emitter
Emitter
7 µm
Base
Base
1.2 µm
Collector
b)
2-step etched-JTE
Emitter
Emitter
Base
150 µm
Collector
Fig. ‎4.27 Cross section view of fabricated Darlington a) with isolated base layer (D1) and b) with non-isolated base layers (D2)
(Paper III).
a)
-100
100
300
500
700
900
0,8
1100
80
IB=200 µA
Ron= 20 mΩ‎cm2
β=2900
0,7
0,6
BVCEO= 1 kV
IB=150 µA
60
0,4
40
IB=100 µA
Ic(uA)
Ic(A)
0,5
0,3
0,2
20
IB=50 µA
0,1
0
0
0
5
10
15
20
Collector-emitter Voltage VCE(V)
b)
300
600
900
Ron= 20 mΩ‎cm2
β=1000
3
1200 1500 1800 2100 2400 2700 3000
80
IB=3 mA
BVCEO= 2.8 kV
2,5
2
IB=2.5 mA
60
IB=2 mA
40
1,5
1
IB=1.5 mA
Ic(uA)
0
3,5
Ic(A)
64
20
0,5
IB=1 mA
0
0
5
10
15
0
20
25
30
Collector-emitter Voltage VCE(V)
Fig. ‎4.28 Room temperature I-V characteristics of the Darlington transistor a) with isolated base layer (D1) and b) with nonisolated base layers (D2) (Paper III).
Chapter 4
higher open-base breakdown voltage of 2.8 kV which is 75% of the parallel–plane breakdown
voltage. Increasing the resistance between base and emitter by increasing the distance between
driver and output BJT or by making a narrower connection can be beneficial to achieve higher
current gain and reduced threshold base current.
4.9 High Temperature Characteristics
For high temperature applications, bipolar transistors are preferred devices due to the negative
temperature coefficient of the current gain and positive temperature coefficient of the onresistance. This feature enhances the parallel connection capability of these types of devices by
decreasing the risk for thermal runaway in which the current increases in a positive feedback with
temperature. For the current gain, it is believed based on device simulations that at higher
temperatures, the ionization of deep level acceptors (Al) in the base layer increases which results
in a reduction of the emitter injection efficiency. Also decrease in the mobility of the drift layer at
higher temperature results in the increase of the on-resistance in the BJTs. High temperature
performance of the small and large area transistors (see section ‎4.7) are demonstrated in Fig. ‎4.29.
The small area device shows a negative temperature coefficient of the maximum current gain that
decreases from 55 at room temperature to 26 at 200 °C while the on-resistance increases from 4
mΩcm2 to 10.2 mΩcm2 at 200 °C. Also, the large area BJT performs in a similar way and shows a
decrease of maximum current gain from 52 to 24 and increase of on-resistance from 6.8 mΩcm2
to 27 mΩcm2 at 200 °C. The resistance of the drift layer is calculated as 3 mΩcm2 indicating that
there is no significant conductivity modulation in these devices.
The negative temperature coefficient of the current gain for the Darlington transistor with
isolated base layer (D1) and the driver BJT is shown in Fig. ‎4.30. It can be seen that both the
driver BJT and the Darlington pair follow the β
Darlington
= β
(Driver BJT)
× β
(Output BJT)
formula at
elevated temperatures and the Darlington device shows a second order negative temperature
coefficient of the current gain. The maximum current gain for the Darlington is measured as high
as 640 at 200 °C that corresponds to the current gain of 25 for the driver BJT.
65
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
60
12
50
10
40
8
30
6
20
4
10
2
0
RON (mΩ.cm2)
Maximum Current Gain
a)
0
0
50
100
150
200
250
Temperature (°C)
60
30
50
25
40
20
30
15
20
10
10
5
0
RON (mΩ.cm2)
Maximum Current Gain
b)
0
0
50
100
150
200
250
Temperature (°C)
3500
60
3000
50
2500
40
2000
30
1500
20
1000
10
500
0
BJT Maximum Current Gain
Fig. ‎4.29 High temperature performance of a) small and b) large area devices
Darlinton Maximum Current Gain
66
0
0
50
100
150
200
250
Temperature (°C)
Fig. ‎4.30 Temperature dependence of the current gain for the Darlington transistor with isolated base layer and the driver BJT.
Chapter 5
5 Summary and Future Outlook
The SiC BJTs is one candidate for high power applications due to its low power on-state loss and
fast switching capability. A SiC BJT shows negative temperature coefficient of the current gain
and also positive temperature coefficient of the specific ON-resistance that are desired for
paralleling in the power circuits. Also for a SiC BJT, second breakdown occurs at a very high
current density which is well outside the normal operation area of the device. However to
compete with other switching devices, it is necessary for a power SiC BJT to provide higher
current gain for more efficient power switching and for high voltages they should also
demonstrate conductivity modulation in the saturation region for the lowest ON-resistance. The
main obstacle for commercialization of 4H-SiC BJTs is degradation of the forward voltage drop
(VCESAT) and of the current gain, under forward bias stress. Degradation of V CESAT is mainly
attributed to carrier trapping and recombination in the base and/or collector due to the SSFs, but
the reason for gain degradation is not clear and different possible mechanisms have been
proposed.
To avoid problems associated with ion implantation, SiC BJTs with a p+ epitaxially regrown
extrinsic base layer are reported. Also it was shown that efficient removal of the remaining p+
67
68
Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
regrown layer from the surface of the emitter–base junction using combined dry etching and
thermal oxidation can increase the maximum current gain. Furthermore, implantation free 4HSiC BJTs with linearly graded base layer have been demonstrated with common-emitter current
gain of 50 and an open-base breakdown voltage of 2700 V and on-resistance of 12 mΩcm2. In
this design, high breakdown voltage was obtained using a simple type of etched JTE without
additional mask steps. High voltage PiN diodes were fabricated, characterized and analyzed to
determine an optimum dose of remaining JTE charge and the number of required etch steps for
a fully efficient JTE. Physical device simulation and experimental results indicate that for a high
voltage PiN diode, a double-zone JTE can decrease the sensitivity of the breakdown voltage to
the dose of remaining dopants compared to a single-zone JTE while keeping the total JTE length
constant and, consequently, PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about
80% of the theoretical value) were fabricated with double-zone JTE. The dependence of openbase breakdown voltage of 4H-SiC BJTs to the dose of remaining dopants in the etched JTE
indicate that the dose of 1.2-1.3×1013 cm-2 is an optimum point for the single-zone JTE, which
yields a stable breakdown voltage that is about 67% of theoretical value.
Surface passivation of 4H-SiC BJT is an essential factor for efficient power BJTs. Therefore
different passivation techniques were compared and showed that around 60% higher maximum
current gain can be achieved by a new surface passivation layer with low interface trap density.
This layer consists of a PECVD deposited SiO2 layer followed by post-deposition anneal in N2O
ambient. However, for conventional BJTs with implanted JTE, this passivation can provide
different effective oxide charge compared to other passivation layers and this can affect the
optimum doses of implanted dopants in the JTE area, resulting in reduced breakdown voltage.
Therefore, modification of JTE implantation dose may be needed when applying new passivation
layers to high voltage SiC devices.
The new surface passivation along with double-zone JTE were used for fabrication of high
power BJTs. Consequently, we successfully demonstrated 2800 V small and large area BJTs with
a maximum dc current gain of 55 and 52, respectively. The small area BJT showed RON =4
mΩcm2 while for the large are BJT RON = 6.8 mΩcm2.
Finally, the Darlington transistor with a maximum current gain of 2900 at room temperature and
640 at 200 °C is reported. The high current gain is related to the optimum design for the ratio of
the active area of the driver BJT to the output BJT (approximately 1:10). However to avoid
premature breakdown at the isolation trench between driver and output BJT, a Darlington
transistor with non-isolated base layer is reported. The non-isolated Darlington pair shows an
Chapter 5
open-base breakdown voltage of 2.8 kV which is 75% of the parallel–plane breakdown voltage
but shows lower current gain and 1 mA as the threshold current for triggering the driver BJT.
Finally, it is important to address some major issues for the future research on 4H-SiC BJTs:
(1) Higher material quality is required for performance improvement of the device. It has
been shown that fabricated devices on BPD-free substrate, exhibit superior
characteristics in terms of long term stability. Also epitaxial growth of the SiC layers with
lower densities of defects increases the carrier life-time in the base and collector layers
which is required for higher current gain and conductivity modulation.
(2) Although the current gain has been increased through the improved surface passivation
during these years, it is likely that even higher quality passivation layers in terms of lower
interface state densities can be achieved. Therefore it is recommended to continue the
research on SiC passivation aiming to reduce interface state densities.
(3) Simulation of the 4H-SiC BJTs shows that new designs of the base layer in terms of
modified doping profile in the extrinsic base layer can also enhance the performance of
the device by providing higher current gain [114] and also possibility of collector
conductivity modulation. Therefore we recommend to consider various design
modifications for better performance of high voltage BJTs.
(4) One major advantage of SiC BJTs compare to MOSFETs is high temperature robustness.
No device can be fully exploited unless it has a reliable packaging that can handle high
temperatures. Although extensive development has been carried out on more reliable
packages but it seems that more investigation is needed for high temperature packages.
69
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