Power Supply Monitoring Interface (PSMI)
Revision 2.12
Power Supply Management Interface
Design Guide
Revision 2.12
1
Power Supply Monitoring Interface (PSMI)
Revision 2.12
Revision History
2.0
2.1
2.11
2.12
Initial release and public posting to SSI website
Fixed order of efficiency data in the power supply capability records. Shifted power supply capability
registers to allow for 10 min/max voltage limits. Changed wording of efficiency from 1/256% to 1/(256%)
in power supply capability records. Added description in output current capability registers to require max
current capability be defined for all outputs.
Fixed error in Status and Control register; renamed Status Register, shifted bits to include bit 0.
Added supplier ID filed to Header
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
TABLE OF CONTENTS
1
POWER SUPPLY MANAGEMENT INTERFACE (PSMI) OVERVIEW .................................................................4
2
REGISTER DATA ............................................................................................................................................................6
3
PSMI CAPABILITIES......................................................................................................................................................6
4
HEADER ..........................................................................................................................................................................11
5
SENSOR DATA ...............................................................................................................................................................12
5.1
SAMPLING...................................................................................................................................................................12
5.2
TEMPERATURE SENSORS .............................................................................................................................................12
5.3
FAN SPEED SENSORS ...................................................................................................................................................13
5.4
FAN SPEED CONTROLS ...............................................................................................................................................14
5.5
INPUT AND OUTPUT VOLTAGES ...................................................................................................................................14
5.6
INPUT AND OUTPUT CURRENTS ...................................................................................................................................16
5.6.1
Current sensor sampling....................................................................................................................................16
5.6.2
Current Sensors .................................................................................................................................................16
5.6.3
Peak Current Sensors ........................................................................................................................................17
5.6.4
Peak Current Sensor Reset ................................................................................................................................17
6
SHUTDOWN EVENTS...................................................................................................................................................17
6.1
7
SHUTDOWN EVENT RESET ..........................................................................................................................................17
WARNING EVENTS ......................................................................................................................................................18
7.1
8
WARNING EVENT RESET ............................................................................................................................................18
STATUS............................................................................................................................................................................19
8.1
9
STATUS REGISTER RESET ...........................................................................................................................................19
CONTROL .......................................................................................................................................................................20
10
POWER SUPPLY CAPABILITY RECORDS .........................................................................................................21
11
CUSTOM REGISTERS ..............................................................................................................................................23
12
REDUNDANT POWER..............................................................................................................................................23
13
SMBUS COMMUNICATION....................................................................................................................................24
13.1 DEVICE ADDRESS LOCATIONS ....................................................................................................................................24
13.2 SMBALERT# ..............................................................................................................................................................25
13.3 SMBUS ACCESS PROTOCOL .......................................................................................................................................25
13.4 MONITOR DEVICE PROTOCOL .....................................................................................................................................25
13.4.1 Read Protocol ....................................................................................................................................................25
13.4.2 Write Protocol....................................................................................................................................................25
13.5 HOT PLUG REQUIREMENTS FOR POWER SUPPLIES .......................................................................................................25
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
1 Power Supply Management Interface (PSMI) Overview
New power management features in computer systems require the system to communicate with the power supply
to access currents, voltages, fan speeds, and temperatures. Current measurements provide data to the system
for determining potential system configuration limitations and provide actual system power consumption for facility
planning. Temperature and fan monitoring allow the system to better mange fan speeds and temperatures for
optimizing system acoustics. Voltage monitoring allows the system to calculate input wattage and warning of
system voltage regulation problems. This specification defines a power supply management interface (PSMI) for
use in computer power supplies. Features to support diagnostic capabilities and management of redundant
power suppliers are also included. The communication method is SMBus to the power supply or power
distribution board. The goal is to create an industry design guideline to enable communication between power
supplies and system building blocks.
Below is a summary list of potential PSMI features. Depending upon the power supply requirements, different
features may be implemented.
PSMI Capabilities
• This is a summary of PSMI features supported by the power supply. These registers are present in all
PSMI power supplies allowing the system to quickly determine the power supplies PSMI capabilities.
Thermal management
• Ambient temperature sensor(s)
• Control temperature sensor(s) (Example: heat sink temperature in power supply)
• Fan speed sensor(s)
• System control of power supply fan(s)
• Power supply fan control override indicator
Power monitoring
• Output voltages
• Output currents
• AC Input current
• AC input voltage
Diagnostics
• Shutdown events; general failure, over current, over temperature, and loss of AC input
• Warning events; high power, high current, high temperature, slowing fan
Status
•
•
•
•
•
Fan control override mode
Signals; PWOK, PSON
Input voltage range indicator
Interrupt
Redundancy
Control
• Fan control mode; system or power supply
• Failure and Warning LED indication
Power Supply Capability records
• Reporting of power supply capabilities; currents, voltages, wattages, temperatures, and fan speed
• Header; PSMI designator, PSMI Design Guide revision level, Code revision level, PSMI device vendor
specific data
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Revision 2.12
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
2 Register Data
The registers described in this design guide are all 16-bits wide. Registers providing sensor data must ensure that
the data supplied is derived from a single analog to digital conversion and not skewed so as the MSB and the
LSB come from two different conversions or events. If the a-d conversion has an accuracy of less than 16-bits,
say 8 or 10 bits, the value must be stored at the correct scaling in the required 16-bit format.
Signed 2-byte data is returned in 2’s compliment format. The data is returned in Little Endian format – LSB sent
first, followed by MSB. Power supplies with multiple sensors that may be accessed in one bus operation return
the LSB followed by the MSB for the first sensor, LSB followed by the MSB for the second sensor, and so on. The
specific order will be explicitly specified in the command description.
Note: all registers not specified are reserved. If these registers are implemented in the PSMI device they must be
read only and if read must return zero when read.
3 PSMI Capabilities
The supported PSMI features can be quickly determined by reading the configuration registers. The following
registers define supported sensors, events, controls, and records. Registers 06h – 0Dh are required in all PSMI
support devices.
Name
Thermal sensor configuration
Register
Bit(s)
06h
Access
Description
RO
Bits containing a numerical value to indicate the number of each
type of sensor or control registers supported by the power supply.
A value of 0 means the sensor is not supported.
Temperature sensor
quantity
T1, T2, T3, T4
0, 1, 2
Number of temperature sensors. Maximum of 4 for
each PSMI device.
Fan sensor quantity
F1sense, F2sense,
F3sense, F4sense
3–5
Fan RPM sensors. Maximum of 4 for each PSMI
device. There shall be individual sensors for each fan
in the power supply. Values of 4 through 7 are
reserved and must not be returned.
Fan control registers. Maximum of 4. F1cont must
map to F1sense and so on if there is an equal number
of control register to sense registers. Values of 4
through 7 are reserved and must not be retuned.
Fan control quantity
F1cont, F2cont, F3cont,
F4cont
6–8
More than one fan may share a single control register;
in this case refer to the fan sensor assignment register
for determining which sensors are affected by the
control registers.
0 = all temperatures are affected by any Fncont control register
Fan Temperature
associations
9
1 = refer to the temperature association fields to determine which
temperature sensors are effected by each RPM control register
0 = F1cont control affects all fans
Fan control associations
A
Reserved
1 = refer to the fan association fields to determine which fan
sensors are effected by each RPM control register
B-F
Must be set to zero
T1
0–3
T2
4–7
Describes the location of each of the four temperature sensors.
0000 = Internal (attached to heat sink or other hot spot)
0001 = Inlet air temperature
0010 = Outlet air temperature
Temperature sensor types
07h
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Power Supply Monitoring Interface (PSMI)
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T3
8–B
T4
C-F
Temperature sensor offsets
T1offset
08h
T2offset
09h
T3offset
0Ah
T4offset
0Bh
Temperature sensors may be offset to allow for a relative target
temperature. These registers define the offset value so absolute
temperatures can be determined.
Temperature = Tnsense + Tnoffset
These use the same 16-bit format as the temperature sensors.
Fan Speed Resolutions for
F1sense and F2sense
Defines the scaling factors for the F1sense and F2sense fan
speed monitoring registers.
0Ch
F1 Counts or RPM
(SRRCOR)
This bit, if reset (0), indicates that the H/W reports fan speed in
RPMs. In this case, field SRRCPM is not used. If set (1), this bit
indicates that the H/W reports fan speed by returning a count of
the number of clock pulses per measured revolution. In this case,
field SRRCPM provides the resolution of the clock pulses.
0
F1 Clock Pulse
Multiplier
(SRRCPM)
Clock Pulse Multiplier. These bits indicate the resolution of the
clock oscillator, as a multiple of 2.5Khz. For example, if a 90KHz
oscillator is used, a value of 36 (24h) would be provided. The
fan’s speed in RPMs can be calculated using formula:
1-7
RPMs = (SRRCPM * 2500 * 60) / counts.
F2 Counts or RPM
(SRRCOR)
F2 Clock Pulse
Multiplier
(SRRCPM)
Fan Speed Resolutions for
F3sense and F4sense
8
See above description for F1
9-F
See above description for F1
Defines the scaling factors for the F3sense and F4sense fan
speed monitoring registers.
0Dh
F1 Counts or RPM
(SRRCOR)
F1 Clock Pulse
Multiplier
(SRRCPM)
F2 Counts or RPM
(SRRCOR)
F2 Clock Pulse
Multiplier
(SRRCPM)
0
See above description for F1
1-7
See above description for F1
8
See above description for F1
9-F
See above description for F1
These registers are used to configure the fan control register
scaling method and define the maximum allowed fan speed.
Each fan shall have a 16-bit register defining the scaling and
maximum speed.
Fan speed control
configuration
Refer to the fan speed control registers for a description of RPM
and duty cycle scaling.
F1config
0Eh
0 = fan speed set using RPMs
1 = fan speed set using duty cycle percentage
0
Provides the fans maximum speed in RPMs;
0 RPM to 65,535 RPM counting by 2.
1-F
F2config
0Fh
0
Same as F1config
1–F
F3config
10h
0
Same as F1config
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1–F
F4config
11h
0
Same as F1config
1-F
Voltage / current sensor configuration
register
V1 through V10
12h
RO
Bits contain a numerical value indicating the number of power
supply outputs. Maximum of 10. Values 11 through 15 are
reserved and shall not be returned.
This is used to align the outputs with the voltages and physical
connections. The sensors are assumed listed in order of voltage
levels (lowest to highest positive voltages, then lowest to highest
negative voltages, and finally standby outputs).
Power supply output
quantity
The association of outputs with connectors and voltages will be
described in detail in the power supply specification.
0-3
ATX12V Example #1:
V1 = 3.3V, V2 = 5V, V3 = 12V1, V4 = 12V2, V5 = -12V, V6 =
5VSB
SSI EPS12V Example #2:
V1 = 3.3V, V2 = 5V, V3 = 12V1, V4 = 12V2, V5 = 12V3, V6 =
12V4, V7 = -12V, V8 = 5VSB
Single main 12V output Example #3:
V1 = 12V, V2 = 5VSB
Indicator that voltage sensors are supported.
V1sense, V2sense … V10sense
Voltage sensors
V1sense through
V10sense
0 = output voltage sensors not supported
4
1 = outputs have voltage sensors. The sensors shall be in the
same order as the outputs are described in the power supply
output configuration bits 0-3 above.
Bits contain a numerical value indicating the number of output
current sensors supported. Maximum of 10. Values 11 through
15 are reserved and shall not be returned.
Iout1, Iout2 … Iout10
Output current sensors are associated with the power supply
outputs in the same order as described above in the power
supply output configuration; I1out ⇒ V1; I2out ⇒ V2 and so on.
There may be fewer current sensors than outputs. In this case
the later outputs are assumed to not have current sensors.
Output currents sensors
Iout1 through Iout10
ATX12V Example #1 with 4 current sensors:
Iout1 ⇒ V1 (3.3V)
Iout2 ⇒ V2 (5V)
Iout3 ⇒ V3 (12V1)
Iout4 ⇒ V4 (12V2)
V5 and V6 for -12V and 5VSB do not have current sensors.
5–8
SSI EPS12V Example #2 with 6 current sensors:
Iout1 ⇒ V1/3.3V
Iout2 ⇒ V2/5V
Iout3 ⇒ V3/12V1
Iout4 ⇒ V4/12V2
Iout5 ⇒ V5/12V3
Iout6 ⇒ V6/12V4
V7 and V8 for -12V and 5VSB do not have current sensors.
Input current sensor
9
0 = no input current sensing
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
Iin
1 = input current sensing is included in the power supply.
Maximum of one input current per power supply can be sensed.
Peak current sensors
Bit indicates if peak current sensors are implemented in the
power supply. The number and configuration of peak current
sensors shall match the output / input current sensors.
A
0 = no peak current sensors
1 = peak current sensors are implemented
0 = no input voltage sensing
Input voltage sensors
Vin
B
Reserved
1 = input voltage sensing is included in the power supply.
Maximum of one input voltage per power supply can be sensed.
C-F
Must be set to zero
This register is used only if the Fan Control Association bit is set
in the Thermal Sensor Configuration register otherwise it must
return 0x00.
This defines the association of fans to Fncont control registers in
power supplies with multiple fans controlled by a single RPMn
control register.
Fan control associations
13h
RO
Each nibble defines the fans that are affected by that Fncont
control register by assigning a bit to each fan association. A 0 in
that fan bit location means the fan is not affected by the control
register, a 1 means the fan is affected by the control register.
0 = fan not effected by Fncont
1 = fan is effected by Fncont
F1cont fans
0-3
Fan 4
bit 3
Fan 3
bit 2
Fan 2
bit 1
Fan 1
bit 0
F2cont fans
4-7
Fan 4
bit 7
Fan 3
bit 6
Fan 2
bit 5
Fan 1
bit 4
F3cont fans
8-B
Fan 4
bit B
Fan 3
bit A
Fan 2
bit 9
Fan 1
bit 8
F4cont fans
C-F
Fan 4
bit F
Fan 3
bit E
Fan 2
bit D
Fan 1
bit C
This register is used only if the Fan Temperature Association bit
is set in the Thermal Sensor Configuration register otherwise it
must return 0x0000.
This defines the association of RPMn control registers to the
temperature sensors that they affect.
Each nibble defines the temperatures that are affected by that
Fncont control register by assigning a bit to each temperature
association. A 0 in that temperature bit location means the
temperature is not affected by the control register, a 1 means the
temperature is affected by the control register.
Fan Temperature associations
0 = temperature not effected by Fncont
1 = temperature is effected by Fncont
F1cont temperatures
14h
0-7
T3
bit 2
T2
bit 1
T1
bit 0
reserved
bit 7 = 0
reserved
bit 6 = 0
reserved
bit 5
RO
9
reserved
bit 4
T4
bit 3
Power Supply Monitoring Interface (PSMI)
Revision 2.12
F2cont temperatures
F3cont temperatures
8-F
15h
F4cont temperatures
Shutdown events
0-7
8-F
16h
T3
bit A
T2
bit 9
T1
bit 8
reserved
bit 7 = 0
reserved
bit 6 = 0
reserved
bit D
T3
bit 2
T2
bit 1
T1
bit 0
reserved
bit 7 = 0
reserved
bit 6 = 0
reserved
bit 5
T3
bit A
T2
bit 9
T1
bit 8
reserved
bit 7 = 0
reserved
bit 6 = 0
reserved
bit D
RO
reserved
bit C
T4
bit B
reserved
bit 4
T4
bit 3
reserved
bit C
T4
bit B
RO
RO
RO
The following bits define what Shutdown event bits are supported
by the power supply.
0 = not supported, 1 = supported
Failure
0
General failure event bit.
Over current shutdown
1
Over current shutdown bit
Over temperature shutdown
2
Over temperature shutdown bit
AC loss
3
AC loss shutdown bit (only for redundant power supplies)
Fan1 failure
4
Fan1 failure event bit
Fan2 failure
5
Fan2 failure event bit
Fan3 failure
6
Fan3 failure event bit
Fan4 failure
7
Fan4 failure event bit
Reserved
Status
8–F
17h
Must be set to zero
RO
The following bits define what status features are supported by
the power supply.
0 = not supported, 1 = supported
F1cont override indicator
0
F2cont override indicator
1
F3cont override indicator
2
F4cont override indicator
3
PWOK
4
Support of PWOK signal monitoring bit
PSON
5
Support of PSON signal monitoring bit
Interrupt
6
Support of interrupt capability and associated bit
Redundancy
7
Support for redundancy indicator
Input range
8
Support for input range indicator
Determines if the power supply has the feature to indicate when
the power supply is overriding system control of the fans.
9-F
Control
Must return zero
The following bits define what control features are supported by
the power supply.
0 = not supported, 1 = supported
18h
F1cont control mode
0
F2cont control mode
1
F3cont control mode
2
Determines if the feature to allow system control of the power
supply fans is supported in the power supply.
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Power Supply Monitoring Interface (PSMI)
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F4cont control mode
3
LED control
4
Reserved
Support for system control of the power supply LED(s)
5-7
Must return zero
The following bits define what records are supported by the
power supply.
0 = not supported, 1 = supported
Records
Power supply capability
records
8
Support of power supply capability records.
Vendor PSMI device field
9
Support of PSMI device vendor specific field
Custom features
A
Support of custom features are implemented in the register range
of 55h to 5Fh
Reserved
B-F
Warning events
19h
Must return zero
RO
Bits containing a numerical value to indicate the number of each
type of warning bits supported. A value of 0 means the warning
event is not supported.
Control temperature warning
events
0, 1
Number of high control temperature warning bits
Ambient temperature
warning events
2, 3
Number of high ambient temperature warning bits
Fan failure warning events
4–6
Number of fan failure warning bits
Output current warning
events
7–A
Number of output current warning bits
Input voltage warning event
B
Support of input voltage out of range warning event
0 = not supported, 1 = supported
Input current warning event
C
Support of high input current warning event
0 = not supported, 1 = supported
Reserved
D-F
Must be set to zero
Register locations reserved for future PSMI design guide
expansion. Reserved space in an actual PSMI device is not
required. Must be set to zero.
1Ah –
1Fh
Reserved configuration registers
4 Header
The PSMI device in the power supply shall have a header to identify the power supply or power distribution as
PSMI and which design guide revision level it is based. There is a register to identify the code revision level.
Register
Bits
Access
Discovery Key 1
Discovery Key 2
Discovery Key 3
Discovery Key 4
Name
3Eh
LSB
MSB
LSB
MSB
RO
RO
RO
RO
PSMI Major Version
40h
LSB
RO
MSB
RO
LSB
RO
Major version of code in the power supply PSMI device
MSB
RO
Minor version of code in the power supply PSMI device
RO
Reserved space for the Internet IANA Enterprise ID. This is used
to identify the power supply manufacturer. The least significant
numbers of the ID shall start in the LSB of register 42h.
3Fh
PSMI Minor Version
Power supply code major
version
Power supply code minor
version
Supplier ID
41h
42h – 43h
Description
Value to use to validate device as PSMI. Value = ‘P’ (50h)
Value to use to validate device as PSMI. Value = ‘S’ (53h)
Value to use to validate device as PSMI. Value = ‘M’ (4Dh)
Value to use to validate device as PSMI. Value = ‘I’ (49h)
Major version of PSMI specification that this power supply is
compliant.
Minor version of PSMI specification that this power supply is
compliant.
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Name
Register
Reserved
Bits
Access
Description
44h – 52h
Must return zero
5 Sensor Data
5.1
Sampling
Sensor data must be periodically updated to the full accuracy of the sensor. The maximum time between data
refresh for temperature, voltage, and current sensor values is 250ms. The maximum time between data refresh
for fan sensor values is 1 second. Proper analog filters shall be used on the input of voltage and current sensor
a-d converters to prevent aliasing. Even though the sensor registers are 16-bit the minimum analog to digital
conversion resolution is 8-bits. The minimum resolutions defined for each sensor assumes 8-bit analog to digital
conversion.
5.2
Temperature sensors
There is space reserved for up to four temperature sensors. As stated in the PSMI Capability section; the
sensors may be configured to measure inlet/outlet air temperature or internal hot spot temperature.
Temperature offset values (Tnoffset) are defined for each sensor in the section 3, PSMI Capabilities.
Temperature offsets are used to convert a relative temperature value in the temperature sensor registers to the
actual temperature. The actual temperature is calculated by; temperature = Tn + Tnoffset.
Target temperatures (Tntarget) are defined for each sensor in section 10; Power Supply Capability records.
Target temperatures are used by the system to determine proper airflow conditions for the power supply. The
system does this by using the difference between the target temperature and the actual temperature to determine
fan speeds; temperature difference = Tntarget – (Tn + Tnoffset)
Temperature sensor maybe categorized as absolute or relative sensors.
• Absolute temperature sensors are used by the system to determine the power supply’s inlet air
temperature. These sensors return an absolute temperature value. Tnoffset is set to zero for absolute
sensors.
• Relative temperature sensors are used by the system to control airflow to the power supply. These
sense an internal hot spot in the power supply. The system adjusts airflow to keep these sensor values
at or near 0ºC. Tntarget is set to zero for relative temperature sesnors.
Temperature sensor data format reports temperatures in the range of +/-512° C from the desired maximum
temperature. The temperature sensor data is returned as a 2’s complement 16-bit binary value. It represents the
number of 1/64º C increments in the actual reading. See the following figure:
MSB
Upper nibble
S
Sign
x
x
MSB
Lower nibble
x
x
x
x
LSB
Upper nibble
x
x
x
Integer Value (~0-511)
x
LSB
Lower nibble
x
x
x
x
Fractional Value (1/64C)
12
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
Table 1 Temperature Sensor Value Examples
Temperature
2’s compliment representation
80 ºC
0010 0100 0000 0000
79.875 ºC
0001 0011 1111 1000
1 ºC
0000 0000 0100 0000
0 ºC
0000 0000 0000 0000
-1 ºC
1111 1111 1100 0000
-5 ºC
1111 1110 1100 0000
Although a 16-bit value is always returned, it does not imply a 16-bit A to D converter is needed. A lower
resolution converter may be appropriately mapped onto the 16-bit return value. The only restriction is that any
unused bits be set so as to be interpreted in a manner that will not affect the reading. For example if an 8-bit
unsigned A to D converter that resolves temperature in 0.25C increments is used, the 8-bit output of the converter
will be mapped onto the middle two nibbles with the upper and lower nibble of the 16-bit value set to 0.
5.2.1
Absolute and relative temperature sensors
Absolute Temperature Sensor Requirements (Toffset = 0ºC) for inlet and outlet air temp sensors
Max number of sensors
3
Range
-10 ºC to +70ºC
Resolution
1 ºC
Error
+/-3 ºC
Relative Temperature Sensor Requirements (Ttarget = 0ºC) for internal temperature sensors
Max number of sensors
3
Range
-20 to +15 ºC from control temperature
Resolution
0.25 ºC
Error
+/-1 ºC over -20 ºC /+15 ºC with respect to target
Name
Register
Bit(s)
Temperature Sensors
5.3
Description
RO
T1
00h
0-F
T2
01h
0-F
T3
02h
0-F
T4
03h
0-F
04h , 05h
0-F
reserved
Access
Temperature sensor registers used to measure absolute and/or
relative temperatures.
Fan speed sensors
There are four sensors reserved for monitoring fans inside the power supply. These registers are read only.
These registers are used to ascertain the current speed of the fans. Updated current speed readings need to be
made available at a minimum rate of 1Hz. This register must always return an valid fan tachometer
measurement, even when a fan is disabled, non-functional or not present.
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Power Supply Monitoring Interface (PSMI)
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Name
Register
Bit(s)
Fan Speed Sensors
5.4
Access
Description
RO
F1sense
20h
0-F
F2sense
21h
0-F
F3sense
22h
0-F
F4sense
23h
0-F
How the value obtained from these registers is used to obtain a
fan speed, measured in RPMs, is detailed in the description of
register FSSFSR (Fan Speed Resolution Register; above in
section 3).
When speed is being reported in Counts, special return value
0FFFFh will be used to indicate that the fan is not spinning (has
stalled or been stopped) or that the tachometer input is not
connected to a valid signal. When speed is reported in RPMs,
value 0 will be used to indicate that the fan is not spinning (has
stalled or been stopped) or that the tachometer input is not
connected to a valid signal.
Fan Speed Controls
There are four control registers reserved for setting the desired fan speed. These registers may be controlled by
the power supply or the system. The mode or operation is set by the fan speed control bits located in the Control
Register (see section 8). When the power supply fan is controlled by the system, the power supply may override
the system fan control if the power supply gets too hot. This override condition is indicated by the fan override
bits located in the Status Register (see section 8). The fan speed control registers are read/write. If the power
supply is overriding a system fan speed request, the control register value will return the actual fan speed set by
the power supply rather than the fan speed provided by the system. The configuration of the register value to
control the fan speed is set in the Power Supply Capability Records (section 10).
Maximum number of fan speed sensors:
Duty cycle fan speed range:
RPM fan speed range:
Resolution:
Register size:
Name
Register
4
0 to 255 (0 = 0% duty cycle; 255 = 100% duty cycle)
0 to 65,535RPM
1/255 of the fans maximum speed
16-bits
Bits
Fan speed control
Access
Description
RW
F1cont
24h
0-F
F2cont
25h
0–F
F3cont
26h
0–F
F4cont
27h
0–F
Fan speed control registers; one for each fan inside the power
supply. These are used by the power supply or system to set fan
speeds. Control source is selected by bits in the status register.
Register locations used by the power supply need only be present.
5.5
Input and Output voltages
Voltages shall be monitored with 16-bits reserved for each sensor. These registers are read only.
The data format is different for output voltage and input voltage registers; +/-128V for output voltages and +/-512V
for input voltage. The voltage sensor data is returned as a 16-bit 2’s complement binary value. This represents
the number of 1/256 volts in the actual output reading and the number of 1/32 volts in the actual input reading.
AC RMS values will always be returned as a positive value.
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
The following figure illustrates the bit mappings for +/-128V output voltage.
MSB
Upper nibble
x
x
x
MSB
Lower nibble
x
x
Sign
x
LSB
Upper nibble
x
x
x
x
Integer Value (~127V)
x
LSB
Lower nibble
x
x
x
x
x
Fractional Value (1/256V)
Table 2 Output Voltage Sensor Examples
Voltage
-48VDC
12VDC
-12VDC
3.3VDC
2’s compliment representation
1101 0000 0000 0000
0000 1100 0000 0000
1111 0100 0000 0000
0000 0011 0100 1101
The following figure illustrates the bit mappings for +/-512V input voltage.
MSB
Upper nibble
x
x
x
MSB
Lower nibble
x
Sign
x
x
x
LSB
Upper nibble
x
x
x
x
LSB
Lower nibble
x
Integer Value (~511V)
x
x
x
x
Fractional Value (1/32V)
Table 3 Input Voltage Sensor Examples
Voltage
120 VAC
230 VAC
2’s compliment representation
0000 1111 0000 0000
0001 1100 1100 0000
Voltage sensors must resolve up to 133% of the rated voltages they are sensing.
For example, an 8-bit A to D designed to measure a 12 volt output might be mapped as follows with the upper
nibble of the A to D mapped to the lower nibble of the sensors MSB etc.:
A to D
Upper nibble
x
MSB
Upper nibble
x
Sign
x
x
x
x
Lower nibble
x
x
MSB
Lower nibble
x
x
x
x
x
x
x
LSB
Upper nibble
x
x
Integer Value (~127V)
x
x
LSB
Lower nibble
x
x
x
Fractional Value (1/256V)
15
x
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
Maximum output voltage sensors:
Output voltage range:
Minimum Resolution:
Register size:
Error:
10
0V to 133% of rated voltage
Rated voltage / 190
16-bits
+/-2% rated voltage
Maximum input voltage sensors:
1
Input voltage range:
0V to 133% of rated voltage*
Minimum Resolution:
Max rated voltage / 190
Register size:
16-bits
Error:
+/-5% rated voltage
* This can be a DC voltage input (example: -48VDC for telecommunication systems) or an AC voltage (example:
115volts RMS).
Name
Registers
Bit(s)
Voltage sensors
Access
Description
RO
Output voltage sensors mapped to the power supply
outputs as described in the configuration field.
Vsense1 – Vsense10
28h – 31h
Register locations used by the power supply need only
be present.
Vin
5.6
32h
Input voltage sensor register
Input and Output currents
Current sensors measure the average output currents of the power supply. Not all outputs require a current
sensor. The association of sensors to outputs is described in the Configuration table.
5.6.1
Current sensor sampling
For the sensor to measure average output currents each current sensor signal is filtered with a fixed bandwidth
defined in the capability records. There is a common bandwidth defined for all output current sensors.
Average currents are important to the system for sizing system power consumption and facility capabilities. Since
the system current may change quickly, filtering is needed to guarantee only average (or continuous) current data
is measured.
5.6.2
Current Sensors
Currents shall be monitored with 16-bits reserved for each sensor. These registers are read only.
The data format used to report current values in the range of 0A to 1024A to be reported. The current sensor data
is returned as a 16-bit binary value. It represents the number of 1/64 amps in the actual reading.
Maximum output current sensors:
Maximum input current sensors:
Current range:
Resolution:
Register size:
Error:
10
1
0A to 1024A*
1/190 of rated output/input current*
16-bits
+/-5% of rated current
* This can be DC input or output currents (example: telecommunication systems or power supply outputs) or AC
input current (amps RMS).
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
5.6.3
Peak Current Sensors
The current sensors shall have additional 16-bit registers to store the peak average sensed value from the current
sensor registers. These registers are updated with the value in its associated current sensor register every time
the current sensor register value is greater than the value stored in the peak current sensor register. Therefore,
the value in the peak current sensor registers is averaged in the same method as the current sensor register.
Since the system loading conditions may change faster than the system can poll the registers, the peak current
sensors capture data that may otherwise be missed. These sensor registers shall be Read and Write to reset.
The number, range, resolution, register size, and error shall be the same as the current sensor registers.
5.6.4
Peak Current Sensor Reset
The peak current sensors shall be reset to 00h when PSON is asserted during a power cycle. The peak current
sensors shall hold their value during a loss of AC input power for as long as the standby output is present. A
write of any value to the peak current sensor shall reset the value to 00h.
Name
Registers
Bit(s)
Access
Description
RO
Sensors for measuring the power supply average
output currents. The configuration fields describe how
these sensors are associated with the actual power
supply outputs. The averaging bandwidth is recorded
in the capability records.
Current sensors
I1out – I10out
Iin
33h – 3Ch
0-F
3Dh
0-F
53 – 5Ch
0-F
5Dh
0-F
Peak output current sensors
I1out_peak – I10out_peak
Iin peak
RWR
Sensors recording the peak average output current
captured in each output current sensor.
6 Shutdown Events
The shutdown event register is used by the system to diagnose power related system failures when the system
has shutdown. This may be used by redundant or non-redundant power systems.
6.1
Shutdown Event Reset
The shutdown event register shall be reset to 00h when PSON is asserted during a power cycle. The shutdown
event register shall hold their value during a loss of AC input power for as long as the standby output is present.
A write of 1b to any bit location shall reset the value to 0b.
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
Name
Shutdown Event Register
Registers
Bit(s)
5Eh
Failure
Access
RWR
Description
1 = asserted, 0 = de-asserted
Asserts for any general failure of the power supply that
causes a shutdown. These include over current, over
temperature, fan failure, device failure, over voltage,
and under voltage.
0
Asserts if an over current condition on any output
causes the power supply to shutdown.
Over current
1
The power supply’s standby power shall still be
available to provide power to the PSMI device in this
condition.
Asserts if any over temperature condition causes the
power supply to shutdown.
Over temperature
2
AC loss
3
Fan1 Failure
4
Fan2 Failure
5
Fan3 Failure
6
Fan4 Failure
7
Not used
The power supply’s standby power shall still be
available to provide power to the PSMI device in this
condition.
Asserts when the power supply has shutdown due to
loss of the AC input. Only for redundant powered
systems that still have power from a second source.
This shall not assert for momentary losses of AC power
that do not cause an interruption of power supply
outputs.
Asserts to 1b when a fan failure causes the power
supply to shutdown.
The power supply’s standby power shall still be
available to provide power to the PSMI device in this
condition.
8-F
Reserved and must be returned as zero
7 Warning Events
The warning event registers are used by the system to check for conditions in the power supply that are at the
power supply’s capability levels set in the capability records. The warning event register bits are latched to their
asserted stated once an event occurs. These sensor registers shall be Read and Write to reset
7.1
Warning Event Reset
The warning event registers shall be reset to 00h when PSON is asserted during a power cycle. The registers
shall hold their value during a loss of AC input power for as long as the standby output is present. A write of 1b to
any bit location shall reset the value to 0b.
Name
Thermal Warning Event Register
Registers
Bit(s)
5Fh
Access
RWR
T1warning
0
T2 warning
1
T3 warning
2
T4 warning
3
Description
1 = asserted, 0 = de-asserted
Asserts when T1cont temperature is exceeding the
maximum value as recorded in the capability records.
Asserts when T1amb temperature is exceeding the
maximum value as recorded in the capability records.
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
F1 warning
4
F2 warning
5
F3 warning
6
F4 warning
7
Not used
Output current warning event register
These bits assert to indicate a predictive fan failure
condition. This is determined by comparing the
specified RPM versus the fans operating voltage or
PWM signal.
8-F
60h
RWR
Iout1 – Iout10
0-9
Not used
A-F
Input warning events
61h
Input Over Current
Warning
Must be set to zero
Associated bits will be asserted when the measured
output current exceeds the value in the associated
capability record.
Must be set to zero
RWR
Associated bits will be asserted when the measured
output current exceeds the value in the associated
capability record.
0
Not used
1, 2
Input under voltage
warning
Must be set to zero
Based on primary minimum input voltage limit in
capability record
3
Not used
4-F
Must be set to zero
8 Status
The status register contains bits to monitor fan control modes, signals, operating range, and LED control.
8.1
Status Register Reset
The status register shall be reset to 00h when PSON is asserted during a power cycle. The register shall hold its
value during a loss of AC input power for as long as the standby output is present.
Name
Bit(s)
Access
Description
RPM1 override
0
RO
RPM2 override
1
RO
RPM3 override
2
RO
Asserts when power supply overrides RPM1 control by
increasing the RPM1 value. The power supply shall
increase the RPM1 value when it requires a higher
RPM to properly cool the power supply.
RPM4 override
3
RO
1 = RPM control override
0 = no override on RPM control
PWOK
4
RO
Asserts when the PWOK signal is asserted.
1 = asserted, 0 = de-asserted
PSON
5
RO
Asserts when the PSON signal is asserted.
1 = asserted, 0 = de-asserted
Interrupt
6
RWR
Asserts when an interrupt is sent to the system. This
bit shall latch once an event has occurred. It shall
reset to 0b with a power cycle or writing 1b to the bit.
1 = asserted, 0 = de-asserted
7, 8
RO
Used by the system to determine output power, output
current, input voltage, and input current capability
limits. This is used to define capability limits at
different AC input voltage levels; example: 100VAC,
Status registers
Power supply operating
range
Registers
62h
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
115VAC, and 200VAC where the power supply may
have different output power and current capabilities.
The input voltage ranges are defined in the power
supply capability records.
00 = First operating range
01 = Second operating range
10 = Third operating range
Redundancy
9
RO
Used to indicate that the system is operating in a nonredundant power condition. This is reserved for
redundant power sub-systems on the power distribution
board.
0 = redundant power OK
1 = loss of redundant power
Reserved
A-F
Must return zero
9 Control
This register is used to allow the system to set the fan speed control method and LED status.
Name
Bit(s)
Access
Description
RPM1 control mode
0
RW
RPM2 control mode
1
RW
RPM3 control mode
2
RW
RPM4 control mode
3
RW
The control of the power supply fan(s) can be set to
two different modes of speed control. Power supply
control allows only the power supply to vary the speed
of the fan(s) in the power supply. System control
allows the system to control the power supply fan(s) via
the fan control registers (RPMn). However if the
commanded speed is lower than that required by the
power supply it may run the fan at the higher speed it
needs.
Control register
Registers
63h
1 = system control, 0 = power supply control
Used to allow the system to assert a Shutdown or
warning indication on the power supply LEDs. At
power on these bits default to 0b.
LED Control
Shutdown LED Status
4
RW
0 = LED controlled by power supply
1 = Shutdown LED status
Warning LED Status
5
RW
0 = LED controlled by power supply
1 = Warning LED status
Shutdown Event mask
6
RW
0 = shutdown events do not cause an interrupt
1 = shutdown events will cause an interrupt
Default = 1
Warning Event mask
7
RW
0 = warning events do not cause an interrupt
1 = warning events will cause an interrupt
Default = 1
Mask Bits
Reserved
8-F
20
Must return zero
Power Supply Monitoring Interface (PSMI)
Revision 2.12
10 Power Supply Capability records
The power supplies capability limits are defined in these registers. The data is formatted into 16-bit registers.
These registers are required only for power supplies indicating support of capability records in the configuration
fields.
The format of values in the capability records is the same as their associated sensors.
Name
Register
Bit(s)
Access
Description
Maximum Temperatures
T1target
64h
RO
T2target
65h
RO
T3target
66h
RO
T4target
67h
RO
Maximum temperature allowed at temperature sensor for the
power supply to meet its reliability and performance
requirements. This defines the target temperature for
determining the proper fan speed(s) to cool the power supply.
This temperature must be lower than the power supply over
temperature shutdown limit.
These registers are used to define the minimum fan speed
allowed by each fan in the power supply. Each fan may have a
16-bit register defining the scaling and minimum speed.
Fan operating minimums
Refer to the fan speed control registers for a description of RPM
scaling.
F1min
68h
RO
Provides the fans minimum speed in RPMs;
0 RPM to 65,535 RPM
F2min
69h
RO
Same as F1min
F3min
6Ah
RO
Same as F1min
F4min
6Bh
RO
Same as F1min
Sound power capability
6Ch
Max fan speed sound power
0-7
RO
Min fan speed sound power
8-F
RO
Sound power range of power supply with fans running at
minimum and maximum speeds.
The sound power units will be defined in a future revision.
Output voltage limits
Vout1 maximum
6Dh
RO
Vout1 minimum
6Eh
RO
6Fh –
80h
RO
Vout2 – Vout10 limits
Maximum and minimum voltage allowed on the Voutn voltage as
specified by the power supply. The maximum value is less than
the over voltage shutdown limit. The minimum value is greater
than the under voltage shutdown limit.
Output current capability
First output currents
81h –
8Ah
RO
Second output current
capability
8Bh –
94h
RO
Third output current
capability
95h –
9Eh
RO
Input current maximum limits
First Input current limit
9Fh
RO
Second input current limit
A0h
RO
21
Maximum output current capability of the power supply. These
are set to the power supplies rated output currents. All outputs
shall have an associated maximum currant capability defined.
Three ranges are defined for power supplies with varying output
capability at different input voltages. These ranges must
correlate with the minimum input voltages defined later in this
table.
Maximum input current capability of the power supply. These are
set to the power supplies rated input currents. Three ranges are
defined for power supplies with varying output capability at
different input voltages. These ranges must correlate with the
Power Supply Monitoring Interface (PSMI)
Revision 2.12
Third input current limit
A1h
RO
First input voltage limit
A2h
RO
Second input voltage limit
A3h
RO
Third input voltage limit
A4h
RO
minimum input voltages defined later in this table.
Minimum input voltage limits
Total output power maximum limits
First output power limit
A5h
RO
Second output power limit
A6h
RO
Third output power limit
A7h
RO
Combined output power
limit 1
A8h
RO
Minimum input voltage capability of the power supply. These are
set to the power supplies rated input voltage. Three ranges are
defined for power supplies with varying output capability at
different input voltages.
Defines the maximum output power capability of the power
supply. Capability of setting three different levels is reserved for
power supplies with different output power capabilities at different
input voltages. These ranges must correlate with the minimum
input voltages defined later in this table.
The data format used to report wattage values in the range of 0W
to 65,536W to be reported. The wattage data is returned as a
16-bit binary value with each 1 bit increment representing 1W.
Combined power capability of two outputs when the power supply
is operating in the first range. Allows for 3.3V/5V combined
power definitions.
Format will be the same as the above total output power
capability with a range of 0W to 65,536W.
Each of the four nibbles in the 16-bit register define an output
included in the combined output power calculation. 0h is used as
a filler if less than four outputs are used in the combined power
calculation.
Combined outputs for power
limit 1
A9h
RO
Example #1: 002Ah defines a combined power limit for outputs
V2 and V10.
Example #2: 3456h defines a combined power limit for outputs
V3, V4, V5, and V6.
Combined output power
limit 2
AAh
RO
Combined outputs for power
limit 2
ABh
RO
Output bandwidth
ACh
RO
Input bandwidth
ADh
RO
Power supply efficiency curve for high
line operation
RO
Light load output power
AEh
Mid-load output power
AFh
Max load output power
B0h
Light load efficiency
B1h
Mid-load efficiency
Power supply efficiency curve for low
line operation
See definition from combined output for power limit 1 above.
Defines the bandwidth for output current sensors and input
current sensor measurements. All output current sensor have
the same bandwidth.
Current sensor bandwidths
Max load efficiency
See definition from combined output power limit 1 above.
These register define a piecewise linear model of the power
supply’s efficiency as a function of load. Two curves are defined
for different input voltages; low line and high line.
The piecewise linear model is made up of three points defined at
light load, mid-load, and max load.
The output power data is in the same format as the above total
output power registers.
0-7
The efficiency data is returned as an 8-bit binary value with each
1 bit increment representing 1/(256%).
8-F
B2h
The data format used to report bandwidth values in the range of
0Hz to 6,553,6Hz to be reported. The bandwidth data is
returned as a 16-bit binary value with each 1 bit increment
representing 0.1Hz.
0-7
RO
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
Light load output power
B3h
Mid-load output power
B4h
Max load output power
B5h
Light load efficiency
B6h
Mid-load efficiency
Max load efficiency
0-7
8-F
B7h
0-7
Load share error
RO
Output share error for V1
B8h
Output share error for V2
B9h
Output share error for V3
BAh
Output share error for V4
BBh
Redundancy Configuration
This defines load share error for redundant load sharing power
supplies with up to 4 load shared outputs. These are listed in the
same order as the output voltage and output current sensors.
The load share error data is returned as an 8-bit binary value with
each 1 bit increment representing 0.1A. The range is 0A to
25.5A with a 0.1A resolution.
BCh
RO
Redundant power sub-systems may have different number of
power supplies in the system. This register defines the total
number of power supplies that may be installed in the system and
the minimum number of power supplies needed to support a full
system configuration. This register is used only on power
distribution boards.
Max power supply quantity
0–7
Numerical value containing the maximum number of power
supply that can be installed in the system. This is only used in
the power distribution PSMI device.
Min power supply quantity
8–F
Numerical value containing the miniumum number of power
supplies that are required to be installed to operate a fully
configured system. This is used only by the power distribution
PSMI device.
Not used
BDh BFh
Must be set to zero
Not used
E0h FFh
Must be set to zero
11 Custom registers
The following Space has been reserved for custom features and PSMI vendor device data.
Name
Register
Bit(s)
Access
Description
Vendor specific registers
C0h –
CFh
Reserved space for device specific information
Custom feature area
D0h DFh
Reserved space for custom features
12 Redundant power
Redundantly powered systems have hardware to distribute power from the multiple hot swap redundant power
supplies to the system. This power distribution hardware may provide power converters, current limit circuits, fan
power, fan control, and temperature sensors. To support the power monitoring features, the same PSMI features
in the power supplies may be used for the power distribution hardware.
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
13 SMBus Communication
The device in the power supply shall be compatible with both SMBus 2.0 ‘high power’ specification for I2C Vdd
based power and drive (for Vdd = 3.3V). This bus shall operate at 3.3V but be tolerant of 5V signaling.
One pin is the Serial Clock [SCL] (PSM Clock). The second pin is used for Serial Data [SDA] (PSM Data). Both
pins are bi-directional, open drain signals, and are used to form a serial bus. For redundant power supplies: The
device(s) in the power supply shall be located at an address(s) determined by address pins A0 and A1. The
circuits inside the power supply shall derive their power from the standby output. For redundant power supplies
the device(s) shall be powered from the system side of the or’ing device. No pull-up resistors shall be on SCL or
SDA inside the power supply. These pull-up resistors are provided by the system and may be connected to 3.3V
or 5V. For the system design, the pull-ups should be located external to the power supply and derive their power
from the standby rail.
Clock Stretching Limit: It is highly recommended that device in the power supply operate at the full 100 kbps
SMBus speed without using clock stretching to slow down the bus. If clock stretching is required, the device in the
power supply is limited to 1ms of total clock stretching for the entire SMBus transaction (from START to STOP).
Devices that do clock stretching are not allowed to clock stretch once they have detected that they are not the
device being addressed. I.e. the device must not clock stretch once it has detected that the slave address on the
bus does not match its slave address.
Clock Low Timeout: It is recommended that the device implement the SMBus clock-low timeout (Ttimeout). This
capability requires the device to abort any transaction and drop off the bus if it detects the clock being held low for
>25ms, and be able to respond to new transactions 10ms later.
Additional design requirements: The device must recognize SMBus START and STOP conditions on ANY clock
interval. (These are requirements of the SMBus specifications, but are often missed in first-time hardware
designs.) The device must not hang due to 'runt clocks', 'runt data', or other out-of-spec bus timing. This is
defined as signals, logic-level glitches, setup, or hold times that are shorter than the minimums specified by the
SMBus specification. The device is not required to operate normally, but must return to normal operation once 'in
spec' clock and data timing is again received. Note if the device 'misses' a clock from the master due to noise or
other bus errors, the device must continue to accept 'in spec' clocks and re-synch with the master on the next
START or STOP condition.
Additional SMBus hardware requirements:
• 300ns maximum fall time with a 400pF capacitive load and 2.7Kohm pull up to 3.3V
• 10ns minimum fall time with a 20pF capacitive load and 2.7Kohm pull up to 3.3V
• SMBus shall tri-state before removal of a power supply
• The power supply shall not load the SMBus if it has no input power
13.1 Device Address Locations
The power supply device address locations are shown below. For redundant systems there are two signals to set
the address location of the power supply once it is installed in the system; A0 ad A1. For non-redundant systems
the power supply device address locations should align with the A0/A1 location of 0/0.
PDB addressing A0/A1
0/0
0/1
Power supply IPMI FRU device
A0h
A2h
Power supply PSMI device
B0h
B2h
Note: Non-redundant power supplies will use the 0/0 address locations.
1/0
A4h
B4h
1/1
A6h
B6h
For redundant power systems there will be a power distribution board (PDB). In this case there may need to be a
FRU device and PSMI device on the PDB. If the PDB is passive then the FRU and PSMI device on the PDB may
not be needed. Below are the PDB device address locations:
PDB IPMI FRU device: ACh
PDB PSMI address:
4Ah
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Power Supply Monitoring Interface (PSMI)
Revision 2.12
13.2 SMBAlert#
This sideband signal indicates that the power supply is experiencing a problem that the system agent should
investigate. This is a logical OR of the Shutdown events and Warning events.
Table 4: SMBAlert# Signal Characteristics
Open collector / drain output from power
supply. Pull-up to 5VSB or 3.3VSB located
external from the power supply.
OK
Power Alert to system
Signal Type (Active Low)
Alert# = High
Alert# = Low
Logic level low voltage, Isink=4 mA
Logic level high voltage, Isink=50 μA
Sink current, Alert# = low
Sink current, Alert# = high
Alert# rise and fall time
MIN
MAX
0V
0.4 V
5.25 V
4 mA
50 μA
100 μs
13.3 SMBus Access Protocol
This section describes the SMBus access protocols for the PSMI device. In the figures below, the fields have the
following meanings:
S
SMBus Start Condition
P
SMBus Stop Condition
W
Write indication
R
Read Indication
A
Acknowledge
13.4 Monitor Device Protocol
The SMBus Packet Error Checking (PEC) mechanism may optionally be supported by PSMI devices.
13.4.1 Read Protocol
The read protocol used is the SMBus 2.0 Read Byte/Word protocol. All reads are 16 bit words, byte reads are not
supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI device.
S
Slave
Addr
W
A
Register
Number
A
S
Slave
Addr
R
A
Low Order
Data Byte
A
High Order
Data Byte
A
P
13.4.2 Write Protocol
The write protocol used is the SMBus 2.0 Write Byte/Word protocol. All writes are 16 bit words, byte reads are not
supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI device.
S
Slave
Addr
W
A
Register
Number
A
Low Order
Data Byte
A
High
Order
Data Byte
A
P
13.5 Hot Plug Requirements for power supplies
Since redundant power supplies will be asynchronously installed and power on in a system, the devices on the
supply need to be tolerant of joining the SMBus in the middle of a transaction and ignore bus activity after being
powered on until a valid start of transaction is seen.
25