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A CMOS 5 nV= Hz 74-dB-Gain-Range 82-dB-DR
Multistandard Baseband Chain for Bluetooth, UMTS,
and WLAN
Stefano D’Amico, Andrea Baschirotto, Senior Member, IEEE, Marcello De Matteis, Nicola Ghittori,
Andrea Vigna, and Piero Malcovati, Senior Member, IEEE
Abstract—An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in
a 0.13 m CMOS occupying 1.65 mm2 is presented. The circuit
consits of an open-loop programmable-gain amplifier (PGA1),
an Activelow-pass filter (LPF), and a closed-loop
programmable-gain amplifier (PGA2). The chain gain can be
68 dB, while the input-referred
programmed in the range 6
noise (IRN) is 5 nV
Hz. A dynamic range (DR) larger than 82
dB is achieved for a 1% total harmonic distortion (THD). The
current consumption is minimized and adjusted for the different
operation conditions, down to 11 mA for the full chain.
Index Terms—Analog circuits, receivers, reconfigurable architectures.
I. INTRODUCTION
T
HE implementation of an integrated multistandard transceiver, that is competitive with solutions based on parallel and separate devices for the different standards, must take
into account various issues. First of all, both silicon area and
static power consumption must be minimized, thus requiring the
maximum possible hardware sharing among the transceivers for
the different standards [1]–[3]. The challenges in designing the
analog baseband section of such a reconfigurable receiver are
mainly related to the significant difference in the standard specifications in terms of channel bandwidth, DC-gain ( ), noise,
resolution, and linearity. The approach here adopted is to adjust the baseband circuit performance, including the power consumption, through a digital control (8 bit register for the full
baseband chain) according to the standard in use. This solution
allows us to re-use all the circuitry, adjusting the biasing conManuscript received November 12, 2007; revised February 15, 2008. This
work was supported in part by the Italian National Program FIRB under Contract
RBNE01F582.
S. D’Amico and M. De Matteis are with the Department of Innovation Engineering, University of Salento, 73100 Lecce, Italy (e-mail: stefano.damico@unile.it; marcello.dematteis@unile.it).
A. Baschirotto was with the Department of Innovation Engineering, University of Salento, Lecce, Italy. He is now with the University of Milano-Bicocca,
Italy (e-mail: andrea.baschirotto@unimib.it).
N. Ghittori was with the Department of Electrical Engineering, University of
Pavia, Pavia, Italy. He is now with Marvell, Pavia, Italy (e-mail: nicolag@marvell.com).
A. Vigna was with the Department of Electrical Engineering, University of
Pavia, Pavia, Italy. He is now with Maxim, Milano, Italy (e-mail: av@design.
mxim.com).
P. Malcovati is with the Department of Electrical Engineering, University of
Pavia, 27100 Pavia, Italy (e-mail: piero.malcovati@unipv.it).
Digital Object Identifier 10.1109/JSSC.2008.922378
ditions of the active building blocks, and, eventually, turning
on/off some stages.
The paper is organized as follows. The baseband chain architecture and specifications are presented in Section II. Then,
Section III describes in detail the analog baseband channel. The
solution adopted for the first programmable gain amplifier of
the chain (PGA1) is explained, focusing on input-referred noise
(IRN) and frequency response characteristics. Then, we present
the fourth-order low-pass filter (LPF) used in the chain, which
is based on biquadratic cells realized with the Active
topology. The last part of Section II is dedicated to the second
programmable gain amplifier (PGA2) description, where the
programmable gain is implemented by using a typical closedloop topology, while avoiding linearity problems and frequency
response degradation. Finally, Section III is dedicated to the
measurement results of the baseband chain, in terms of frequency response for each standard, linearity performance (IIP3)
and output noise spectral density.
II. BASEBAND CHAIN ARCHITECTURE
Fig. 1 shows the overall receiver [4] architecture, based
on a fully-differential structure. The circuit includes two RF
1.2 V with
sections, one for UMTS and Bluetooth (
common-mode voltage at 0.6 V) and one for WLAN and Blue2.5 V with common-mode voltage at 1.25 V).
tooth (
These two paths are connected through a multiplexer (MUX)
at the input of two identical baseband chains (for the I and
Q components). One standard at time can be processed by
the proposed system, but the overall reconfigurable terminal
will include two instances of the system, in order to allow the
concurrent use of any combination of two standards. In the
design considered in this paper, we realized the baseband chain
using two PGAs and one LPF.
An extended system study is reported in [3]. Each standard
presents its own requirements in terms of bandwidth, DC-gain,
noise and linearity. Here the main design strategies are summarized.
The reconfigurable baseband chain requirements, have been
obtained by considering the worst conditions of operation. For
instance, for the noise performance and the maximum DC-gain
requirement, the most critical standard is UMTS, with a required
IRN of 5 nV Hz. Since this value is less than the maximum allowed for the other two standards [3], the UMTS noise requirement has been taken as specification for the overall baseband
chain.
0018-9200/$25.00 © 2008 IEEE
D’AMICO et al.: CMOS 5 nV
Hz 74-dB-GAIN-RANGE 82-dB-DR MULTISTANDARD BASEBAND CHAIN FOR BLUETOOTH, UMTS, AND WLAN
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Fig. 1. Overall receiver architecture.
TABLE I
RECONFIGURABLE BASEBAND CHAIN MAIN REQUIREMENTS
TABLE II
DC-GAIN VERSUS BITS CONFIGURATION
Fig. 2. PGA1 circuit.
A. Programmable Gain Amplifier (PGA1)
According to the noise performance, the baseband chain results over-designed for Bluetooth and WLAN operation modes.
The power consumption is not optimized in these cases. This is
the price to pay for reusing blocks in reconfigurable receivers.
Otherwise, a number of circuit and architecture design solutions
are adopted to reduce the overall power consumption. Moreover,
a large chip area saving is obtained by sharing building blocks
between the different operation modes.
Bluetooth, UMTS and WLAN require 1 MHz, 2 MHz and
10 MHz of bandwidth, respectively. The bandwidth is selected
through the LPF that presents a selectable cut-off frequency,
according to the operation mode. The following strategy has
been adopted for the DC-gain control. The LPF features a fixed
DC-gain (4 dB) because in the adopted circuit solution, the
DC-gain and the frequency control are not orthogonal. Therefore, by keeping the LPF DC-gain constant while programming
the cut-off frequency, the circuit complexity is simplified. Otherwise the overall DC-gain of the baseband chain is determined by
the two PGAs. The first PGA has wide gain steps (see Table II),
while the second PGA features small gain steps (2.5 dB), that
allow a fine gain control. Table I summarizes the baseband chain
requirements.
III. ANALOG BASEBAND CHANNEL
The proposed baseband chain, as already mentioned, consists
of two PGAs and one LPF (PGA1/LPF/PGA2, in Fig. 1). These
different blocks will be discussed in the next subsections.
The basic schematic of the PGA1 is reported in Fig. 2. A
resistively-degenerated and resistively-loaded differential stage
(whose DC-gain is fixed by the resistive ratio) is used [5]–[7].
For small input signals, the required large gain is achieved by
, which accordingly
minimizing the degeneration resistance
reduces the IRN, while the load resistance
, is maximized.
For high gain mode, the PGA1 suffers for the out-of-band
linearity. In fact, the intermodulation tone is amplified by the
PGA1, and it can lead to the saturation of the overall baseband
chain. In order to prevent this problem, the PGA1 bandwidth
, the
is reduced for high gain mode. In fact, by maximizing
and
, is pushed at lower frequency
dominant pole due to
for higher gain. As a consequence, the out-of-band tones are
partially suppressed, and the intermodulation tone is attenuated.
On the other hand, for large input signals, the required
low gain is achieved by maximizing the degeneration resistance, which also increases the linear range. An output buffer
adjusts the common-mode voltage and drives the following
low-impedance load.
The input stage follower guarantees large in-band linearity
due to its large loop-gain. This circuit consists of a – converter (input opamps,
& , and
), a resistive load ( )
and an output level shifter ( & ). This structure satisfies more efficiently the target specifications (input DC-level,
noise, bandwidth, and power consumption) than using a classic
structure. Moreover, the proposed PGA1 is able
opampto work with 0.6 V and 1.25 V input common-mode level
coming out from the RF part which is selected according to the
&
operate in source follower
operation mode. Transistor
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Fig. 5. Active
G -RC cell.
tors are connected (by means of a digital control) to synthesize
the desired
and
values.
and
values are programmed through bits b0, b1
The
and b2 which act on the switches realized with transistors M9,
M10 and M11. When these switches are on, the corresponding
resistors are connected in parallel, while, when they are off, the
corresponding resistors are disconnected. The DC-gain map as
a function of the bit configurations are reported in Table II.
The switches are placed on the symmetry axis of the resistor
array for two main reasons. Firstly, they do not add parasitic
capacitances on the input transistors sources and drains nodes,
which are the most critical for the overall PGA1 transfer function. Moreover, they are more linear due to the reduced signal
swing across them.
and
The IRN of the PGA1 depends critically on the
values and on the single-ended input stage opamp, as indicated
in the following equation:
Fig. 3. Input opamp.
(2)
Fig. 4. Gain control circuit.
configuration; the differential input voltage
is copied over the series impedance of the two nonlinear
(of
& ) and the linear degentransconductance
. The
linearity is improved by the
eration resistors
closed-loop gain. The additional opamp, shown in Fig. 3, uses
a single differential pair with active load for large bandwidth
and low noise level.
This input stage single-ended opamp allows maximizing the
follower loop-gain avoiding gain losses due to the body effect.
Indeed the PGA1 DC-gain ( ) is approximated by the following
equation:
(1)
where
is the additional opamp DC-gain, and
is the
transconductance of the input stage M1&M2.
The PGA1 gain depends on the degeneration ( ) and load
( ) resistances. In order to program the gain , these resistances have to be adjusted. Both of them have been implemented
as a resistors array (as shown in Fig. 4), and a number of resis-
5 nV Hz (this contriThe PGA1 exhibits a low
bution is dominant due to the large baseband chain gain, up
to 68 dB), a large input common-mode range (the input bias
voltage is 0.6 V for the cellular RF-front-end, while it is 1.25 V
for the WLAN RF front-end), a large bandwidth (to avoid
in-band signal attenuation) and a large gain programmability
dB
dB for WLAN, and dB 29 dB for the other
(
standards).
B. Low-Pass Filter (LPF)
The fourth-order channel LPF is realized with the cascade
biquadratic cells [8]–[13]. In Fig. 5 the
of two Activeschematic of the single biquadratic cell is presented.
The opamp has a single-pole transfer function (in the frebiquadratic cell
quency range of interest). In the Active
the opamp is used as open loop integrator, in order to synthesize
a complex pole pair. The opamp transfer function can be written
as
(3)
and
are the opamp first-pole angular frequency
where
and the DC-gain, respectively. The opamp uses a two-stage
Miller topology, as shown in Fig. 6.
The equivalent circuit of the entire cell is represented in
Fig. 7. It consists of an input stage (the input transconductance
and the load resistance), an output stage (the output transcon-
D’AMICO et al.: CMOS 5 nV
Hz 74-dB-GAIN-RANGE 82-dB-DR MULTISTANDARD BASEBAND CHAIN FOR BLUETOOTH, UMTS, AND WLAN
1537
Fig. 6. Miller opamp schematic.
Fig. 7. Equivalent circuit of the active
G -RC cell.
ductance and the load resistance), and a Miller compensation
and ).
network (resistor and capacitor
In addition the load contribution (
and
) of the other
circuits connected to the cell is shown. In Fig. 7 an adjusting
. The adjusting circuit effect
circuit [8] sets
is to change the dependence of the filter frequency response on
the MOS device parameters into a dependence on the passive
component values ( , , , ). In this way the biquadratic
cell can be reconfigured by the external digital circuitry.
The adjusting circuit forces the operational amplifier frequency response to track its time constant with the passive
components ( and ). Therefore, the biquadratic cell cut-off
frequency depends directly on the passive components values,
with
, a tuning
resistance and capacitance. Matching
circuit based on the
time constant adjusting can be used
in order to compensate the frequency response variations due
to the technological spread, temperature and aging. The Accell exhibits the following key features.
tive• Low power consumption (a key issue for portable terminals): one operational amplifier is used to synthesize a
second-order transfer function. In addition the operational
amplifier unity-gain-bandwidth, , is comparable to the
filter pole
. This reduces its power consumption with
respect to other single opamp closed-loop structures (Acor MOSFET-C), where a larger than
tiveis used, with a higher power consumption;
• High linearity: a very large linear range is achieved thanks
to the filter closed-loop structure. Fig. 8 shows the frequency response at the out-of-band signals are first fillow-pass filter at the input.
tered by the very linear
G RC
Fig. 8. Activebiquad cell frequency response at the output node and
at the opamp input node.
This gives a large out-of-band IP3, which results useful
in telecom systems where the higher amplitude of out-ofband blockers requires a large out-of-band linearity. Furinput net filtering is very
thermore, in this design, the
cell is placed after
important because the Active
the PGA1 stage, where the DC-gain can be 29 dB and
the out-of-band frequencies close maximum in-band frequency. For reference, Fig. 9 shows the UMTS input spectrum at the antenna, which is down-converted and amplified by the RF front-end, and then it is present (shifted
in frequency around DC) at the PGA1 input. Out-of band
blockers larger than 60 dB w.r.t. the signal have to be processed by baseband chain [14], [15]. Out-of band blockers
are partially smoothed by the PGA1 thanks to its pole, then
they are better suppressed by the filter.
• Frequency response accuracy: The adjusting circuit makes
the opamp frequency response dependent on the passive
component values ( and ) spread, which is the only
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 7, JULY 2008
Fig. 9. Detailed block diagram of the PGA2.
Fig. 10. UMTS signal spectrum.
spread to be compensated and this is done by the tuning
system. This makes this approach completely different
from the previous approach [16], [9], where the opamp
frequency response is taken into account “as it is” to
synthesize the desired transfer function. In this previous
approach, the filter transfer function strongly suffers from
the opamp frequency response sensitivity to technology,
component spreading, and temperature. This is not the
filters, whose frequency response
case of the Activeis completely under the tuning system control.
The cell cut-off frequency can be programmed among three
possible values, according to the selected standard:
• 1 MHz for Bluetooth;
• 2.2 MHz for UMTS;
4 dB.
• 11 MHz for WLAN with
For the lower bandwidth cases the power consumption is reduced by controlling the input stage device sizes and their current levels. For all the standards, the grounded resistors are used
to control also the common-mode voltage.
C. Programmable Gain Amplifier (PGA2)
After the PGA1 and the LPF, the quite large PGA2 input
signal amplitude requires more linearity than noise performance
[6], [7]. A closed-loop architecture is therefore used. Two gainstages are adopted as a tradeoff between the number of stages
(increasing complexity and noise) and the gain-per-stage (increasing the power consumption), as shown in the detailed block
diagram reported in Fig. 10 [17]. The opamps present, the same
structure reported in Fig. 6.
In the used structure, the signal current does not flow through
, thus avoiding
the nonlinear resistance of the switches
linearity and frequency response accuracy degradation. In fact
the switches are connected between the opamp input node,
and
resiswhere ideally there is no signal swing, and the
flows through
without
tances. So the signal current
flowing in the switches, so that the input signal bypasses the
switches. Furthermore, the finite on/off switch resistance does
and
values. This technique is
not affect the nominal
largely used at low frequency, in audio applications. Anyway,
the technology improvements allow us to adjust it in order
to work at the operation frequency of the modern telecom
receivers.
The two stages are slightly different. The first and the
second gain stage have a gain-programmability range of
dB
dB and
dB
dB , respectively, with
2.5 dB step each. The second stage also implements a first-order
15 MHz low-pass transfer function. A feed-back capacitor in
has been inserted in the second stage. The
parallel with
capacitor is adjusted according to the selected gain in order to
maintain the cut-off frequency constant with gain programmability [17].
This filtering action allows the stage to be stable also for
low gain values, i.e., when the loop-gain is high, and the phase
margin is reduced. For this reason, for gain values up to 10 dB
it is used alone, while the first stage is bypassed and turned off
(saving power). For larger gain values, the first stage is turned
on and realizes a minimum gain of 10 dB. This is because, since
it is not implementing a low-pass transfer function, it would be
unstable for low gain values. Finally, as shown in Fig. 10, re-
D’AMICO et al.: CMOS 5 nV
Hz 74-dB-GAIN-RANGE 82-dB-DR MULTISTANDARD BASEBAND CHAIN FOR BLUETOOTH, UMTS, AND WLAN
1539
Fig. 12. Programmable frequency response.
Fig. 11. Chip photograph.
sistors,
, have been included. These resistors are driven by
an analog off chip voltage, which is chosen in order to compen) in order not to affect the
sate the offset. They are large (20
noise performance. The current of each stage, equal to 2 mA, is
comparable with state-of-the-art performance [17]. A tuning circuit, compensating technology, temperature and worst-case effects adjusts the frequency response of the full baseband chain.
A 4 bit word is passed both to LPF and PGA2, guaranteeing a
cut-off frequency error lower than 5%. The tuning circuit is reported in [8].
Fig. 13. In-band and out-of-band linearity performance (UMTS setting).
IV. EXPERIMENTAL RESULTS
The baseband receiver chain has been realized in a 0.13 m
CMOS technology using only 2.5 V 0.13 m devices with
double-oxide. The chip photo is shown in Fig. 11. It is embedded in a fully reconfigurable receiver and occupies a
1.65 mm die size. The resistors and the capacitors are designed as multiple of a minimum common size, in order to have
a better matching.
The baseband chain has been successfully tested in standalone configuration in all the required operation conditions. The
frequency response for different gain levels and cut-off frequencies is shown in Fig. 12. For the Bluetooth case a filter bandwidth larger than the standard requirement is implemented. For
the system design, the WLAN gain is up to 39 dB, while for the
UMTS and Bluetooth the gain is up to 68 dB.
The reference resistance for the reported data expressed in
dBm is 50 .
The linearity performance has been evaluated in terms of
input intermodulation intercept point IIP3 for different cases.
In the UMTS case the performance is reported in Fig. 13:
in-band (tones at 700 kHz and 800 kHz) IIP3
21 dBm (for
Fig. 14. 1 dB compression point (WLAN setting).
4 dB) and out-of-band (tones at 10 MHz and 19 MHz)
41 dB).
OIP3 50.5 dBm (for
In the WLAN and Bluetooth cases, the two tones for the IIP3
test are at 3 MHz, 4 MHz and 300 kHz, 400 kHz, respectively.
Also in this case, the obtained IIP3 is 21 dBm. The in-band
linearity performance are quite close for all operation modes.
Fig. 14 shows the input 1 dB compression point equal to
4 dB).
1.3 dBm (
The noise level is dominated by the PGA1 performance,
5 nV Hz noise floor, as shown in
which exhibits an IRN
Fig. 15. For
and WLAN setting, the baseband chain
features a total harmonic distortion (THD) of 40 dB for a
4 dBm input signal, which gives a dynamic range (DR) of
82 dB.
The current consumption is optimized according to the operation condition. It goes from 11 mA (UMTS/Bluetooth mode,
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TABLE III
PERFORMANCE SUMMARY
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p
Fig. 15. Input-referred noise spectrum.
21.5 dB DC-gain) up to 22 mA (WLAN mode 39 dB DC-gain).
Table III summarizes the performance of the circuit.
V. CONCLUSION
In this paper, we presented a complete analog baseband
channel for a multistandard reconfigurable receiver supporting
UMTS, WLAN and Bluetooth. The channel consists of three
functional blocks: a programmable gain amplifier, a low-pass
filter, and a last stage again providing programmable gain. In
the UMTS mode the maximum achievable gain is 68 dB, while
in the WLAN mode it is reduced to 39 dB. Measurements
on the implemented baseband section validate the proposed
design, as the main receiver tests imposed by the standards are
fulfilled with a maximum total current consumption limited to
22 mA (WLAN mode, 38 dB DC-gain).
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Guerrieri, A. Lodi, L. Lavagno, and P. Malcovati, “Baseband analog
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[15] K. R. Rao, J. Wilson, and M. Ismail, “A CMOS RF front-end for a
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Marcello De Matteis received the degree in electronic engineering from the Politecnico di Milano,
Italy, in 2004. In 2008, he received the Ph.D. degree
in information engineering from the University of
Salento, Lecce, Italy.
He is currently with the Department of Innovation Engineering, University of Salento, Italy, as a
Postdoctoral Researcher. His research topic is the
design of low-power analog filters and amplifiers for
telecommunication receivers baseband chain.
Stefano D’Amico received the degree in electrical
engineering from the Politecnico di Bari, Italy, in
2001. In 2005, he received the Ph.D. degree from the
University of Salento, Italy.
He is currently with the Department of Innovation
Engineering, University of Salento, as an Assistant
Professor. He has authored or co-authored more
than 12 papers in international journals, more than
60 presentations at international conferences (with
published proceedings), two book chapters, and three
industrial patents. His research topics are low-power
baseband analog circuits for sensors interface and telecommunications.
Dr. D’Amico was the secretariat of the IEEE PRIME 2006 Conference. He is
associate editor for Europe of the Journal of Circuits, Systems, and Computers.
Andrea Baschirotto (M’95–SM’01) was born in
1965 in Legnago (Verona), Italy. He graduated in
electronic engineering (summa cum laude) from the
University of Pavia, Pavia, Italy, in 1989. In 1994, he
received the Ph.D. degree in electrical engineering
from the University of Pavia.
In 1994, he joined the Department of Electronics,
University of Pavia, as a Researcher (Assistant Professor). In 1998, he joined University of Lecce, Italy,
as an Associate Professor. In 2007, he joined the University of Milano-Bicocca, Italy, as an Associate Professor. About his research activity, he founded and he is leading the Microelectronics Group at University of Lecce, which is collaborating with several
companies and research institutions (IMEC, Infineon, University of Pavia, RFDomus, STMicroelectronics, etc.). His main research interests are in the design of CMOS mixed analog/digital integrated circuits, in particular for lowpower and/or high-speed signal processing. He has participated in several research collaborations, also funded by National and European projects. He is
and has been responsible for some National and Regional projects for the design of ASICs. Since 1989, he has collaborated with several companies on the
design of mixed-signal ASICs, including STMicroelectronics, Mikron, ACCO,
ITC-IRST, IMEC, RFDomus (he was in its Advisory Board), etc. He has authored or co-authored more than 190 papers in international journals and presentations at international conferences, six book chapters, and holds 25 U.S.
patents. In addition, he has co-authored more than 120 papers within research
collaborations on high-energy physics experiments. He has a long-term experience in microelectronics in teaching, researching, and industrial designing. He
has been teaching regular academic courses since 1997. He organized the full
educational courses for electronics engineering (Bachelor, Master, and Ph.D.) at
the University of Lecce. He has given industrial courses since 1996 (in Bosch,
STMicroelectronics, ITC-IRST, Conexant, Mikron, etc.). He is a speaker at the
MEAD Summer courses held at EPFL (Lausanne, Switzerland). He has given
short courses or tutorial at the most important conferences (ISSCC, ISCAS,
PRIME).
Dr. Baschirotto was an Associate Editor for IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS–PART II for the period 2000–2003, and of
TRANSACTIONS ON CIRCUITS AND SYSTEMS–PART I for the period 2004–2005.
He was the Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS
special issue on ESSCIRC 2003. He was the Technical Program Committee
Chairman for ESSCIRC 2002, and he was the General Chair of PRIME2006.
He is a member of the Technical Program Committee of several international
conferences, including ISSCC, ESSCIRC, and DATE. Since 2008, he has
been the Secretary of the European Committee of ISSCC. He is the General
Coordinator of a National PRIN Project on reconfigurable high-dynamic range
gas sensor systems.
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Nicola Ghittori received the Laurea degree (summa
cum laude) and the Ph.D. degree in electronic engineering from the University of Pavia, Italy, in 2002
and 2006, respectively. During his Ph.D., he worked
on CMOS analog circuits for wireless transceivers
and analysis of package and substrate crosstalk in
mixed-signal integrated circuits.
He is currently with Marvell Semiconductor,
Pavia, Italy.
Andrea Vigna was born in Broni, Italy, in 1977.
He received the Laurea degree (summa cum laude)
and the Ph.D. degree in electrical engineering and
computer science from the University of Pavia, Italy,
in 2002 and 2006, respectively. During his Ph.D.,
he worked on analog integrated circuits for wireless
transceivers, in CMOS technologies, with particular
focus on the analysis and design of D/A conversion
systems for multistandard transmitters.
He is currently with Maxim Integrated Products
(System and Power Management Business Unit),
Pavia, Italy.
Piero Malcovati (M’95–SM’05) was born in Milano, Italy, in 1968. He received the Laurea degree
(summa cum laude) in electronic engineering from
the University of Pavia, Italy, in 1991. In 1992, he
joined the Physical Electronics Laboratory (PEL)
at the Federal Institute of Technology in Zurich
(ETH Zurich), Switzerland, as a Ph.D. candidate. He
received the Ph.D. degree in electrical engineering
from ETH Zurich in 1996.
From 1996 to 2001, he was an Assistant Professor
in the Department of Electrical Engineering, University of Pavia. Since 2002, he has been an Associate Professor of electrical measurements in the same institution. His research activities are focused on microsensor interface circuits and high performance data converters. He has authored or co-authored more than 40 papers in international journals, more than
150 presentations at international conferences (with published proceedings),
seven book chapters, and five industrial patents.
Dr. Malcovati was a co-recipient of the ESSCIRC 2007 Best Paper Award.
He was guest editor for the Journal of Analog Integrated Circuits and Signal
Processing for the special issue on IEEE ICECS 1999. He served as Special
Session Chairman for the IEEE ICECS 2001 Conference, as Secretary of the
Technical Program Committee for the ESSCIRC 2002 Conference and as Technical Program Chairman of the IEEE PRIME 2006 Conference. He was and still
is a member of the Scientific Committees for several international conferences,
including ESSCIRC, DATE, and PRIME. He is the regional editor for Europe
of the Journal of Circuits, Systems, and Computers, as well as Associate Editor
for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II.