Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well
Transistor on Silicon Substrate using Thin (≤ 2 µm) Composite Buffer Architecture
for High-Speed and Low-voltage ( 0.5V) Logic Applications
M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau*, J. Kavalieros, W. K. Liu*, D. Lubyshev*,
R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau
Technology and Manufacturing Group, Intel Corporation, Hillsboro, OR-97124, USA
*IQE Inc, Bethlehem, USA
Contact: robert.s.chau@intel.com
Abstract
This paper describes for the first time, the heterogeneous
integration of In0.7Ga0.3As quantum well device structure on
Si substrate through a novel, thin composite metamorphic
buffer architecture with the total composite buffer thickness
successfully scaled down to 1.3µm, resulting in highperformance short-channel enhancement-mode In0.7Ga0.3As
QWFETs on Si substrate for future high-speed digital logic
applications at low supply voltage such as 0.5V.
Introduction
The InGaAs quantum well field effect transistor
(QWFET) is one of the most promising device candidates for
future high-speed and low-power digital logic applications
due to high electron mobility, large Γ to L valley separation
and good short-channel performance [1-3]. A seamless,
robust heterogeneous integration of high-performance
InGaAs QWFET on Si substrate will allow low-voltage,
high-speed III-V based logic circuit blocks to couple with the
main stream Si CMOS platform for future microprocessor
applications, while avoiding the need for developing large
diameter (≥300mm) III-V substrates. This paper describes in
detail for the first time, the integration of In0.7Ga0.3As
quantum well (QW) structure on Si through a novel, thin
composite metamorphic buffer architecture consisting of
GaAs and graded InxAl1-xAs layers, resulting in short-channel
enhancement-mode In0.7Ga0.3As QWFETs on silicon with
high performance at low supply voltage of 0.5V.
Materials Growth and Characterization
In0.7Ga0.3As quantum well (QW) device layers shown in
Fig. 1 were heterogeneously grown on 4o off-cut (100) p-type
Si substrates with lattice mismatch of >8% using a composite
metamorphic buffer consisting of GaAs and graded
InxAl1-xAs layers by solid source MBE. The thickness of the
composite buffer is successfully scaled down to 1.3µm for
the first time without degrading the properties of In0.7Ga0.3As
QW. Figs. 2a-2b show cross-sectional TEM images of the
entire structure grown on Si with 1.5µm and 1.3µm
composite buffer, respectively. In both cases, the misfit and
threading dislocations are predominantly contained in the
composite buffer, and the active device layers are virtually
defect-free, which is also shown in Fig. 2c using highresolution TEM. The relaxation state and the grading scheme
1-4244-0439-X/07/$25.00 © 2007 IEEE
were evaluated using high-resolution x-ray rocking curve, as
shown in Fig. 3. The angular separation between the
diffraction peaks of GaAs with respect to Si confirms full
relaxation of the GaAs layer. The indium composition of the
InxAl1-xAs buffer layer is graded from 0 to 52%, with an
overshoot of indium concentration (0.52<x<0.7) in-between,
as evidenced by the two peaks existing in the InxAl1-xAs
buffer region of Fig. 3. This overshoot was employed to
ensure full relaxation of this buffer layer while minimizing its
total thickness. The relaxation of the entire composite buffer
layer allows the growth of a defect-free In0.7Ga0.3As QW on
Si (Figs.2a-2c). Figs. 2c and 3 suggest the In0.7Ga0.3As QW
layer is compressively strained with respect to the
In0.52Al0.48As barrier. AFM surface morphology of the
In0.7Ga0.3As QW layers grown on Si with 2µm and 1.3µm
composite buffers exhibit a cross-hatch pattern, as shown in
Figs. 4a and 4b respectively, demonstrating excellent
metamorphic growth of the buffer layers. The surface rms
roughness of In0.7Ga0.3As QW grown on Si was measured
over an area of 5x5µm2 to be less than 4nm, which is similar
to that of In0.7Ga0.3As QW grown on GaAs [4].
Figure 5a shows the In0.7Ga0.3As QW mobility at 300K
and 77K as a function of total buffer thickness ranging from
3.2µm to 1.3µm of the composite buffer grown on Si. No
mobility degradation is observed for all the buffer
thicknesses, demonstrating that the thin composite
metamorphic buffer architecture is effective in filtering
dislocations. Fig. 5b compares the Hall mobility versus sheet
carrier density (Ns) measured in the In0.7Ga0.3As QW layers
grown on Si, GaAs and InP substrates at 300K and 77K. For
a given Ns, the mobility in the In0.7Ga0.3As QW layer grown
on silicon via the composite buffer is equivalent to those in
the In0.7Ga0.3As QW layers grown on III-V substrates such as
GaAs and InP. No degradation in QW mobility on Si is
observed despite the >8% lattice mismatch, demonstrating
effective dislocation filtering using the composite buffer on
Si. Fig. 6a shows the quantitative mobility spectrum analysis
(QMSA) for In0.7Ga0.3As QW on Si at different temperatures.
The large conductivity ratio between the majority carrier
(electrons) and the minority carrier (holes) at all temperatures
and also the increase in electron mobility with decreasing
temperature suggest no parallel, parasitic conduction in Si or
through the composite buffer layer. In addition, both Ns and
mobility exhibit no dependence on magnetic field at different
625
Device Characteristics
Figure 7 shows the SEM micrograph of an In0.7Ga0.3As
QWFET on Si with the composite buffer described above.
The use of a combination of wet and RIE etch to recess the
gate towards the channel, as well as Pt/Au Schottky gates,
enable enhancement-mode (e-mode) operation and improve
short channel performance of the device. The ID-VDS
characteristics of the e-mode LG=80nm In0.7Ga0.3As QWFET
on Si with 1.3µm composite buffer layer is shown in Fig. 8.
Figs. 9a and 9b show the ID-VG characteristics of the e-mode
LG=80nm In0.7Ga0.3As QWFETs on Si with 2µm and 1.3µm
buffer, respectively. The Schottky gate leakage is also
included for reference. Both devices exhibit good transistor
characteristics and high performance at VDS=0.5V. The
LG=80nm In0.7Ga0.3As QWFET on Si with 1.3µm composite
buffer achieves threshold voltage (VT) = + 0.11V, IDsat =
0.32mA/µm and ION/IOFF = 2150 at VDS=0.5V with 0.5V VG
swing. Fig. 10 shows VT as a function of LG for the e-mode
and depletion-mode (d-mode) In0.7Ga0.3As QWFETs on Si. A
positive VT shift of ~600mV from d-mode to e-mode
operation was accomplished through gate recess etch. Figs.
11 and 12 show the sub-threshold slope (SS) and drain
induced barrier lowering (DIBL), respectively as a function
of LG for In0.7Ga0.3As QWFETs on Si, demonstrating
improved SS and DIBL of e-mode over d-mode devices.
Fig.13 shows the transconductance (Gm) characteristics of emode and d-mode LG =80nm In0.7Ga0.3As QWFETs on Si
with different composite buffer thicknesses at VDS = 0.5V.
The improved Gm’s of the e-mode devices with 1.3µm and
1.5µm buffer layers over that of the e-mode device with 2µm
buffer are due to the improved transistor fabrication process.
Fig. 14 shows the current gain (h21) versus frequency of the emode LG=80nm In0.7Ga0.3As QWFET on Si with 1.3µm
composite buffer at VDS = 0.5V. Fig. 15 shows the cut-off
frequency as a function of DC power dissipation comparing
the e-mode LG=80nm In0.7Ga0.3As QWFET on Si with 1.5µm
composite buffer at VDS=0.5V versus the standard LG=60nm
Si n-MOSFET transistor at both VDS=0.5V and 1.1V.
Comparing to the Si n-MOSFET, the e-mode In0.7Ga0.3As
QWFET on Si exhibits >10X reduction in DC power
dissipation for the same speed performance or >2X gain in
speed performance for the same power.
Conclusions
In0.7Ga0.3As quantum well structure has been successfully
integrated onto Si substrate using a novel, thin composite
metamorphic buffer architecture with total buffer thickness
scaled down to 1.3µm, resulting in high-performance shortchannel enhancement-mode In0.7Ga0.3As QWFETs on Si
substrate with good device characteristics for future highspeed, ultra-low power digital logic applications.
References
[1]S. Datta et al, IEEE Electron Dev. Lett., vol. 28 (8), p. 685 (2007).
[2]D. Kim and J. A. del Alamo, IEDM Tech. Dig., p. 837 (2006).
[3]Y. Yamashita et al, IEEE Electron Dev. Lett., vol. 23 (10), p. 573 (2002).
[4]D. Lubyshev et al, J. Vac. Sci. Technol. B, vol. 22 (3), p. 1565 (2004).
n++-In0.53Ga0.47As contact
InP etch stop
: 20 nm
: 6 nm
In0.52Al0.48As top barrier
: 8 nm
Si delta-doped layer
In0.52Al0.48As spacer layer
: 5 nm
In0.7Ga0.3As channel
: 13 nm
In0.52Al0.48As bottom barrier
: 100 nm
InxAl1-xAs graded buffer (x=0-0.52): 0.7-1.1 µm
GaAs nucleation and buffer layer: 0.5-2.0 µm
4o(100) Offcut p-type Si substrate
Metamorphic buffer
temperatures, as shown in Fig. 6b, further indicating no
parallel, parasitic conduction in the buffer layer or in Si.
Fig.1: Heterogeneous integration of In0.7Ga0.3As QWFETs on Si using
metamorphic composite buffer architecture consisting of GaAs and
InxAl1-xAs graded buffer layers. The composite buffer in this work has
total thickness in the range of 1.3µm to 3.2µm.
In0.7Ga0.3 As QW
0.8 µm InxAl1-xAs
0.7 µm GaAs
Si
Fig. 2a: Cross-sectional TEM image of In0.7Ga0.3As QWFET on Si
using 1.5µm composite buffer. The misfit and threading dislocations are
predominantly contained in the composite buffer, with the In0.7Ga0.3As
QW virtually defect-free.
In 0.7Ga 0.3As QW
0.8µm InxAl1-xAs
0.5µm GaAs
Si
Fig. 2b: Cross-sectional TEM image of In0.7Ga0.3As QWFET on
Si using composite buffer with total thickness of 1.3µm. The
active In0.7Ga0.3As QW is virtually defect-free.
626
Si substrate
InxAl1-xAs graded buffer
GaAs buffer
In0.53Ga0.47As cap layer
3.2µm
X- ray Intensity [a.u]
InP etch stop
In0.52Al0.48As top barrier
In0.7Ga0.3As QW
2µm
1.6µm
1.5µm
1.3µm
In0.7Ga0.3As
Quantum well
-15000
In0.52Al0.48As bottom barrier
Fig. 2c: High-resolution TEM of In0.7Ga0.3As
QW, In0.52Al0.48As barriers, InP etch stop and
In0.53Ga0.47As cap layer. The device layers are
defect-free.
2µm buffer
-10000
-5000
Omega/2theta [arcsec]
0
40000
10000
300K
77K
1000
1.2
13
Electron
Hole
-5
12
-2
Sheet Carrier Density [cm ]
-1
Conductivity [Ω ]
200K
-3
-5
10
-7
10
75K
-3
10
77K
77K
77K
77K
20000
10000
300K
12
2x10
12
4x10
12
2DEG sheet carrier density [cm-2]
4
11
3
10 13
10
10 5
10
200K
4
10
11
Source
3
1013
10
105
10
75K
4
10
10
Gate
Active
device
region
Source
Mesa
isolation
(Stop on
InAlAs
bottom layer)
Gate air-bridge
-7
11
2
10
3
4
10
10
Mobility [cm2/Vs]
5
10
Fig. 6a: QMSA mobility spectra for
In0.7Ga0.3As QW on Si at different temperature
demonstrating no parallel, parasitic conduction
to the active In0.7Ga0.3As channel.
10
3
3
10
4
10
Field [Gauss]
10
5
10
Fig. 6b: Sheet carrier density (Ns) and electron
mobility show no dependence on magnetic field at
different temp, indicating no parallel, parasitic
conduction in the composite buffer layer on Si.
Fig.7: SEM micrograph of a two-finger
In0.7Ga0.3As QWFET on Si with Pt/Au gate airbridge at the mesa edge and Ti/Pt/Au source/drain
metals.
627
12
6x10
Fig. 5b: Electron mobility versus sheet carrier density
(Ns) in In0.7Ga0.3As QW grown on Si (via novel
composite buffer), GaAs and InP substrates at 300K
and 77K. No degradation in QW mobility on Si
despite >8% lattice mismatch, demonstrating
effective dislocation filtering with the composite
metamorphic buffer architecture on Si.
10
-5
10
300K;
300K;
300K;
Drain
-7
On Si
On GaAs
On InP
30000
10
3.2
10
300K
10
10
10
2.8
5
10
300K
10
2.4
Mobility [cm2/Vs]
-3
2.0
Composite buffer layer thickness [µm]
Fig. 5a: In0.7Ga0.3As QW electron mobility versus
composite buffer layer thickness on Si at 300K and
77K. No mobility degradation is observed,
demonstrating that the metamorphic buffer
architecture is effective in filtering dislocations.
Fig. 4b: AFM image from the surface of
In0.7Ga0.3As QW layer on Si with 1.3µm
composite buffer shows cross-hatch pattern
with surface rms roughness of 39Å.
10
1.6
2D Hall electron mobility [cm2/Vs]
Quantum well mobility [cm2/Vs]
40000
1.3µm buffer
Fig. 4a: AFM image from the surface of
In0.7Ga0.3As QW layer on Si with 2µm
composite buffer shows cross-hatch pattern
with surface rms roughness of 30Å.
Fig. 3: High-resolution x-ray rocking curves from
the (004) Bragg lines of In0.7Ga0.3As QWFET
structures on Si substrates with different composite
buffer thicknesses ranging from 1.3-3.2µm.
10
VGS = 0.5V
1.3 µm buffer
-1
0.30
0.3V
0.10
0.2V
0.05
-3
10
-4
10
-5
10
0.00
0.0
0.1
0.2
0.3
0.4
-7
10
-0.4
0.5
Drain voltage, VDS [V]
200
0.2
-0.2
600mV
-0.4
-0.6
e-mode on Si with 1.3µm buffer
e-mode on Si with 2µm buffer
d-mode on Si with 2µm buffer
50
75
100
125
150
175
200
180
120
100
80
60
50
225
Gm [ µS / µm ]
1400
1200
1000
150
175
200
Embedded
fT = 302 GHz
600
400
200
VDS = 0.5V
0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
Fig.13: Transconductance, Gm characteristics
of e-mode and d-mode LG =80nm In0.7Ga0.3As
QWFETs on Si with different composite
buffer thicknesses at VDS = 0.5V.
400
Fig. 14: Current gain (h21) versus frequency
for the 80nm LG enhancement-mode
In0.7Ga0.3As QWFET on Si with 1.3µm
composite buffer, showing the embedded and
de-embedded data at VDS = 0.5V.
e-mode In0.7Ga0.3As QWFET on Si
with 1.5µm buffer
350
300
250
VDS = 0.5V
1.1V
200
VDS = 0.5V
150
100
50
Frequency [Hz]
225
Fig.12: DIBL as a function of LG for emode and d-mode In0.7Ga0.3As QWFETs on
Si, showing improved DIBL of e-mode
devices over d-mode due to shorter gate to
channel separation in e-mode.
450
-20 dB/dec
0.6
Gate length, LG [nm]
De-embedded
800
Gate voltage, VG [V]
225
Model
IG @VDS=0.5V
-0.2
0.0
0.2
0.4
Gate voltage, VG [V]
220
e-mode on Si with 1.3µm buffer
200
e-mode on Si with 2µm buffer
180
d-mode on Si with 2µm buffer
160
140
120
100
80
60
40
20 VDS = 0.5V
0
50
75
100 125 150 175 200
Fig. 11: Sub-threshold slope (SS) as a function of
LG for e-mode and d-mode In0.7Ga0.3As QWFETs
on Si, showing improved SS of e-mode over dmode devices due to shorter gate to channel
separation in e-mode.
|h21| [dB]
1600
125
-0.4
Gate length, LG [nm]
Fig. 10: Threshold voltage (VT) as a function of LG
for enhancement-mode (e-mode) and depletionmode (d-mode) In0.7Ga0.3As QWFETs on Si.
Positive VT shift of about 600mV from d-mode
operation to e-mode operation was accomplished
through gate recess etch.
e-mode on Si: 1.3µm buffer
e-mode on Si: 1.5µm buffer
e-mode on Si: 2µm buffer
d-mode on Si: 2µm buffer
100
IG @VDS=0.05V
1.3 µm buffer
Fig. 9b: Drain current (ID) and gate leakage (IG)
versus VG of enhancement-mode LG=80nm
In0.7Ga0.3As QWFET on Si with 1.3µm
composite buffer at room temperature. VT =
+0.11V, IDsat = 0.32mA/µm, ION/IOFF = 2150 at
VDS=0.5V with 0.5V VG swing.
VDS = 0.5V
75
-5
10
-7
e-mode on Si with 1.3µm buffer
e-mode on Si with 2µm buffer
d-mode on Si with 2µm buffer
140
-4
10
10
0.6
160
Gate length, LG [nm]
1800
-0.2
0.0
0.2
0.4
Gate voltage, VG [V]
-3
10
10
Fig. 9a: Drain current (ID) and gate leakage (IG)
versus VG of enhancement-mode LG=80nm
In0.7Ga0.3As QWFET on Si with 2µm composite
buffer at room temperature. VT = + 0.07V, IDsat =
0.25mA/µm, ION/IOFF = 2500 at VDS=0.5V with
0.5V VG swing.
Sub-threshold slope [mV/dec]
Threshold voltage, VT @VDS=0.05V
Fig.8: ID-VDS characteristics of enhancementmode LG=80nm In0.7Ga0.3As QWFET on Si
with 1.3µm composite buffer at room
temperature.
0.0
2 µm buffer
10
-6
IG @VDS=0.05V
IG @VDS=0.5V
-6
10
0.1V
DIBL [mV/V]
0.15
10
ID & IG [mA/µm]
0.20
ID @ VDS =0.5V
-2
Cut-off frequency, fT [GHz]
0.4V
ID @ VDS =0.05V
-1
10
-2
0.25
-0.8
10
ID @ VDS =0.05V
ID @ VDS =0.5V
10
ID & IG [mA/µm]
Drain current, ID [mA/µm]
0.35
0
0
0.40
Si n-MOSFET
Si n-MOSFET
10
1
2
3
10
DC power dissipation [µW/µm]
10
Fig. 15: Cut-off frequency as a function of DC power
dissipation for the enhancement-mode LG=80nm
In0.7Ga0.3As QWFET on Si with 1.5µm composite
buffer at VDS=0.5V, versus standard Si n-MOSFET
transistor with LG = 60nm at VDS=0.5V and 1.1V.
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