PERFORMANCE ESTIMATE FOR HIGH-SPEED CMOS-CURRENT-MODE-LOGIC
CIRCUTS BASED ON OUTPUT VOLTAGE SWING CONSIDERATIONS
Niels Christoffers, Renee Lerch, Bedrich J. Hosticka, Stephan Kolnsberg, Rainer Kokozinski
Fraunhofer Institute for Microelectronic Circuits and Systems
Finkenstraße 61
47058 Duisburg,Germany
niels.christoffers@ims.fhg.de
ABSTRACT
Current-mode-logic circuits play an important role in the
design of CMOS frequency synthesizers for modern wireless digital communication systems. They provide the building blocks for frequency dividers with input frequencies in
the range of the desired carrier frequencies. In this communication we estimate the upper limit frequency as a function
of the gate length using voltage swing considerations.
1. INTRODUCTION
High-speed digital circuitry, i.e. gates and flipflops, plays a
substantial role in PLL-based frequency synthesizers used
in modern wireless digital communication systems. The
output frequency fout of the synthesizer shown in Figure 1
is generated by a VCO that is exposed to strong component
value variations. It is required to be a known multiple M of
the accurate reference frequency fref produced by a crystal
oscillator and therefore has to be controlled using negative
feedback. A frequency divider is employed to obtain a signal the frequency fd = fout =M of which can be compared
with the reference frequency by means of a Phase- and Frequency Detector (PFD) that produces a corrective signal for
the VCO via charge pump and loop filter. [3]
ref
f
up
PFD
f
d
VCO
dn
f
The divider is a digital counter. It has to be designed for
a bandwidth at least as high as the output frequency of the
synthesizer. Current-mode-logic (CML) building-blocks [5]
are often proposed as solution to meet such requirements
using easily available and cost-saving CMOS processes [1,
4].
In this communication we present several insights into
the design of current-mode flipflops and gates. Using a simplified formula for the drain current of short channel MOSFETS presented in [6], a simplified definition of delay and
considerations of the necessary DC-gain we establish fundamental limitations for the output voltage swing of CML
building blocks and relate it to the minimum gate length
of the employed transistors. We show that for low VCO
frequencies the current drawn from the supply is proportional to the square of the frequency and the cube of the
gate length, but can increase faster for sufficiently high frequencies.
In Section 2 we present the block level schematic of a
prescaler used in a frequency divider of a synthesizer and
compute the delay requirements of the employed gates. In
Section 3 the circuits realizing high-speed gates and flipflops
are presented. Their design, especially the necessary output
voltage swing, is discussed in Section 4: The results allow
prediction of available gain and delay of the flipflops and
gates for a given technology. A summary is given in Section 5.
out
%M
Figure 1: Block level schematic of a frequency synthesizer
2. A PRESCALER USING CML BUILDING
BLOCKS
One possible block level schematic for a frequency divider
is given in Figure 2[1]. The depicted divider comprises a
prescaler that divides by N +1 or N , depending on whether
MC is high or low, a program counter with modulus P , and
the swallow counter that will output an overflow indication
to MC after S input impulses and afterwards stop operation until it is restartet by a reset impulse from the program
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counter. The complete circuit generates a division
M = PN + S:
(1)
Program Counter
Prescaler
MC
current flows through the first while the latter is off. The
output is directly controlled by the input. A falling edge of
the clock turns the differential pair off and lets IBIAS flow
through the cross coupled pair. Having two stable states,
namely I6 = IBIAS and I7 = 0 or I6 = 0 and I7 = IBIAS it
holds the output of the latch in that state observed in the immediate instant before the transition of the clock. A flipflop
is realized using two latches in a master-slave configuration.
Swallow Counter
R
RL
reset
vD+
Figure 2: Block level schematic of a frequency divider
M4
RL
vQ+
vQ;
I6
I7
vD;
M5
M6
The building block with the highest input frequency
fCLK = fout is the prescaler. The schematic of it in case
of N = 15 is given in Figure 3. Consider a situation
when the output state of the flipflops is (Q1 Q2 Q3 Q4) =
(0 1 0 1) and MC is low. A rising edge of the clock causes
Q 3 to go low after the delay FF2 + FF3 of FF2 and FF3 .
3 and Q 4 are low propaNow, the information that both Q
gates through the gates G1, G2, and G3 with their delays
G1, G2 , and G3, respectively, to the input of FF2. It has
to arrive before the next rising edge triggers the prescaler to
compute the next state based on the inputs of the flipflops.
If not
FF2 + FF3 + G1 + G2 + G3 < f 1
(2)
CLK
the circuit will malfunction [1].
1
D
CLK
FF1 Q
vCLK +
M3vCLK ;
M2
IBIAS
M7
M1
Figure 4: Current-Mode Latch.
The current-mode-gate depicted in Figure 5 realizes the
AND-function. However, since inverters can easily be realized by interchanging the two lines of a differential signal
path it can act as an OR- NAND- or NOR-gate as well if the
DeMorgan-rules are exploited.
G1
G2
1
1 G3
&
D
FF2
Q
D
FF3
D
Q
FF4
RL
RL
out
Q
vB+
MC
Figure 3: Block level schematic of the prescaler within the
divider
IBIAS
M4
vA+
v Q;
vQ +
vB ;
M5
M2
M3
M1
3. CML LATCHES AND GATES
Figure 5: Current-Mode Gate
The schematic of a current-mode-logic latch is given in Figure 4. It contains a differential pair M4 /M5 and a pair of
cross coupled MOSFETS M6 /M7. If the clock input is high
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vA;
4. DESIGN CONSTRAINTS FOR CML-CIRCUITS
In order to rate CML-circuits in terms of their high-frequency
behaviour we first estimate the delay through the input differential pair of either latch or gate to be
RLCL = I v^ CL BIAS
(3)
where CL is the total capacitance connected to one of the
two differential output nodes and v^ the single ended output
voltage swing. Assuming n identical input stages are connected we obtain
= n0
(4)
where 0 = RLCox WL, Cox is the specific oxide capacitance, and W and L are the width and the length of the
input transistors, respectively. Note that according to (2) 0
must be inversely proportional to the input frequency fCLK .
During the design of CML building blocks a proper setting of the output voltage swing v^ is indispensible for two
reasons discussed in the following.
Note that the transistor M1 in both latch and gate must
be kept in saturation. Therefore the voltage drop across the
load resistance and the transistor pairs M2 /M3, M4 /M5 in
latch and gate and additionally across M6/M7 in the latch
is limited. We assume that an upper bound for the voltage
drop across the transistors is defined:
IBIAS RON Mx < VON max
(5)
where RON Mx is the ON-resistance of a transistor Mx . If
this requirement is met for M4 /M5/M6/M7 it is met for
M2 /M3, too, since their gate source voltage in ON-state is
higher and hence their ON-resistance lower.
The ON-resistance of the transistors M4 and M5 is [2]
L
1
RON = W
e Cox (VDD ; v^ ; RON IBIAS ; VT )
(6)
where e
0:04m2=(vs) is the electron mobility. We can
find an upper bound for the output voltage swing multiplying (6) by IBIAS , solving for IBIAS RON and afterwards
solving (5) for v^. We obtain:
(VDD ; VT ; VON max )
v^ < e VON max
L2 = + V
0
e ON max
(7)
The upper bound for the voltage swing is nearly independent of 0 for very high delays. However, it will fall linearily when 0 is much smaller than L2 =(e VON max )
To establish a lower bound for the output voltage swing
we observe the output signal of a differential pair after a
change of the input voltage from ;v^ to +^
v . After the subsequent settling process has finished we require the output
voltage to be identical to the input voltage. However, it cannot be higher than the input voltage times the DC-gain of
the differential pair. We demand
ADC = gm RL > Amin > 1
(8)
The transconductance of the MOSFETs in the differential
pair can be expressed in terms of the current using a simplified formula for the drain current in short channel MOSFETS proposed in [6]:
e Cox W (VGS ; VT )2 LEsat
(9)
2 L VGS ; VT + LEsat
where Esat
4 106V/m is the field strength for velocity
saturation. Solving (9) for VGS ; VT and computing the
derivative @VGS =@ID we find
1 =
1
gm
e Cox WEsat +
2
q ID = (e Cox Esat)2 + L= (WCox ) (10)
ID2 = (e Cox Esat) + 2ID L= (WCox )
ID
Substituting the delay, the load capacitance , the output voltage swing we re require from (8)
2 v^ > 20 Esat
q
2 L2
A
min
;1 + 1 + e 0 Esat (e 0 Esat ;2AminL) (11)
p
Using a the Taylor series based approximation 1 + x
1 + x=2 we find that for long delays 0 the voltage swing v^
is inversely proportional with 0 and grows linearly with L2 .
The minimum current IBIAS = v^CL =0 therefore grows
with the square of the input frequency fCLK and with the
cube of the gate length L if the transistor width W remains
unchanged. If 0 approaches 2Amin L=(e Esat ) the out-
put swing and the current theoretically even become infinite. For that reason a decrease of the gate length L has
a tremendeous impact on the power consumption of CML
frequency dividers for high input frequencies.
Still, the question of the necessary DC-gain remains to
be answered: One typical output signal of the positive output node of FF3 obtained by circuit simulations for an input
frequency of 1.5GHz is depicted in Figure 6. The disturbances highlighted by circles stem from the fact that the output signal of FF2 has no perfect rectangular shape. Therefore, during its transitions with finite slope the current IBIAS
is shared by the differential pair M4 /M5 and the cross coupled pair M6 /M7 so that both possess less than IBIAS . The
total gain from the input to the output therefore drops and
causes the output to decrease. To prevent the output from
reaching the trip point between High and Low a sufficient
margin must be added to the DC-gain. From simulations we
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5. SUMMARY
ff3out
Figure 6: Output signal at the positive node of
simulations)
FF3 (from
infer that ADC
3 allows robust operation of the circuits.
However, it should be increased if disturbances are expected
in addition to that discussed above.
Having established an upper and lower bound for the
output voltage swing of current-mode latches and gates we
are now in the position to determine the minimum delay
given the gate length and the necessary DC-gain. For sufficiently low 0 it is impossible to find u
^ in such a way that
both requirements (7) and (11) are met. In Figure 7 the
maximum available DC-gain is displayed versus 1=0 for a
maximum voltage drop VON max = 0:25V and several gate
lengths L. The higher the DC-gain the more robust to disturbances the circuits will be. We can see that for a transistor
length L = 0:6m and a minimum DC-gain of ADC = 3
1=0 can be no higher than 13 109/s. For the prescaler we
find the critical delay of (2) to be 70 if the delays of the
single blocks are computed using (4). The maximum input
frequency to the divider would therefore be in the vicinity
of 1.7 GHz which is slightly higher than the maximum input
frequency of the divider used for circuit simulations.
= 0:13m
L
8
6
5
L
= 0:25m
4
L
3
0.5
1
1.5
[2] Allen P.E. Holberg D.R. CMOS Analog Circuit Design.
Oxford University Press. Inc, New York, 1st edition,
1987.
[3] Egan W. F. Frequency Synthesis by Phase Lock. John
Wiley and Sons, INC., New York, Chichester, Brisbane,
Toronto, 1. edition, 1981.
[6] Lee T.H. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press. Inc, New
York, 1st edition, 1998.
= 0:6m
2
1
[1] Razavi B. RF Microelectronics. Prentice-Hall Inc., Upper Saddle River, 1st edition, 1997.
[5] J. Musicer J.M. Rabaey. MOS Current Mode Logic
for Low Power, Low Noise CORDIC Computation in
Mixed-Signal Environment. In Proc. ISLPED, pages
102–107, 2000.
7
ADC
6. REFERENCES
[4] Craninckx J. Steyaert M. Wireless CMOS Frequency
Synthesizer Design. Kluwer Academic Publishing,
Boston, Dordrecht, London, 1. edition, 1998.
10
9
In the preceeding sections we have provided insights into
the design of frequency dividers using current-mode-logic
with input frequencies in the vicinity of theoretical limits.
These limits have been estimated by finding requirements
for the output voltage swing as a function of the delay requirement for the gates and latches.
Simulations indicate that the performance estimates are
very helpful at finding the maximum possible performance
of a current-mode-logic circuit. However deviations must
be accepted since the transconductances found by simulations are slightly (approximately 10%) lower than those predicted by (10). Also, the foregoing discussion neglects parasitic capacitances arising from the interconnects between
the transistors and the resistors.
Nevertheless it has been shown that a lower and upper
bound for the output voltage swing exist and approach each
other for increasing frequencies. For sufficiently high frequencies the output voltage swing cannot meet both requirements. The current consumed by the circuits increases with
the square rather than linearly with the frequency.
2
2.5
3
3.5
1=0 s
4
4.5
5
5.5
x 10
6
10
Figure 7: Maximum DC-gain versus inverse delay for different gate lengths.
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