Vol. 35, No. 8
Journal of Semiconductors
August 2014
A PSR single-stage flyback LED driver with simple line regulation and
quasi-resonant operation
Nie Weidong(聂卫东)1; 2; Ž , Yu Zongguang(于宗光)1 , Wang Haibing(王海兵)2 , Guo Bin(郭斌)2 ,
Teng Long(滕龙)2 , and Yang Lihang(杨力航)2
1 Department
2 Wuxi
of Electronic Engineering, Jiangnan University, Wuxi 214122, China
Crystal Source Electronics Co., Ltd., Wuxi 214028, China
Abstract: A single-stage flyback driving integrated circuit (IC) for light-emitting diodes (LEDs) is proposed. With
an average primary-side current estimation and negative feedback networks, the driver operates in the boundary
conduction mode (BCM), while the output current can be derived and regulated precisely. By means of a simple
external resistor divider, a compensation voltage is produced on the ISEN pin during the turn-on period of the
primary MOSFET to improve the line regulation performance. On the other hand, since the delay time between
the time that the secondary diode current reaches zero and the turn-on time of the MOSFET can be automatically
adjusted, the MOSFET can always turn on at the valley voltage even if the inductance of the primary winding varies
with the output power, resulting in quasi-resonant switching for different primary inductances. The driving IC is
fabricated in a Dongbu HiTek’s 0.35 m bipolar-CMOS-DMOS process. An 18 W LED driver is finally built and
tested. Results show that the driver has an average efficiency larger than 86%, a power factor larger than 0.97, and
works under the universal input voltage (85–265 V) with the LED current variation within ˙0.5%.
Key words: constant output current; single-stage flyback LED driver; primary-side-regulation; quasi-resonant
switching; line regulation
DOI: 10.1088/1674-4926/35/8/085008
EEACC: 2570
1. Introduction
Currently, illumination consumes about 25% of the
world’s total electric energy productionŒ1 . Thus green and
energy-efficient illumination technologies such as lightemitting diodes (LEDs) have attracted wide attention in the
past several decades. The performance of LEDs is significantly
affected by LED driving circuits. AC-to-DC switching power
supplies can achieve high efficiency, large power density, and
high control accuracy, making them ideal candidates for LED
driversŒ1 9 .
The primary-side-regulation (PSR) single-stage flyback
converter is being adopted more and more in general lighting applications, owing to its elimination of the opto-coupler,
simple control mode, good electrical isolation, high efficiency,
compact size and low cost.
However, many limitations for the PSR single-stage flyback converter exist. First, owing to the turn-off delay of primary MOSFETs and other intrinsic propagation delays, an error exists between the actual primary current and the estimated
current, and the error increases with increasing the input voltage. Thus the PSR flyback converter experiences a worse line
regulation under universal input voltage (85–265 V). Reference [4] is an intensive study on the line regulation, with a
complex sample and hold circuit to track and compensate the
turn-off delay cycle by cycle. The technique is effective, but
the control mode and circuit are complicated.
Second, the efficiency is still not good enough (only about
80%)Œ1; 6 9 . For the PSR single-stage flyback converter op-
erating in boundary conduction mode (BCM), in order to synchronize MOSFETs turning-on at the voltage valley to decrease
the switching losses, the traditional solution is to adopt a fixed
delay time (FDT) between the time that the secondary diode
current reaches zero and the turn-on time of the MOSFETŒ6; 7 .
However, when a primary winding with different inductance
value is used, the MOSFET cannot turn on at the voltage valley,
resulting in the increase of switching losses and the decrease
of efficiency. Reference [7] attempts to solve the problem by
adding a DLY pin and an external resistor RDLY . If the inductance value of primary winding is changed, the value of RDLY
should be adjusted for quasi-resonant operation. However, it is
inconvenient to use, and the cost of the driver and the volume
of the printed circuit board are increased.
In this paper, we develop a PSR single-stage flyback LED
driver with simple line regulation modification and quasiresonant operation. The error between the actual primary current and the estimated current can be compensated, leading
to the improved line regulation. Furthermore, by adopting
the proposed valley turn-on circuit with adaptive delay time
(ADT), the MOSFET turns on nearly at the valley voltage even
if the primary winding inductance varies with the output power.
Finally, a closed-loop, PSR single-stage flyback driver prototype for 18 W LEDs is constructed and tested. Results show
that the line regulation and the average efficiency are all improved.
2. Circuit configuration and operation
Figure 1(a) shows the main control circuit of the proposed
† Corresponding author. Email: youdanwd@163.com
Received 26 December 2013, revised manuscript received 19 March 2014
085008-1
© 2014 Chinese Institute of Electronics
J. Semicond. 2014, 35(8)
Nie Weidong et al.
Fig. 1. The proposed LED driver. (a) Control diagram. (b) Key control waveforms.
PSR single-stage flyback LED driver, which consists of an input AC source, bridge rectifier, input capacitor Cin , flyback
transformer, power MOSFET, LED driving integrated circuit
(IC), output rectifier diode Do and capacitor Co . The auxiliary
winding is used for providing the VIN supply voltage for the IC
and sensing the output voltage feedback signal to the ZCD. The
control IC includes an output current estimation circuit and a
power factor correction (PFC) control circuit. The former section provides the estimation of the LED output current based
on the sensed primary-side signals. The latter section provides
the control signal for the primary MOSFET based on the output
voltage of the operational transconductance amplifier (OTA) to
achieve the desired output current and high power factor (PF)
simultaneously.
The OTA along with the external capacitor Cext behaves as
an integrator. The dominating pole frequency of the converter
is determined by gm /(2 Cext /, where gm is the transconductance of OTA and designed to be 20 S, and Cext D 1 F. The
dominating pole frequency is about 3.2 Hz, which ensures that
the voltage on the COMP pin (Vcom / can remain almost constant during a line cycle. As the ramp slope of the saw-tooth
signal produced by the saw-tooth signal generator is fixed, the
MOSFET’s on-time (Ton .t// will remain unchanged also. Then
the primary current is in phase with the AC line voltage, resulting in high PF.
As shown in Fig. 1(a), the sample and hold (S/H) circuit
is adopted to sample the voltage across Rsen .Vsen .t//, and the
maximum value of Vsen .t/ (Vp_pk .t// over every switching period is held by the capacitor C1 , which is denoted by Vs1 .
K is used to amplify Vs1 . When the switch S is on, K is
able to drive the low-pass filter (LPF), and Vs1 can remain
constant. S is controlled by the detection signal Vc . During
the MOSFET’s off-time (Toff .t//, S is on. During Ton .t /, S
is off. The voltage signal after LPF (Vo_LPF / represents the
average value of the pulse voltage after S. Thus Vo_LPF D
K Vs1 Toff .t //(Ton .t/ C Toff .t //; K is the amplification factor
for Vs1 .
Vo_LPF is sent to the negative point of OTA and compared
with a fixed voltage Vref . Ton .t/ is determined by the integrator
voltage Vcom . If the LED output current increases, Vo_LPF will
be increased and Vcom will be decreased, resulting in a decrease
of Ton .t/. The peak value of the primary current (ip_pk .t// will
be decreased, causing the LED output current to decrease. Vice
versa, the LED output current is kept stable and constant.
The key control waveforms for illustration during a halfline period (Tline /2) are shown in Fig. 1(b) after the system enters normal operation.
Turn-on period (t1 –t2 /: the primary current ip .t/ rises linearly from zero to the peak value ip_pk .t/. No power is delivered through the transformer. The secondary winding current
is zero.
During this period, the ramp voltage signal is compared
with Vcom . At t D t2 , the ramp voltage reaches Vcom , and
the RS flip–flop outputs a “0” signal to turn off the MOSFET.
Meanwhile, Vp_pk .t/ is held by C1 by means of the S/H circuit.
Turn-off period (t2 –t3 /: the energy stored in the primary
winding is transferred to the secondary side, and the secondaryside current is (t) decreases linearly from its peak current
is_pk .t /. During this period, S is on to let the sampled voltage
signal pass. Since S is off during Ton .t /, the waveform of the
estimated voltage after S (Vs2 / is a pulse signal with an amplitude equal to Vp_pk .t / and a conduction period equal to Toff .t/
(Fig. 1(b)).
After Toff .t /, the secondary winding has run up energy, and
the RS flip–flop will receive a “1” signal from the valley turnon circuit, then the RS flip–flop will output a “1” signal to turn
on the MOSFET again, indicating the next switching period.
085008-2
The average value of the LED output current over a switch-
J. Semicond. 2014, 35(8)
Nie Weidong et al.
Fig. 2. Line regulation and valley turn-on circuit.
ing period (is_av .t // is given by
is_av .t / D
Np Toff .t/
1 Toff .t/
is_pk .t/ D
ip_pk .t /;
2 Ts .t/
2Ns Ts .t/
(1)
where Np and Ns are the primary and secondary winding
turns, respectively; Ts .t/ is the switching period, and Ts .t / D
Ton .t/ C Toff .t /.
Since Vo_LPF represents the average value of pulse voltage
after S, it can be expressed as
Vo_LPF D K
Toff .t/
Toff .t/
Vp_pk .t/ D K
isamp .t/Rsen ;
Ts .t/
Ts .t/
(2)
where isamp .t/ is the peak value of sampled current for Rsen ,
which equals ip_pk .t/. From Eqs. (1) and (2), Vo_LPF is expressed as
Ns
Vo_LPF D 2K Rsen is_av .t/:
(3)
Np
It indicates that the LED average value over a switching
period (is_av .t // can be derived from Vo_LPF . As Vo_LPF is sent
to the negative point of OTA, it follows Vref due to the negative
feedback loop of the converter over a line cycle. Then we have
Z 2
1
Vref D
Vo_LPF d!L t;
(4)
2 0
where !L is the angular frequency of the input AC line voltage.
Meanwhile，the average output current of the LED over a
line cycle (ILED / is expressed as
Z 2
1
is_av .t/d!L t:
(5)
ILED D
2 0
Comparing Eqs. (3) and (4) with Eq. (5), we can obtain
ILED as
Np
1
ILED D
Vref :
(6)
Ns 2KRsen
Since Vref and K have been decided by the IC, ILED is only
the function of Rsen and Np /Ns . In this way, the output current ILED can be regulated and kept constant, regardless of the
change of Vin and Vout .
3. The line regulation modification circuit
From Eqs. (1) and (2), it can be seen that is_av .t/ is obtained from ip_pk .t / and Vo_LPF is obtained from isamp .t/. It is
assumed that ip_pk .t/ equals isamp .t/ and then is_av .t/ is estimated by Vo_LPF . However, because of the actual turn-off delay of MOSFET and other internal delay, ip_pk .t / is bigger than
isamp .t /. The larger the input voltage is, the larger the difference
isŒ4; 6 .
The total delay time Td is mainly contributed by the turnoff delay in the MOSFET; it is almost constant for a universal
line systemŒ4 . The difference between them (ip_pk .t // can be
given by
ip_pk .t/ D ip_pk .t /
isamp .t/ D
Vline .t/
Td ;
Lp
(7)
where Vline .t/ is the rectified input line voltage, and Lp is the
inductance value of the primary winding.
Fortunately, the auxiliary winding is idle during the ontime of MOSFET. So it is used to produce a compensation voltage, which can be added to the ISEN pin to improve the line
regulation performance during this period. The proposed line
regulation modification circuit is shown in Fig. 2, which consists of a voltage reference Vr , a mirror current and an internal
compensation resistor Rsen_c .
In Fig. 2, switches S3 and S4 are on during the on-time
of the MOSFET. The auxiliary winding voltage Va .t / reflects
Vline .t/, which can be expressed by
085008-3
Va .t / D
Na
Vline .t/;
Np
(8)
J. Semicond. 2014, 35(8)
Nie Weidong et al.
where Na is the number of auxiliary winding turns.
The source current of M1 (I1 / is determined by Va .t / and
the external upper resistor Ru . Since R1 , Rd Ru , I1 jVa .t/j/Ru , where jVa .t/j is the absolute value of Va .t /. The
current through the resistor Rsen_c (I2 / is given by I2 D k1 I1 ,
where k1 is the W=L ratio of M3 to M1. Thus the voltage
across the compensation resistor Rsen_c (Vsen_c .t// is given
by
Na Vline .t/
Vsen_c .t/ D
k1 Rsen_c :
(9)
Np Ru
If Vsen_c .t/ D Rsen ip_pk .t/, combining Eqs. (7) and (9),
we can have
Td Rsen
Na k1 Rsen_c
D
:
(10)
LP
Np Ru
If the condition of Eq. (10) is met, Vsen_c .t/ D Rsen ip_pk .t /,
indicating that Vsen_c .t / reflects the actual value of ip_pk .t / and
the error between ip_pk .t/ and isamp .t/ is compensated to zero.
4. The proposed valley turn-on circuit
4.1. Valley turn-on circuit with ADT
The quasi-resonant switching mode should be applied to
reduce switching losses. In order to synchronize MOSFET
turn-on at the voltage valley even if a primary winding with
different inductance value is used, the valley turn-on circuit
with ADT is proposed, as shown in Fig. 2. It includes a resonant circuit, a voltage valley detector and a fixed time delay
circuit.
The delay time between the zero-crossing point of the secondary diode current and the MOSFET turn-on, labeled Td_on ,
is the sum of an adjustable delay time Td_a and a fixed delay
time Td_f . As shown in Fig. 2, Td_a is determined by a resonant
circuit and a voltage valley point detecting circuit, and Td_f is
determined by a D flip–flop D1, a timing-circuit, a comparator
C2, an inverter INV and a RS flip–flop SR1.
The equivalent resonant circuit is shown in the right side
of Fig. 2. After the secondary diode current reaches zero, the
primary winding inductance and the parasitic capacitor Cdss at
the MOSFET’s drain node begin to resonateŒ5; 6 . At this moment, the drain voltage of MOSFET (Vd .t// experiences a maximum value (Vline .t / C .Np /Ns /.VLED C Vf //, where VLED and
Vf are the output voltage of LEDs and the forward voltage of
the secondary-side diode, respectively. Vd .t/ resonates under
the dumped fashion, which can be described byŒ5
Vd .t/ D Vline .t/ C
Np
.VLED C Vf /e
Ns
˛t
cos.2fr t/;
(11)
where ˛ is the decay factor, fr is the resonance frequency, and
fr D 1=.2.Lp Cdss /1=2 /.
The auxiliary winding voltage Va .t/ also experiences a resonance and can be expressed by
Va .t/ D
Na
.VLED C Vf /e
Ns
˛t
cos.2fr t/:
(12)
For simplicity, ˛ can be set to zero. The delay-time between the zero-crossing point and the voltage valley is labeled
Td_v , with Td_v D .Lp Cdss /1=2 . Thus at t D Td_v , Vd .t/
and Va .t / experience minimum values, given by Vd_min D
Vline Np /Ns .VLED C Vf / and Va_min D Na /Ns .VLED C Vf /,
respectively.
The pin ZCD voltage (VZCD / decreases with decreasing
Va .t /. As VZCD falls to a certain value of VZCD_t , the drain voltage of M9 (Vd_M9 / goes down to trigger the fixed delay time
circuit. VZCD_t is determined by the current I3 , the W =L ratios
of M5–M9. The adjustable delay time Td_a can then be calculated by
Na
.VLED C Vf / cos.2fr Td_a /;
Ns
(13)
where I4 is the source current of M9.
When Vd_M9 is decreased to Vref1 , the comparator C1 outputs high, and the D flip–flop is triggered, letting Qn go low
and M10 shut down, and charging Ct through It . When the voltage across the capacitor Ct reaches Vref2 , the comparator C2
outputs low, letting the output of inverter INV go high and the
flip–flop SR1 output high, and turning on the MOSFET. So
Td_f D Ct Vref2 /It . The low output signal of C2 will reset the D
flip–flop, resulting in the turn-on of M10 and the discharging
of capacitor Ct .
In general, the inductance of primary winding is determined by the output power, and its value should decrease with
increasing output power to ensure the relative constant frequency of the switching cycleŒ1; 3; 7 . Td_v will decrease when
decreasing the primary inductance value. From Eq. (13), the
adjustable delay time Td_a will also decrease, causing the delay
time Td_on (Td_on D Td_a C Td_f / to decrease correspondingly.
Thus the turn-on of MOSFET is roughly synchronized at the
voltage valley.
VZCD_t
Rd C Ru
Rd
Ru I4 D
4.2. Resonant waveform comparison of the drivers with
traditional FDT and proposed ADT
While after the transformer demagnetization, if the traditional FDT is adopted, the turn-on of MOSFET may be far
away from the voltage valley point when adopting a primary
winding with different inductance value, resulting in higher
switching losses.
Resonance waveforms of Vd .t / after transformer demagnetization for the drivers with FDT and ADT are shown in
Fig. 3. A1 and B1 adopt ADT, while A2 and B2 adopt FDT.
The output power and voltage for A1 and A2 are 10 W and 25.6
V, while those for B1 and B2 are 20 W and 51 V, respectively.
Except for the primary inductance Lp , the other parameters
are the same: Vin D 220 V/50 Hz, the output current Io D
390 mA, Np : Ns : Na D 6.25 : 2.5 : 1, and the parasitic capacitor at drain node Cdss D 107 pF. Lp is selected to ensure a
relatively constant switching cycle. For A1 and A2 , Lp D 1.2
mH, thus Td_v D 1240 ns; for B1 and B2 , Lp D 0.6 mH, thus
Td_v D 800 ns.
For A1 and B1 , Td_f is designed to be 340 ns. According to
Eq. (13), Td_a for A1 and B1 is 900 ns and 480 ns, respectively.
So Td_on for A1 is 1240 ns, equals to the voltage valley delay
time Td_v . Td_on for B1 is 820 ns, having only 20 ns difference
between Td_on and Td_v .
However, for drivers A2 and B2 with FDT, this is not the
case. It is designed that A2 is to turn on at the voltage valley, thus for A2 , Td_on D Td_v D 1240 ns. But for B2 , since
Td_v D 800 ns, the MOSFET of B2 is to turn on with 440 ns
085008-4
J. Semicond. 2014, 35(8)
Nie Weidong et al.
Fig. 4. Photograph of the driving IC.
Fig. 3. Resonance waveforms of Vd .t / with (a) ADT and (b) FDT.
Fig. 5. Output current with different external resistor divider values.
Table 1. Key parameters of the prototype LED driver.
Parameter
Symbol
Value
MOSFET
650 V/2 A
Primary-side switch
Lp
0.6 mH
Primary inductance
Np : Ns : Na
6.25 : 2.5 : 1
Transformer turns ratio
Current sense resistor
Rsen
0.25 
Resistor divider
Ru : Rd
300 k : 30 k
Rst
280 k
Start-up resistor
Cext
1 F
Compensation capacitor
VIN capacitor
CVin
0.15 F
Diode
D1
D4-SMP
470 F/50 V
Output capacitor
Co
600 V/4 A
Output rectifier diode
Do
—
Transformer core
TR-EF015
later than the voltage valley point. From Eq. (11), Vd .t/ of the
MOSFET is 320 V at this moment, about 145 V higher than
the valley voltage (175 V). Therefore, compared with adopting FDT, the drivers adopting ADT can ensure the turn-on of
MOSFET roughly at the voltage valley when using a different
primary inductance.
5. Results and discussion
In order to evaluate the performance of the proposed control driver, an 18 W prototype is built and tested. The driving
IC has been implemented in a Korean Donbu HiTek’s 0.35 m
bipolar-CMOS-DMOS (BCD) process.
The die side with PAD is 1.63 1.07 mm2 . A photograph
of the implemented chip is shown in Fig. 4.
The specifications of the prototype are as follows: Vin D
85–265 V/50 Hz, Vo D 46 V, Io D 390 mA, the output protection voltage is 58 V, and the maximum switching frequency is
set to 120 kHz. The key parameters of this prototype are listed
in Table 1.
The line regulation with different values of external resistor divider is shown in Fig. 5. When Ru /Rd D 400 k/40 k,
the line regulation modification is inadequate, and the output current increases with increasing line input voltage. When
Ru /Rd D 200 k/20 k, it is overdone, and the output current
decreases with increasing input line voltage. When Ru /Rd D
300 k/30 k, it is appropriate, and the output current is in
the range of 389–393 mA over the universal input voltage.
The waveform of Vd .t/ at 220 V/50 Hz input voltage and
18 W output power is shown in Fig. 6. The delay time Td_on is
850 ns, while Td_v is 830 ns. There is only a 20 ns time error
between Td_on and Td_v , which agrees well with the theoretical
analysis above.
The measured efficiency and PF in the range of 85–265 V
are shown in Fig. 7. Results indicate that the proposed driver
can achieve an efficiency over 84% under the universal input
085008-5
J. Semicond. 2014, 35(8)
Nie Weidong et al.
Œ8; 9
drivers recently released
. The driver developed in this
work has a better compromise among the input voltage, PF,
line regulation, load regulation and efficiency.
6. Conclusion
A single-stage flyback AC-to-DC LED driver has been
developed. The driver operates in the BCM with an average
primary-side current estimation and a negative feedback network. A compensation voltage reflecting the input line voltage
is added to the ISEN pin, thus the error between the actual current and the estimated current can be compensated to zero. By
adopting a valley turn-on circuit with ADT, the turn-on of the
MOSFET remains roughly at the voltage valley when using
different primary inductance. The driving IC is implemented
in a 0.35 m BCD process and an 18 W LED driver prototype
is built and tested. A ˙0.5% line regulation, a PF higher than
0.97 and an average efficiency of 86.5% are achieved over the
universal input line voltage, which can be an effective solution
for LED illumination applications.
Fig. 6. Waveform of Vd .t/ (Vd : 100 V/div, time: 1 s/div).
References
Fig. 7. Measured efficiency and power factor.
Table 2. Performance summary and comparison.
Specification
Ref. [8]
Ref. [9]
This work
85–265
90–265
88–265
Input voltage (V)
13–22
8–19
7–12
Output power (W)
> 0:97
> 0:94
> 0:95
PF
˙0:5
˙2:94
˙0:8
Line regulation (% )
˙1:0
˙2:90
˙1:1
Load regulation (%)
87
86.5
Average efficiency (%) 81
This work
2012
2013
Released time
voltage, and the highest efficiency of 87.5% is measured at
180 V input voltage. The average efficiency is around 86.5%
for the entire input voltage range. Moreover, a high PF greater
than 0.97 can be achieved, meeting the relevant harmonic standards.
Table 2 shows the performance comparison of the proposed driver with some of the PSR single-stage flyback LED
[1] Li Y C, Chen C L. A novel single-stage high-power-factor ACto-DC LED driving circuit with leakage inductance energy recycling. IEEE Trans Industrial Electron, 2012, 59(2): 793
[2] Dai Guoding, Yu Feng, Wang Xuan, et al. Design and implementation of a high precision and wide range adjustable LED driver
controller. Journal of Semiconductors, 2010, 31(2): 025010
[3] Wang S, Ruan X, Yao K, et al. A flicker-free electrolytic
capacitor-less AC–DC LED driver. IEEE Trans Power Electron,
2012, 27(11): 4540
[4] Chou H H, Hwang Y S, Chen J J. An adaptive output current
estimation circuit for a primary-side controlled LED driver. IEEE
Trans Power Electron, 2013, 28(10): 4811
[5] Nie W D, Wu J, Yu Z G. A simple cost-effective PSR LED
driver without auxiliary winding. IEICE Electron Express, 2013,
10(23): 1
[6] Xie X G, Wang J, Zhao C, et al. A novel output current estimation
and regulation circuit for primary side controlled high power factor single-stage flyback LED driver. IEEE Trans Power Electron,
2012, 27(11): 4602
[7] Texas Instruments. Off-line primary side sensing controller
with PFC (TPS92314). [Online] Available: http://www.ti.com/
lit/ds/symlink/tps92314.pdf
[8] STMicroelectronics. 10W wide range high power factor isolated
LED driver using HVLED815PF800. [Online] Available: http: //
www.st.com / st-web-ui / static / active / en / resource / technical/
document/application_note/ DM00092673. pdf
[9] Fairchild Semiconductor. Fairchild reference design for
FL7732. [Online] Available: http://www.fairchildsemi.com/
support/referencedesign/docs/RD-L026.pdf
085008-6