Journal paper
Speed
Optimized
Diode-Triggered
SCR
(DTSCR) for RF ESD Protection of UltraSensitive IC Nodes in Advanced Technologies
Transactions on Device and Materials Reliability 2005 A novel diode‐triggered silicon‐controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low‐voltage application (signal and supply voltages ≤1.8 V) with extremely narrow ESD design margins. Trigger‐voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., fTmax = 45 GHz in BiCMOS 0.35µm LNA input) and thin gate oxides (e.g., tox = 1.7 nm in CMOS 0.09µm high‐speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger‐speed issues resulting in critical trigger‐voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n‐p‐n/p‐n‐p inherent to CMOS devices or can alternatively be implemented based on vertical high‐
speed SiGe HBT with adjacent p+ SCR anode.
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
Speed Optimized Diode-Triggered SCR (DTSCR)
for RF ESD Protection of Ultra-Sensitive
IC Nodes in Advanced Technologies
Markus P. J. Mergens, Christian C. Russ, Koen G. Verhaege, John Armer, Phillip C. Jozwiak,
Russell P. Mohn, Member, IEEE, Bart Keppens, and Cong Son Trinh
Abstract—A novel diode-triggered silicon-controlled rectifier
(DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD)
protection element is introduced for low-voltage application (signal and supply voltages ≤ 1.8 V) with extremely narrow ESD
design margins. Trigger-voltage engineering in conjunction with
fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction
bipolar transistor (HBT) base regions (e.g., fTmax = 45 GHz
in BiCMOS 0.35-µm LNA input) and thin gate oxides (e.g.,
tox = 1.7 nm in CMOS 0.09-µm high-speed input). Ultrathin
gate protection requires a reinforced trigger diode chain to avoid
SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device
model (CDM). SCR integration can be realized based on parasitic
n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent
p+ SCR anode.
Index Terms—BiCMOS, CMOS, electrostatic discharge (ESD),
gate-oxide protection, radio frequency (RF), SiGe heterojunction bipolar transistor (HBT), silicon-controlled rectifier (SCR),
trigger speed.
S
Fig. 1. Narrow ESD design-window application of ultrathin gate oxide
(tox = 1.7 nm) protection in CMOS 0.09-µm: TLP oxide breakdown characteristic (I–V and leakage) and typical supply voltage of VDD = 1.2 V.
Comparison to GGNMOS protection TLP I–V curve: Snapback trigger voltage
Vt1 and holding voltage Vhold are too close to the transient Gox breakdown
voltage.
Manuscript received January 13, 2004; revised November 24, 2004. This
paper is the expanded and modified version of a conference paper presented at
the IEDM, Washington, DC, 2003.
M. P. J. Mergens was with Sarnoff Europe, Gistel B-8470, Belgium.
He is now with Infineon Technologies, Munich D-81669, Germany (e-mail:
mmergens@onlinehome.de).
C. C. Russ was with the Sarnoff Corporation, Princeton, NJ 08543 USA. He
is now with Infineon Technologies, Munich D-81669, Germany.
K. G. Verhaege and B. Keppens are with Sarnoff Europe, Gistel B-8470,
Belgium.
J. Armer, P. C. Jozwiak, R. P. Mohn, and C. S. Trinh are with the Sarnoff
Corporation, Princeton, NJ 08543 USA.
Digital Object Identifier 10.1109/TDMR.2005.853510
Decisively, the superior voltage-clamping capabilities make
SCRs ideal protection alternatives in technologies, where the
so-called ESD design-window (refer to below) becomes very
narrow. Therefore, significant future relevance of these efficient
voltage clamps is anticipated in particular for sub-0.13-µm
CMOS applications.
Fig. 1 provides an example for narrow ESD design-window
application of protecting an ultrathin gate oxide (physical thickness tox = 1.7 nm) in a 0.09-µm CMOS technology. The plot
compares the transmission line pulse (TLP) I–V characteristic
(square pulse duration 100 ns, selectable rise time 200 ps,
2 ns, and 10 ns) of an unprotected NMOS gate oxide to a
conventional GGNMOS protection I–V curve. As indicated by
the leakage-current evolution of the stressed gate oxide, damage occurs at a transient breakdown voltage of approximately
BVox ∼ 5.4 V. The GGNMOS snapback trigger voltage comes
extremely close to this critical limit. Moreover, the relatively
high holding voltage does not provide any ESD design margin.
Therefore, applying such an NMOS device for thin-oxide
protection in this 0.09-µm CMOS and in more advanced
I. I NTRODUCTION
ILICON-CONTROLLED rectifiers (SCRs or thyristors)
have long been used as on-chip electrostatic discharge
(ESD) protection elements over a broad range of technologies
because of their superior ESD-protection capabilities [1]–[7].
With SCRs, an extremely high failure current, low dynamic on
resistance, and an ideal ESD performance width scaling can be
accomplished. This is a result of the regenerative conduction
mechanism due to double minority carrier injection into both
wells leading to the low-resistive latch-up operation. The excellent high current behavior of SCRs can typically provide an area
gain factor of 4 to 5 over standard silicide-blocked groundedgate NMOS (GGNMOS) ESD-protection elements.
1530-4388/$20.00 © 2005 IEEE
MERGENS et al.: SPEED OPTIMIZED DTSCR FOR RF ESD PROTECTION OF ULTRA-SENSITIVE IC NODES
Fig. 2. TLP NMOS gate-oxide breakdown and GGNMOS snapback parameters (trigger voltage Vt1 and holding voltage Vhold ) as a function of physical gate-oxide thickness in different CMOS technologies (0.18–0.065 µm).
Technology advancement results in a dramatic shrink of the ESD designwindow.
technologies becomes dangerous. Moreover, for radio frequency (RF) design, the requirement for efficient ESD voltage
clamps is even more challenging. Here, a local GGNMOS
protection approach cannot be used due to the high parasitic
junction capacitance (order of magnitude of several picofarads)
being introduced to the RF pin. Such a high ESD capacitance
would largely compromise high-speed performance. Therefore,
in conjunction with NMOS-type clamps, RF ESD implementations require ESD diodes to be locally connected to the
capacitance-sensitive pins (e.g., in the “dual-diode” protection
approach) to minimize the parasitic junction capacitance. However, for worst case ESD stress conditions on the integrated
circuit (IC) level, this implies that there is always a diode
voltage drop in addition to the protection clamp in the ESD
discharge path. Fig. 1 demonstrated how this additional diode
voltage drop would further minimize the ESD design margins
by pushing the total I–V curve of the protection solution outside the ESD design-window. In conclusion, the application
of the conventional GGNMOS protection approach becomes
extremely critical if not impossible for ESD-protection design
of RF inputs containing ultrathin gate oxides in sub-130-nm
CMOS technologies. This general behavior is corroborated in
Fig. 2, which depicts the general trend of shrinking gate oxides
with CMOS technology advancement. The plot compares the
transient NMOS oxide breakdown voltage to the scaling behavior of the corresponding GGNMOS ESD parameters (Vt1 ,
Vhold ) as a function of the oxide thickness for a number
of advanced technologies (0.18–0.065 µm). Apparently, the
ESD susceptibility of the gate oxide is increasing at a rapid
pace as technologies advance to thinner gate oxides resulting
in a dramatic shrinking of the design-window. On the other
hand, the corresponding GGNMOS clamping capabilities do
not improve to the same degree. As a result, the trigger
and holding voltage eventually exceed the dynamic breakdown voltage of the ultrathin gate oxides, thus, disabling the
protection type.
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Fig. 3. Narrow ESD design-window application of SiGe HBT input protection
in BiCMOS 0.35 µm: BE breakdown characteristic (I–V and leakage) and
typical input voltage of Vin = 1.0 V. Comparison to GGNMOS protection
TLP I–V curve: Snapback trigger Vt1 and holding voltages Vhold are outside
the ESD design-window.
The dramatic implications on high-speed input–output (I/O)
driver design in the (low-voltage) thin-oxide domain becomes
evident: the common concept of self-protecting MOS drivers
in I/Os does not work anymore due to input oxide damage.
Salman et al. reported the same behavior for a CMOS 0.1-µm
technology [8].
Except for applying SCRs for ultrathin gate-oxide input
protection in CMOS technologies, these devices can also be
used in bipolar or BiCMOS technologies to protect the sensitive HBT base–emitter (BE) junctions, cf. Fig. 3. Particularly, if stressed in forward mode, the inherent BE diode
fails at low clamp voltages (here approximately 6 V). In this
case, TLP experiments were conducted for a relatively large
HBT cell resulting in a fairly high HBT failure current. For
other RF applications, the HBT size can be up to a factor
of 4 smaller with a low failure current of approximately
0.3 A. In accordance to the thin gate-oxide situation described
above, n-p-n bipolar-based protection (e.g., GGNMOS) cannot
provide sufficient voltage clamping to keep the HBT safe.
This is clearly demonstrated by the GGNMOS TLP I–V curve,
which is entirely situated outside the HBT ESD design-window,
i.e., in the HBT damage regime.
In conclusion, for presently applied product technologies and
for future aggressive technology scaling, conventional bipolarbased protection (e.g., parasitic n-p-n on GGNMOS) does not
work anymore for many ultrasensitive IC nodes due to insufficient voltage clamping.
SCRs are a viable solution alternative to conventional ESD
elements due to their excellent voltage-clamping capabilities
and ESD performance per area. Moreover, the parasitic junction
capacitance per ESD is an order of magnitude lower compared
to NMOS transistors making SCRs suitable candidates for local
RF I/O protection. Note that the junction capacitance roughly
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
Fig. 4. (a) G1 -triggered DTSCR forward biasing SCR G1 –cathode junction. Rsub indicates intrinsic p-well connection to the substrate. (b/c) G2 -triggered
DTSCR forward biasing to G2 –anode junction. (c) Holding diode in series with SCR for normal operation latch-up immunity replaces one trigger diode.
equals a diode capacitance (e.g., in CMOS, a p+/n-well), which
can be reliably estimated by using simulation program with
integrated circuits emphasis (SPICE) parameters and junction
geometry parameters.
To customize latch-up elements for ESD design in leadingedge technologies, one has to overcome a number of design
challenges. SCR-device engineering techniques and SCR ICprotection application are the topics of this paper, covered in
the following sections.
1) Section II-A: SCR trigger-voltage engineering for narrow ESD design-window applications in advanced technologies: diode-chain-triggered SCR (DTSCR) including
various trigger schemes, which allow SCR turn-on well
below the critical voltage limit of IC damage.
2) Section II-B: SCR holding-voltage engineering for latchup immunity: avoid unintended SCR triggering during
normal IC operation.
3) Sections II-C and II-D: DTSCR implementation techniques in advanced CMOS/BiCMOS (SiGe HBT)
technologies.
4) Section III-A: DTSCR IC application example in
0.35-µm BiCMOS: sensitive SiGe HBT base protection,
cf. design-window in Fig. 3.
5) Section III-B: DTSCR IC application example in
0.09-µm CMOS for ultrathin gate-oxides protection, cf.
design-window in Fig. 1. DTSCR trigger-speed enhancement is required for fast ESD transients as produced by
the charged device model (CDM).
II. DTSCR P ROTECTION D ESIGN
A. SCR ESD Trigger-Voltage Engineering
The DTSCR employs an external trigger diode chain to latch
the device during ESD stress conditions as soon as the diode
string injects enough current into the SCR gates (or “trigger
taps”) G1 or G2 , cf. Fig. 4. Triggering can either be accomplished by forward biasing the inherent SCR G1 –cathode junction, cf. Fig. 4(a), or alternatively the G2 –anode diode, cf.
Fig. 5. DTSCR Vt1 engineering: TLP I–V characteristic of DTSCR
(CMOS-SCR, see Section III-B) for three G1 trigger diode schemes: Vt1 ≈
(n + 1) · 0.8 V (n trigger diodes + intrinsic SCR G1 /Cdiode).
Fig. 4(b), or both simultaneously. There is an important design
tradeoff for the number of trigger diodes n required for leakage
limitation during normal operation conditions (maximize n)
and ESD trigger-voltage reduction (minimize n). For IC normal
operation, the number of trigger diodes (n) must be sufficiently
high such that the chain does neither leak nor trigger the SCR.
Conversely, the SCR ESD trigger voltage increases with n.
A reasonable design compromise can be achieved for lowvoltage applications where the supply or signal voltage does not
exceed 1.8 V.
For CMOS-based SCRs, see Section II-C, G2 -triggered devices bear the advantage that the SCR G2 (n-well)–anode diode
can be exploited as a trigger diode within the diode chain
due to the isolation of the parasitic n-well diode from a common p-substrate. In contrast, in G1 (p-well)-triggered elements,
the diode chain sees an intrinsic p-well–substrate connection,
which bypasses the G1 (p-well)–cathode diode as indicated
MERGENS et al.: SPEED OPTIMIZED DTSCR FOR RF ESD PROTECTION OF ULTRA-SENSITIVE IC NODES
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Fig. 6. DTSCR latch-up engineering: TLP I–V characteristic of a G2 -triggered DTSCR (CMOS-SCR) for 1.8-V application with six trigger diodes and no
holding diode compared to five trigger diodes plus one holding diode. Result: Approximately 1-V difference in holding voltage, approximately same Vt1 , but
higher It2 with series diode due to parasitic Darlington current into substrate.
by Rsub in Fig. 3(a). Therefore, the G1 trigger configuration
requires one trigger diode more than G2 triggering to satisfy
normal operation leakage requirements. In other words, G2 triggering allows for the same DTSCR normal operation leakage,
while using one trigger diode less (substituted by the inherent
anode–G2 diode) as compared to G1 triggering. Consequently,
for a predefined leakage specification, G2 -triggered SCRs can
be activated by a one-diode-voltage-drop (∼ 0.8 V) lower
trigger voltage.
Fig. 5 illustrates the Vt1 engineering technique by showing
TLP I–V characteristics of various DTSCRs with different
trigger diode chains. In this example, a lateral SCR is incorporated based on CMOS layers as will be explained in
Section II-C.
B. Holding-Voltage Engineering for
Latch-Up Immunity
To ensure latch-up immunity during normal operation for
VDD higher than the SCR holding voltage (e.g., if the DTSCR
is used as a 1.8-V supply clamp), a series diode is needed to
increase Vhold above VDD [1], cf. Fig. 4(c). This holding diode
can also become part of the trigger chain in a G2 -triggered
element, replacing one trigger diode.
Fig. 6 shows the I–V characteristics of two G2 -triggered
SCRs demonstrating a holding-voltage shift by approximately
1 V with a p+/n-well series diode. Thus, the design is latchup immune for VDD = 1.8 V. Furthermore, the substitution
of a trigger diode by a holding diode does not alter the trigger
voltage Vt1 . Surprisingly, a slightly reduced dynamic on resistance as well as a higher failure current can be observed for the
SCR containing a holding diode. These effects can be attributed
to the parasitic vertical p-n-p of the p+/n-well diode chain
forming a Darlington p-n-p in conjunction with the anode/
n-well junction of the SCR as shown in the schematic in Fig. 6.
Overall, this parasitic creates an additional ESD current path to
GND in parallel to the SCR, thus enhancing the overall ESD
failure current It2 .
Fig. 7. Cross section and schematic layout of a CMOS-based SCR (not
shown: External diode-trigger chain, which can be connected to G1 , or G2 ,
or G1 and G2 ). The local G1 /G2 trigger taps can be inserted between the
interrupted cathode/anode diffusions, respectively [1]. In the DTSCR, a diode
chain is applied to bias the wells through the gates G1 /G2 .
C. SCR Integration in CMOS
Conventional CMOS design integrates lateral SCR n-p-n-p
structures using an adjacent p-well containing an n+ cathode
and an n-well containing a p+ anode, respectively [2]. A
schematic example layout and a cross section of the SCR kernel
including gate/trigger tap implementation (G1 : p+ in p-well;
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Fig. 8. Cross section and schematic layout of SiGe-HBT-based SCR (not shown: external diode-trigger chain, which can be connected to G1 , or G2 , or G1 and
G2 ). The symmetrical SCR device is formed by a vertical n-p-n HBT (emitter/SiGe-base/n-epi) in conjunction with a distributed lateral p-n-p bipolar (anode/
n-epi/SiGe-base). Note: alternatively, the same intermittent trigger taps as shown in Fig. 4 could be used, replacing the solid G1 /G2 stripes.
G2 : n+ in n-well) are depicted in Fig. 7. Separating the external
trigger element from the SCR allows the optimizing of the SCR
independently regarding trigger speed and high current capabilities. For example, allowing for minimum anode–cathode
spacing results in minimum turn-on time due to smallest bipolar
junction transistor (BJT) base lengths composing the SCR.
D. SCR Integration With SiGe HBTs
The schematic layout and cross section of an SiGe-HBTbased SCR are shown in Fig. 8. Due to the vertical current flow
from the SiGe HBT emitter to collector, the SCR will benefit
from the high currents that can flow in a vertical bipolar structure in contrast to a predominantly lateral bipolar conduction in
a lateral SCR (e.g., in CMOS). As demonstrated in Fig. 9, the
ESD performance in terms of maximum current It2 and human
body model (HBM) level drastically increases inserting more
contact rows in the anode and cathode, respectively, due to the
reinforced vertical junction area.
Furthermore, the SCR holding voltage is relatively small
(Vhold ∼ 1.0 V) as compared to regular CMOS implementations reflecting the high transistor current gain of the vertical
SiGe HBT part of the SCR. In addition, the thin SiGe base,
as well as graded doping concentration, makes this SCR a
relatively fast device.
Another interesting benefit of the described SiGe HBT-SCR
is the fact that the SCR is fully isolated from the substrate. As a
result, the gate G1 can be treated the same way as gate G2 (see
discussion above: G1 trigger versus G2 trigger). This allows
simultaneous G1 /G2 triggering with identical diode chains on
both gates. As shown in [10], dual-gate injection enhances the
SCR speed and thus helps to avoid transient trigger-voltage
overshoots during the device turn-on time. See discussion in
Section III-B.
Moreover, due to the complete device isolation from the
substrate, these DTSCRs can also be applied as local protection
elements between I/O and VDD. A further benefit is the high
latch-up immunity of the device induced by substrate current
injection.
III. DTSCR RF ESD-P ROTECTION A PPLICATION
A. Input SiGe HBT Base in BiCMOS 0.35 µm
SiGe HBT ( fTmax = 45 GHz) emitter–base protection applying the conventional dual-diode protection approach in conjunction with a GGNMOS or for example, an NMOS-triggered
SCR power clamp is ineffective due to the low BE failure
voltage (∼ 6 V), as illustrated in the ESD design-window in
Fig. 3. Moreover, a direct local-diode chain protection between
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537
Fig. 9. HBT-based DTSCR (W = 2 × 50 µm; two-sided) TLP I–V for three different variations of number of contact rows in anode and cathode, respectively.
The performance boost with larger number of contact rows reflects the predominant vertical current flow in HBT-based SCRs.
Fig. 10. Bipolar LNA circuit including local DTSCR protection of sensitive HBT BE diode in conjunction with application of capacitance-reduction scheme for
the anode by reverse biasing the p+/n-well junction. ESD-protection scheme meets the RF capacitance spec at each pin (voltage-dependent capacitance C(V )
values calculated by SPICE parameters). All pin combinations exceed ESD spec of 2 kV-HBM and 200 V-MM spec (latter corresponds to approx 4 kV-HBM).
Input and VEE (for both pins, a capacitance spec is defined)
is not possible either, since a too-high capacitance of the
forward-biased diode would compromise the RF performance.
Introducing a diode chain between IN and GND in an input
configuration, as shown in Fig. 10, would violate the ESD
design-window: for worst case stress between IN and VEE,
four width-limited RF diodes (three between IN and GND
plus one between GND and VEE) with relatively high series
resistance would compete with the parasitic HBT BE diode in
forward conduction. This would result in HBT failure below the
ESD spec.
Local DTSCR protection, as shown in Fig. 10, succeeds
for three reasons. 1) By applying three small trigger diodes
in series, the SCR Vt1 can be reduced sufficiently below the
critical HBT failure voltage at 6 V with an acceptably lowinput leakage during normal RF operation. 2) The SCR clamps
the IN–VEE voltage below the HBT damage level, thus enabling a challenging 200 V-MM spec (roughly corresponds to
4 kV-HBM in this technology). 3) To meet the specific input RF
capacitance requirement CIN < 120 fF, the SCR-n-well can be
pulled high to VCC through G2 , thus, reverse biasing the SCR
anode–n-well junction and minimizing the parasitic capacitance
of the anode at IN. This capacitance reduction scheme is the
reason for using the G1 trigger scheme in the local DTSCR
clamp rather than the otherwise preferred G2 trigger (cf.
Section II-A).
The TLP characteristic in Fig. 11 corroborates the functionality of the DTSCR structure, revealing the following I–V
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
Fig. 11. LNA TLP I–V characteristic: Worst case stress (positive on Input versus VEE on ground) protected by local DTSCR, cf. Fig. 1. The DTSCR triggers
and clamps the voltage below HBT BE damage. The ESD spec of 2 kV-HBM and 200 V-MM is achieved within the RF capacitance constraints.
Fig. 12. CMOS 0.09-µm: TLP I–V characteristic of DTSCR including a parallel gate oxide (tox = 1.7 nm) monitor to emulate IC input protection. The thin
Gox can be successfully protected.
regimes: HBT BE diode conduction, DTSCR triggering, joined
HBT/DTSCR conduction (see inset including ESD current path
for most critical stress case), HBT failure occurs after the input
voltage exceeds the critical HBT failure voltage limit of 6 V
at an ESD current of 2.2 A. This HBT RF input design passed
ESD product qualification tests of 2 kV-HBM and 200 V-MM.
B. Input Ultrathin Gox in CMOS 0.09 µm
Fig. 12 depicts the TLP I–V characteristics of two DTSCRs
in a G1 - and G2 -triggered configuration, respectively. Both
structures have the thinnest NMOS gate oxide (tox = 1.7 nm)
as a protection monitor in parallel to emulate an RF IC input
configuration, as seen in Fig. 12. Note that the G2 trigger
scheme essentially results in the same leakage current as compared to the G1 -triggered SCR. However, the G2 -triggered SCR
reveals a lower trigger voltage Vt1 , since one trigger diode
less can be used as explained in Section II-A. The leakage
increase at It2 indicates that the gate oxide fails within the
higher resistive roll-off regime of the SCR I–V curve. The
physical mechanism of this I–V roll-off in SCRs is in detail
explained in [2]. This means that almost the intrinsic failure current of the stand-alone SCR is reached, which proves
that the DTSCR can successfully protect an ultrathin input
gate oxide. Moreover, the margin of Vt1 and the clamping
voltage with regard to transient BVox provides ESD design
flexibility for protection integration on the IC level. As outlined in the introduction, additional ESD voltage drops across
MERGENS et al.: SPEED OPTIMIZED DTSCR FOR RF ESD PROTECTION OF ULTRA-SENSITIVE IC NODES
539
Fig. 13. CMOS 0.09-µm: Fast TLP rise time (TR) experiments for DTSCR
including holding diode and parallel gate-oxide monitor: for fast TR = 200 ps,
the transient voltage overshoot damages the gate oxide in parallel to the DTSCR
due to a too-slow protection response time as qualitatively shown in Fig. 14.
Fig. 15. TLP I–V characteristic of DTSCR containing reinforced G2 trigger
diodes and G2 trigger taps. The trigger voltage is reduced by approximately
0.7 V as compared to conventional DTSCR in Fig. 12. The device normal
operation leakage is not affected by the larger trigger diodes.
Fig. 14. Qualitative SCR TLP voltage pulses comparing slow TLP rise times
(e.g., TR = 10 ns) versus fast TLP rise time (e.g., TR = 200 ps). For fast
transient TR trigger voltage, overshoots may result in ultrathin oxide damage
as experimentally confirmed in Fig. 13.
lenge of SCRs protecting thin gate oxides constitutes the
relatively slow trigger speed [9], as compared to (parasitic)
bipolar elements. The physical reason for the slower speed is
that SCRs are composed of interlinked n-p-n and p-n-p bipolar,
which both need to be turned on to start the regenerative
ESD latch-up operation resulting in high current conduction
and effective voltage clamping due to conductivity modulation.
Therefore, for ultrafast ESD transients such as CDM, the SCR
response time can be too slow to clamp the voltage sufficiently
fast below the damage voltage of the node to be protected.
The resulting transient trigger-voltage overshoots can be particularly dangerous if ESD voltage stress is directly exposed
to an ultrathin gate oxide as, for instance, that present for RF
inputs or so-called decoupling capacitors between supply and
ground in IC RF domains. These elements act as alternating
current (AC) “shorts” to filter out supply noise and are frequently formed by thin gate-oxide capacitors for area reasons.
During ESD stress, the voltage drop across the power clamp
will also be fully seen across such a sensitive gate oxide. To
worsen the situation for the case of a 1.2-V supply, the DTSCR
power clamp requires a series diode for latch-up immunity.
The above-described trigger-speed issue is demonstrated in
Fig. 13 for a conventional DTSCR power clamp. For slow
TLP rise times (TR = 10 ns), the DTSCR successfully protects
the ultrathin gate oxide (e.g., decoupling capacitor) in parallel
in accordance to data in Fig. 12. However, for fast TLP rise
times of TR = 200 ps, the increase of leakage current at a
largely diminished TLP amplitude indicates premature gateoxide damage. Fig. 14 explains qualitatively the observed behavior comparing two schematic TLP voltage pulses. For slow
transients, the trigger-voltage overshoot due to the finite SCR
response time is still situated below the transient oxide damage
level according to the good performance level shown in Fig. 13.
However, significantly increasing the TLP slew rate dV /dt
for TR = 200 ps, the SCR cannot react in time to clamp the
diodes and bus resistance need to be tolerated for efficient RF
ESD design.
The relevant device parameters extracted from the TLP
I–V characteristics (trigger voltage Vt1 , holding voltage Vhold ,
dynamic on resistance Ron , failure current It2 , permissible
maximum device current Imax ) are indicated in the plot. Imax
represents the maximum current level, which must not be
exceeded during ESD stress conditions to allow for efficient
voltage clamping. Applying DTSCR protection in an IC product, the decisive SCR parameters (Imax ∝ W , Ron ∝ 1/W )
can be scaled linearly according to the ESD specification to stay
in the quasi-linear regime of the I–V characteristics and avoid
the higher resistive roll-off region.
DTSCR Trigger-Speed Engineering for Thin Gate Oxides
Under Very Fast ESD Transients: A well-known design chal-
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Fig. 16. TLP I–V characteristic for TR = 200 ps: reinforced DTSCR with and without holding diode and parallel thin gate-oxide monitor (decoupling cap).
The gate oxide can be successfully protected.
voltage transient below the oxide damage level. The transient
trigger peak temporarily exceeds the Gox damage voltage, cf.
Fig. 13, whereas the quasi-static TLP clamping behavior does
not reveal the issue. This slow response time, as indicated by
the TLP analysis, can also limit the CDM protection level on
product chips.
The objective of the DTSCR trigger enhancement is to reduce the transient trigger overshoot during fast ESD transients.
The SCR nucleus itself integrated within the DTSCR is already
optimized regarding speed by minimizing the anode–cathode
spacing. The answer to the problem is to integrate a fast
and sufficiently strong parallel ESD back-up path, which is
activated during the relatively long SCR turn-on time.
An important option with a diode-trigger chain, apart from
low-voltage SCR triggering is that the diode chain can serve as
the ESD trigger backup path for the slower SCR by clipping
possible transient trigger-voltage overshoots. Careful design
of the trigger diodes (width, spacings) and trigger-current injection points (SCR gates G1 or G2 ) is required to form a
sufficiently strong initial ESD current path through the diodes
reducing the initial voltage peak. To understand that an optimized diode chain can protect during the first nanoseconds,
it is important to consider two additional points. First, the
transient oxide breakdown within the first nanoseconds of an
ESD pulse is significantly higher than the 100-ns TLP value
of BVox = 5.2 V shown in Fig. 1. A rough estimation for the
CDM relevant time domain gives an order of magnitude of 1.5
higher breakdown values [11], i.e., BVox (ns) ∼ 8 V. Secondly,
the increased diode width also results in a smaller voltage drop
per diode at the triggering point. At the low trigger-current
level, the diode n-well is not conductivity modulated yet, such
that the diode resistance is still significantly high and width
scaling has an impact on the voltage drop per diode and thus
on Vt1 . As shown in Fig. 15, the DTSCR starts to latch at 2.7 V,
meaning that the reinforced diodes start to conduct at this voltage level. On a CDM-related time scale, the diode chain needs
to clip the voltage below roughly BVox (ns) ∼ 8 V before the
SCR can start to clamp the voltage to safe levels for the majority
of the pulse duration. The TLP data for TR = 200 ps in Fig. 16
indicates that this objective is accomplished for the reinforced
local DTSCR clamp (no Vhold diode) as well as DTSCR power
clamp (one Vhold diode). Both these test devices contain an
ultrathin gate oxide in parallel and successfully protect this
element. Note that the dV /dt effect for TR = 200 ps appears
to further reduce the triggering voltage as compared to Fig. 15,
which will further support fast turn-on. As can be seen for
the DTSCR power-clamp with series Vhold diode, the TLP
performance is reduced by roughly 1 A due to the additional
voltage drop. The good TLP performance of roughly 2.8 A for
this test element was confirmed by HBM tests with a 3.5-kV
pass and 3.7-kV fail level. The DTSCR was also applied as
a power clamp in the RF domain of product chips containing
sensitive ultrathin Gox decoupling capacitors for supply. CDM
product specifications of 500 V were met for all products.
IV. C ONCLUSION
This paper demonstrates that bipolar-based ESD elements,
e.g., parasitic lateral n-p-n in GGNMOS, are not suitable anymore to protect sensitive nodes such as ultrathin gate oxides in
advanced sub-130-nm CMOS technologies. This is due to insufficient high-current clamping capabilities. As demonstrated,
SCRs represent excellent solutions if the trigger voltage is
appropriately engineered to fit into an extremely narrow ESD
design-window. A novel DTSCR for low-voltage application
(signal and supply voltages ≤ 1.8 V) is introduced including
different diode-trigger schemes, which allow for SCR triggervoltage reduction sufficiently below the critical voltage levels.
Moreover, engineering of normal operation latch-up immunity
for DTSCR power-clamp application is discussed within the
context of the specific diode-trigger scheme. As demonstrated,
due to a relatively slow SCR trigger speed, dangerous voltage
MERGENS et al.: SPEED OPTIMIZED DTSCR FOR RF ESD PROTECTION OF ULTRA-SENSITIVE IC NODES
overshoots may jeopardize ultrathin gates during very fast ESD
transients such as CDM. A novel concept of applying an optimized SCR trigger backup in parallel to the SCR allows coping
with this speed issue. Here, the provided backup current path
can be integrated into the DTSCR by exploiting a reinforced,
thus low-resistive, trigger diode chain, which would clip initial
fast voltage transients and results in a reduced DTSCR trigger
voltage. DTSCR integration can be based on lateral parasitic
BJTs in CMOS technologies as well as on vertical high-speed
SiGe HBTs. Moreover, two IC product application examples
are described: protection of an SiGe HBT emitter–base junction
(advanced BiCMOS) and ultrathin gate oxide (sub-0.13-µm
CMOS).
R EFERENCES
[1] M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn,
B. Keppens, and S. Trinh, “Diode-triggered SCR (DTSCR) for RF-ESD
protection of BiCMOS SiGe HBTs and CMOS ultrathin gate oxides,” in
IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Washington, DC,
2003, pp. 21.3.1–21.3.4.
[2] C. Russ, M. Mergens, K. Verhaege, J. Armer, P. Jozwiak, G. Kolluri, and
L. Avery, “GGSCRs: GGNMOS triggered silicon controlled rectifiers for
ESD protection in deep sub-micron CMOS processes,” in Proc. Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symp., Portland, OR,
2001, p. 22.
[3] L. R. Avery, “Using SCRs as transient protection structures in integrated circuits,” in Proc. Electrical Overstress/Electrostatic Discharge
(EOS/ESD) Symp., Las Vegas, NV, 1983, p. 177.
[4] A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip
ESD protection at output and input pads,” IEEE Electron Device Lett.,
vol. 12, no. 1, pp. 21–22, Jan. 1991.
[5] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits.
New York: Wiley, 1995.
[6] C. Diaz and G. Motley, “Bi-modal triggering for LVSCR ESD protection devices,” in Proc. Electrical Overstress/Electrostatic Discharge
(EOS/ESD) Symp., Las Vegas, NV, 1994, p. 106.
[7] M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, and R. Mohn,
“High holding current SCRs (HHI-SCR) for ESD protection and latchup immune IC operation,” in Proc. Electrical Overstress/Electrostatic
Discharge (EOS/ESD) Symp., Charlotte, NC, 2002, p. 73.
[8] A. Salman, R. Gauthier, C. Putnam, P. Riess, M. Muhammad, M.
Woo, and D. Ioannou, “ESD-induced oxide breakdown on self-protecting
GG-nMOSFET in 0.1-µm CMOS technology,” IEEE Trans. Device
Mater. Reliab., vol. 3, no. 3, pp. 79–84, Sep. 2003.
[9] J. Wu, P. Juliano, and E. Rosenbaum, “Breakdown and latent damage
of ultrathin gate oxides under ESD stress conditions,” in Proc. Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symp., Anaheim, CA,
2000, p. 287.
[10] K.-C. Hsu and M.-D. Ker, “SCR device with double-triggered for on-chip
ESD protection in sub-quarter-micron silicided CMOS processes,” IEEE
Trans. Device Mater. Reliab., vol. 3, no. 3, pp. 58–68, Sep. 2003.
[11] H. Gieser and M. Haunschild, “Very-fast transmission line pulsing of
integrated structures and the charged device model,” in Proc. Electrical
Overstress/Electrostatic Discharge (EOS/ESD) Symp., Lake Buena Vista,
FL, 1996, pp. 85–94.
Markus P. J. Mergens received the degree in
physics in 1996 from the Technical University of
Aachen (RWTH), Germany. In 2001, he received
the Ph.D. degree in electrical engineering from the
Swiss Federal Institute of Technology, ETH, Zurich,
for his work conducted at the Robert Bosch GmbH,
Germany.
In 2000, he joined Sarnoff Corporation in Princeton, NJ, where he was the Project Manager responsible for electrostatic discharge (ESD)/input–output
(I–O) product design programs with Japanese and
US customers. He transferred to Sarnoff Europe, Belgium, in 2003. Since
February 2005, he has been with Infineon Technologies in Munich, Germany,
as a Manager of ESD Engineering in the automotive and industrial product area.
541
He has around 10 patents and authored/coauthored more than 20 articles in the
field of ESD protection design and simulation.
Dr. Mergens received the Best Presentation Award for a presentation at the
EOS/ESD Symposium in 2001. Since 2001, he has been an active contributor to
the EOS/ESD Symposium’s TPC while supporting ISCAS and IRPS ESD/LU
subcommittees as well.
Christian C. Russ received the M.S. and Ph.D.
degrees in electrical engineering from the Technical
University of Munich (TUM), Germany, in 1991
and 1999, respectively. His Ph.D. thesis was entitled
“ESD-Protection Devices for CMOS Technologies:
Processing Impact, Modeling, and Testing Issues.”
He worked at the TUM on modeling of ESD
phenomena and pulse-measurement techniques from
1991 to 1994, and was with the R&D Laboratory
IMEC, Leuven, Belgium, on a fellowship from the
European Community for research on ESD and reliability issues in CMOS technologies from 1994 to 1998. From 1998 to
2003, he worked for Sarnoff Corporation, Princeton, NJ, on the creation of
innovative on-chip ESD protection and was responsible for ESD technology
transfer and licensing programs. In 2003, he moved back to Munich, joining
Infineon Technologies as a Senior Staff Engineer involved in the development
of ESD-protection concepts for deep submicrometer CMOS (down to the
32-nm node) and bipolar processes. He has published over 30 conference and
journal publications and has been awarded over 10 patents in his field with
others pending.
Dr. Russ was a recipient or corecipient of several Best Paper/Best Poster/Best
Presentation Awards at the ESREF Conference (1993, 1995) and at the
EOS/ESD Symposia (1993, 1996, 1998, 2000, and 2001). He is a member of
the ESD Association, where he is active in the EOS/ESD Symposia. He was
also the Chairman of the Technical Program Committee in 2003, as well as a
session moderator and workshop panelist.
Koen G. Verhaege received the M.Sc. degree in electrical and mechanical
engineering from the University of Leuven, Belgium, in 1991.
He is currently leading Sarnoff Europe BVBA, Belgium, a company fully
focused on value-added silicon IC design solutions intellectual property:
innovation, transfer and licensing, and a subsidiary of Sarnoff Corporation
(Princeton, NJ). He has authored about 20 peer-reviewed published articles
in the field of on-chip ESD protection and testing and holds several ESDprotection design patents.
John Armer is a Member of the Technical Staff at Sarnoff Corporation,
Princeton, NJ. He joined Sarnoff Corporation (formerly, RCA David Sarnoff
Research Center) in 1979. Since then, he has been involved in a variety of
analog and mixed signal IC design projects utilizing both custom and languagebased design methodologies. While continuing to be actively involved in those
activities, he became a member of the ESD device design team in 1999 where
he focuses on practical implementations of ESD-protection structures in mixed
signal ICs. He is a coauthor of four papers on ESD, three papers in the field of
video processing, and currently has four U.S. patents with several pending.
Phillip C. Jozwiak received the degree in physics from Maria CurieSclodowska University, Lublin, Poland, and the M.S. degree in physics from
Rutgers University, New Brunswick, NJ.
From 1978 to 1980, he worked at BMI Textron, FL, on automation of
sputtering systems and development of thin film coatings for photomasks. In
1980, he joined the RCA Solid State Division, Florida, where he was engaged
in all phases of processing for very large scale integration (VLSI) fabrication.
In 1981, he transferred to RCA Research Laboratories (currently Sarnoff
Corporation) in Princeton, NJ, where he has worked on the development of new
processes for hybrid Microwave Circuits and GaAs metal-semiconductor fieldeffect transistors (MESFETs) monolithic microwave integrated circuit (MMIC)
technologies. He is currently an Associate Member of the Technical Staff at
Sarnoff Corporation. His work also involves testing, measurement analysis and
layout of the ESD-protection structures and I/O pads. He holds five U.S. patents
and is a coauthor of several technical papers. Presently, his interests are the
development of on-chip ESD-protection devices for new and emerging CMOS
technologies.
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005
Russell P. Mohn (M’01) received the B.E. degree in electrical engineering from
the Cooper Union for the Advancement of Science and Art, Cooper Square, NY,
in 2001.
At the Cooper Union for the Advancement of Science and Art, he focused
on signal processing, multiresolution analysis, and artificial neural networks.
At Sarnoff Corporation, Princeton, NJ, he has contributed in the areas of mixed
signal circuit design and the design of on-chip devices that protect against ESD.
Bart Keppens received the I.E. degree in electronics from the Polytechnical
School Groep T, Leuven, Belgium, in 1996.
In 1996, he joined IMEC and was responsible for device electrical characterization, support for the ESD group and support for the Non Volatile
Memories group. Since May 2002, he has been with Sarnoff Europe, Belgium,
solving ESD-related problems for customers worldwide and is now Director
for Technical Operations at Sarnoff Europe. In 2001 and 2002, he acted as a
Workshop Panelist on TLP during the EOS/ESD Symposium.
His master thesis, together with colleague S. Servaes, “Transmission Line
Pulsing (TLP) technique for analyzing ESD reliability,” performed at IMEC,
Leuven, Belgium, received the BARCO award for best Industrial Engineer
thesis in 1996.
Cong Son Trinh received the M.S. degree in software programming from the
High Institute of Applied Microelectronics (ISMEA), Marseille, France.
From 2000 to 2002, he was responsible for ESD-protection development at
ALCATEL Microelectronics, Oudenaarde, Belgium. Then he joined Sarnoff
Europe, Gistel, Belgium, as a Member of the Technical Staff and shortly
thereafter, Sarnoff Corporation, Princeton, NJ, where he is responsible for
ESD/I–O design programs for customers worldwide.
About Sofics
Sofics (www.sofics.com) is the world leader in on‐chip ESD protection. Its patented technology is proven in more than a thousand IC designs across all major foundries and process nodes. IC companies of all sizes rely on Sofics for off‐
the‐shelf or custom‐crafted solutions to protect overvoltage I/Os, other non‐
standard I/Os, and high‐voltage ICs, including those that require system‐level protection on the chip. Sofics technology produces smaller I/Os than any generic ESD configuration. It also permits twice the IC performance in high‐frequency and high‐speed applications. Sofics ESD solutions and service begin where the foundry design manual ends. ESD SOLUTIONS AT YOUR FINGERTIPS Our service and support
Our business models include • Single‐use, multi‐use or royalty bearing license for ESD clamps • Services to customize ESD protection o Enable unique requirements for Latch‐up, ESD, EOS o Layout, metallization and aspect ratio customization o Area, capacitance, leakage optimization • Transfer of individual clamps to another target technology • Develop custom ESD clamps for foundry or proprietary process • Debugging and correcting an existing IC or IO • ESD testing and analysis Notes
As is the case with many published ESD design solutions, the techniques and protection solutions described in this data sheet are protected by patents and patents pending and cannot be copied freely. PowerQubic, TakeCharge, and Sofics are trademarks of Sofics BVBA. Version
May 2011
Sofics Proprietary – ©2011
Sofics BVBA Groendreef 31 B‐9880 Aalter, Belgium (tel) +32‐9‐21‐68‐333 (fax) +32‐9‐37‐46‐846 bd@sofics.com RPR 0472.687.037