A Time-Based Analog-to-Digital Converter
Using a Multi-Phase Voltage-Controlled Oscillator
Jaewook Kim and Seonghwan Cho
Korea Advanced Institute of Science and Technology
(KAIST)
Daejon, Republic of Korea
Email: {jaewook, chosta}@kaist.ac.kr
Abstract— A time-based analog-to-digital converter(ADC) employing a multi-phase voltage-controlled oscillator(VCO) is presented. The VCO is based on a ring oscillator which converts
analog input voltage to phase information. Digital output is
produced by a phase quantizer which consists of a counter for
coarse quantization and phase detector for fine quantization.
Using this technique, an 8-bit 100Msamples/s ADC is designed
and simulated. Impact of jitter and VCO linearity on the ADC
performance is analyzed and verified.
clk
Analog
Input
Vin
Vout
Sampling Period
clk
fmin
I. I NTRODUCTION
Ts1
clk
VDD
Ts2
clk
0
t
The importance of ADC is becoming more crucial in emerging applications such as software radios and high definition
TVs where ADC is starting to become the system bottleneck
in performance as well as power consumption. For high-speed
applications, pipelined and flash ADC has dominantly been
used over the past decade. While the performance of these
ADC architectures has been progressing over the years, the
improvement has been subpar compared to that of the digital
system, as the analog circuits do not benefit as much from
gate length scaling as the digital circuits. This is due to the
supply voltage reduction that comes along with the technology
scaling, which results in lower signal swing and hence a lower
SNR for the ADC. As the supply voltage reaches sub-1V in
future technologies, improving the performance of pipelined
and flash architectures will be increasingly more difficult.
One way to surmount the challenge of low-voltage design
is to process the signal in time-domain. Since time resolution
improves despite the reduction in supply voltage, time-domain
signal processing offers a better solution compared to that of
the existing voltage-based methods.
In time-based ADCs, the input analog voltage is converted
to time or phase information. In [1] an integrated low-power
dual-slope architecture proved to be a promising candidate for
energy-efficient operation for low sampling rate applications.
Another approach based on time-based architecture is introduced in [2], but its feasibility or performance limitation is
not discussed. The ADC proposed in [3] uses a VCO as a
multi-bit quantizer, but it is used for an oversampling deltasigma converter.
In this paper, a time-based Nyquist-rate ADC using a multiphase voltage-controlled oscillator is presented. It is shown
that the ADC’s performance can be improved by increasing
the tuning range and exploiting the multi-phase outputs of
Digital Code
Generator
fvco
fmax
ffr
0-7803-9390-2/06/$20.00 ©2006 IEEE
Phase
Quantizer
VCO
Digital
Output
Vmin
Ts1
(a) Voltage-to-time conversion
Iout
# of rising edges
§ 'I
·
1¸
= integer ¨
© 2S
¹
'Iout
1LSB
= 2S
Ts2 t
Ts1
(c) Phase quantization
Fig. 1.
Ts2
Time
Vmax Vin
(b) VCO output in time domain
# of rising
edges
Digital
output
5
6
7
0101
0110
0111
(d) Digital code generation
Operation principles of a time-based ADC.
the VCO. The performance of the ADC is evaluated in the
presence of non-idealities such as jitter and non-linearities
of the VCO tuning curve. It is shown that the proposed
architecture is a good candidate for low-power high-speed
operation for future CMOS technologies.
II. T IME - BASED ADC USING VCO
A. Time-based ADC
The time-based ADC shown in Fig. 1 uses a VCO as a
voltage-to-time converter where the frequency is controlled
by the analog input voltage. The output phase of the VCO
represents the average analog input during the sampling period
and can be represented by the following equation,
∆φout
= 2π
Ts2
(Kvco Vin (t) + ff r )dt
(1)
Ts1
where Kvco is voltage-to-frequency gain, Ts1 , Ts2 are the
sampling times and ff r is the free-running frequency of
3934
ISCAS 2006
Phase
Quantizer
Vin
X
Y
Z
Vout
Analog
Input
Out
Ring
VCO
Vin
Delay Cell
Vx,y,z
VZ
Fig. 3.
Vout
Phase
Detector
Digital
Output
Vout
The block diagram of Time-based ADC using ring VCO.
clk
Time
Fig. 2.
Digital Code
Generator
( LUT )
clk
VX
VY
Counter
clk
'I out
The block diagram and timing diagram of ring VCO.
Ires,i
Ires,f
mS
fvco
the VCO when Vin =0. The output of the VCO is fed to a
phase quantizer whose digital output corresponds to the analog
input signal. The phase quantizer can be implemented using
a counter which detects the rising edges of the VCO output,
thereby quantizing the output phase by 2π. The digital output
of the phase quantizer is further processed by a mapping circuit
which stores the characteristics of the VCO and generates
the digital code. Since the full scale of the ADC input is
determined by the maximum frequency difference of the VCO
output, the resolution of the ADC that uses a counter as a phase
quantizer can be represented by the following equation,
fmax
fmin
−
)
fsample
fsample
ftuningrange
)
= log2 (
fsample
Resolution = log2 (
(2)
where fmax and fmin are the maximum and minimum
frequency of the VCO output and ftuningrange is the difference between these two values. It should be noted that
the sampling frequency(fsample) should not exceed fmin or
else DNL will be larger than 1-LSB. It can be seen that
the resolution is determined by the tuning range for a given
sampling rate. In addition, the resolution can be improved if
the phase resolution of the quantizer can be made smaller. In
our proposed architecture, the multi-phase output of the ringVCO is exploited to increase the resolution of the ADC.
B. Time-based ADC using a Ring Oscillator
In order to increase the resolution and the sampling rate
of the ADC, a VCO with large ftuningrange and fmax is
desirable. Although an L-C VCO can achieve larger fmax than
a ring oscillator, its small tuning range makes it impractical
for the L-C VCO to be used in the time-based ADC. On the
other hand, the ring oscillator can achieve very wide tuning
range. In addition, a ring oscillator can provide more than one
output phase as shown in Fig. 2.
The architecture of the proposed ADC using a multi-phase
ring VCO is shown in Fig. 3 and its quantization process is
illustrated in Fig. 4. During the sampling period, the VCO
converts the analog input voltage to phase(∆φout ). The output
Time
Fig. 4. The quantization process. φres,i and φres,f represents initial and
final residual phase.
phase, ∆φout , is coarsely quantized by the counter which in
this case counts the rising and falling edges of the VCO
output and hence produces digital output that is quantized
by π. The quantization error of the counter, which we call
the residual phase, is quantized by the phase detector with
the resolution of π/Ndcell with the help from the multi-phase
outputs of the VCO. The digital code generator collects the
phase information from the counter and the phase detector
and maps them to the corresponding output digital values. The
resolution of the proposed multi-phase architecture can now
be represented as the the following equation,
Resolution = log2 [(
= log2
fmax
fsample
−
fmin
fsample
)2Ndcell ]
ftuningrange
+ log2 2Ndcell
fsample
(3)
where in addition to the previously defined parameters, Ndcell
is the number of delay cells in the ring VCO. It can be seen
that the resolution is improved when the multi-phase output of
the VCO is exploited. However, it should be noted that simply
increasing the Ndcell does not improve the ADC performance
indefinitely. As will be shown in the later section, this is due
to the fact that fmax will decrease if Ndcell increases.
III. I MPACT OF N ON -I DEALITIES
There are several factors that will degrade the performance
of the ADC, which include jitter, linearity of the VCO,
mismatch, and the variations in process, voltage-supply and
temperature (PVT).
In practical oscillators, jitter will cause phase errors that
lead to degradation of the ADC resolution. For an N-bit timebased ADC with sampling period of Ts , the jitter(σTs ) should
be less than half LSB so that the DNL is less than one LSB.
3935
VDD
2.5
Vbias
2
- Vout
Fvco [GHz]
-Vin
Vin+
+
1.5
1
0.5
Vctrl
0
0.4
0.5
0.6
control
Fig. 6.
(i.e. σTs < 12 · 2TNs ) To achieve 10-bit ADC at 100MHz, the
VCO jitter should be less than 0.1% of the period, which is
feasible in today’s technology.
The non-linearity of the VCO is another factor which
degrades the performance of the time-based ADC. The nonlinearity of VCO at Vin =Vk is defined as
nonlinearity(%) =
1
1.1
1.2
1.3
Voltage-to-frequency characteristic of the CMOS ring VCO.
0
PSD [dB]
−40
−60
−80
−100
−120
0
10
20
30
40
50
40
50
Frequency[MHz]
(4)
0
−20
PSD [dB]
where is the frequency of a practical non-linear VCO and
fk is the frequency of an ideal VCO for Vin =Vk . To achieve
an N-bit resolution, the frequency difference between the ideal
and the practical VCO should be smaller than one LSB(or the
tuning range of VCO divided by its resolution i.e., fk − fk <
fmax −fmin
). Using Eq. 4, the maximum nonlinearity for an
2N
N-bit time-based ADC can be represented by the following
equation.
fmax − fmin 1
·
· 100
2N
fk
0.9
[V]
−20
fk
nonlinearity(%) <
0.8
V
Fig. 5. Circuit schematic of CMOS delay cell of ring VCO shown in Fig. 2.
fk − fk
· 100
fk
0.7
−40
−60
−80
−100
−120
0
10
20
30
Frequency[MHz]
Fig. 7. FFT result of the proposed ADC. (a) Ideal VCO. (b) Nonlinearity
of VCO, shown in Fig. 6, is considered.
(5)
The mismatch will cause the phase delay of the delay cells
to be different in a ring VCO. The effect of phase delay
mismatch can be considered to be similar to that of the jitter.
Analysis reveals that a 0.1% mismatch in the delay cell limits
the ENOB less than 13-bits. However since the delay itself
constitutes a small portion of the total period, the effect from
mismatch is much smaller than that of the jitter.
PVT variations that cause non-ideal characteristics of the
VCO is critical to the ADC performance and must be minimized. While differential circuit technique can alleviate the
effect of PVT variation to some extent, a calibration circuit
will be necessary in practical systems to store the characteristics of the VCO.
is shown in Fig. 6, where it can be seen that it has quite linear
tuning range from 100MHz to 2.48GHz. The nonlinearity of
implemented VCO defined by Eq. 4 is as low as 2%. The
performance of the ADC has been evaluated in the presence
of non-idealities. The fast fourier transform(FFT) results of
the proposed architecture using ideal and the implemented
VCO for 100MHz sampling frequency are shown in Fig. 7.
Due to the non-linearity of the VCO the effective-number
of bits(ENOB) is reduced from 7.91-bits to 7.75-bits. The
performance of the ADC with the effect of jitter is shown
in Fig. 8. It can be observed that the 1% jitter reduces the
resolution by approximately 0.1-bits. The sampling frequency
versus ENOB is plotted in Fig. 9.
IV. S IMULATION R ESULTS
V. T IME - BASED ADC S IN F UTURE CMOS T ECHNOLOGIES
A seven-stage ring oscillator is implemented using 0.18µm CMOS technology, where the circuit schematic is shown
in Fig. 5 [4]. The voltage-to-frequency curve of the oscillator
In this section the performance of the proposed ADC is
predicted for future CMOS technologies. Since the output
frequency of a ring VCO can be represented as fout =
3936
7.8
4
3.5
ENOB − ENOB(0.35um)
ENOB [bits]
7.6
7.4
7.2
7
3
2.5
2
1.5
1
0.5
6.8
0
6.6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
−0.5
5
Period jitter (%)
Fig. 8.
0.3
0.25
0.2
0.15
0.1
0.05
0
Length(um)
ENOB vs jitter.
Fig. 10. The ENOB vs technology scaling. The ENOB for 0.35um CMOS
process is set to zero.
Assuming that the CMOS technology will scale according to
[6], the improvement in ENOB of the proposed ADC is shown
in Fig. 10. It can be seen that the ADC resolution will increase
by more than three bits when CMOS gate length reaches 22nm
compared to the 0.35µm technology.
10
9.5
ENOB
0.35
9
VI. C ONCLUSIONS
8.5
A time-based analog-to-digital converter(ADC) employing
a multi-phase voltage-controlled oscillator(VCO) is presented.
Impact of jitter and VCO linearity on the ADC performance
is analyzed and verified.
8
7.5
20
30
40
50
60
70
80
90
100
VII. ACKNOWLEDGEMENT
Sampling Rate[Msps]
Fig. 9.
ENOB vs sampling frequency.
1/(2Ndcell Td ), the maximum achievable resolution of the
proposed ADC can be simplified as
Resolution log2 [2Ndcell (
log2 (
1
1
)
]
2Ndcell TDmin fsample
1
) − log2 fsample
TDmin
(6)
where TDmin is minimum propagation delay of a delay
cell. Assuming that the delay cell is a simple inverter, the
propagation delay of the inverter for a velocity saturated device
can be represented as [5],
TDmin
=
W LCox VDD
CVDD
(VDD −Vth )2
I
W vsat Cox (VDD
−Vth )+Ec L
(7)
where the maximum swing of inverter output is assumed to
be VDD . It can be seen that propagation delay is approximately
proportional to gate length(L). Therefore, technology scaling
improves the resolution of the proposed time-based ADC.
This work is supported by Electronics and Telecommunications Research Institute(ETRI). The authors would like to
thank IC Design Education Center(IDEC) for their support
in CAD tool and S.M. Ha and D.M. Park for the invaluable
discussion.
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[Online]. Available: http://www.uspto.gov/patft/
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