2.3 ppm/ C 40 nW MOSFET-Only Voltage Reference
◦
Oscar E. Mattia
Hamilton Klimach
Sergio Bampi
Microelectronics Graduate
Program
Federal University of Rio
Grande do Sul
Porto Alegre, Brazil
Electrical Engineering
Department
Federal University of Rio
Grande do Sul
Porto Alegre, Brazil
Informatics Institute
Federal University of Rio
Grande do Sul
Porto Alegre, Brazil
oemneto@inf.ufrgs.br
hklimach@ufrgs.br
ABSTRACT
A MOSFET-only sub-bandgap voltage reference at less than
50 nW and with very low temperature coefficient is introduced. It consists of a threshold voltage extractor circuit
and a proportional to absolute temperature voltage generator, using no resistors. The behavior of the circuit is analytically described, a design methodology is proposed and
simulation results for a 0.13µm CMOS process are presented.
It allows a reference voltage below the bandgap, 625 mV in
this design example, achieving a temperature coefficient of
2.3 ppm/◦ C for the -40 to 125 ◦ C temperature range. The
circuit consumes 40 nW at 27 ◦ C and under 1.2 V supply,
being the implemented silicon area 0.0099 mm2 .
Categories and Subject Descriptors
B.7 [INTEGRATED CIRCUITS]: Miscellaneous
General Terms
Theory, Design, Performance
Keywords
Voltage Reference; Nano-Power; Resistorless Reference; CMOS
Analog Design
1.
INTRODUCTION
Voltage references are fundamental circuit blocks ubiquitously used in analog, mixed-signal, RF and digital systems,
including memories. Mobile and energy harvesting applications require ultra low power designs, which should be
extended to all circuits, including the analog ones. Resistorless analog blocks have the advantage of implementation in
standard digital processes. Basically, voltage references can
be divided into three fundamental functions: the generation
of two voltages (or currents), one proportional and the other
complementary to absolute temperature (PTAT and CTAT,
respectively) and biasing. The biasing function is sometimes
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http://dx.doi.org/10.1145/2627369.2627621.
bampi@inf.ufrgs.br
implemented together with the PTAT generator, reducing
area and complexity, as done in the traditional bandgap reference (BGR), introduced by Widlar in 1971 [19].
In BGR circuits the CTAT voltage is implemented with
a p-n junction, which presents a slightly non-linear behavior over temperature [15]. This non-linearity is the main
contributor to the curvature over temperature usually seen
in these implementations, impacting directly the thermal
coefficient of the reference. Through the years many curvature compensation techniques were proposed [7], [14] and
[10]. Still, even in modern CMOS approaches they consume
high power [8]. References that do not implement curvature
compensation usually do not achieve low temperature coefficients [9] or operate under a limited temperature range [6].
Switched capacitors can also be used to reduce fabrication
variability [4], but the curvature effect is still present.
The MOSFET threshold voltage, in turn, presents an alternative way to implement a CTAT voltage. It has been
used in recent voltage references to achieve low power consumption and low power supply voltages [3], [17], [5], [12]
and [20]. The temperature range of these references varies
widely, but nano-watt power consumption, resistorless circuits and sub-1 V power supplies are common to almost all.
In this paper we propose a novel voltage reference based on
the sum of two almost linear temperature dependent terms.
A threshold voltage extractor, based on the self-biased current source topology presented in [1], provides the CTAT
voltage. The PTAT voltage is generated by two PMOS unbalanced differential pairs operating in weak inversion. The
sum of these two linear terms results in a significant reduction of the thermal coefficient over a wide temperature
range, while power consumption is kept low by the use of
transistors operating under weak and moderate inversion.
The text is organized as follows: section 2 presents the
threshold voltage extractor and the PTAT voltage generator circuits. A design methodology is proposed in section
3, followed by simulation results of the implemented reference in 0.13µm CMOS - section 4 - including Monte Carlo
variability analysis. To conclude, we compare our results
against typical results of recently published works.
2.
CIRCUIT DESCRIPTION
The transistors used in the proposed circuit operate both
under weak and moderate inversion levels, meaning that circuit analysis requires a model that describes all operation
regions using one equation, as done in the ACM MOSFET
model [2].
2.1
ACM MOSFET Model
In the ACM model, the drain current ID of a long-channel
MOSFET is expressed as
ID = IF − IR = SISQ (if − ir )
(1)
Where IF and IR are the forward and reverse currents,
S = W/L is the aspect ratio, W being the width and L
the length of the transistor. if and ir are the forward and
reverse inversion coefficients, related to the source and drain
inversion charge densities, while ISQ is the sheet normalization transistor current, defined as
1
0
nµCox
φ2t
(2)
2
Where n is the subthreshold slope factor, µ is the channel
effective mobility (both slightly dependent on the gate volt0
age VG ), Cox
is the gate capacitance per unit area, and φt is
the thermal voltage. The relationship between current and
voltage is given by
p
p
VP − VS(D)
= F (if (r) ) = 1 + if (r) −2+ln( 1 + if (r) −1)
φt
(3)
Where VS and VD are the source and drain voltages (all
terminal voltages are referenced to the transistor bulk), and
VP is the pinch-off voltage, approximated by (4).
ISQ =
VG − VT 0
(4)
n
Where VT 0 the threshold voltage for zero bulk bias. The
first term (the square root one) in the right side of (3) is
related to the drift component of the drain current, being
predominant under strong inversion. The last term (the
logarithmic one) is related to the diffusion component, being
predominant under weak inversion operation. In forward
saturation IF IR and consequently ID ' IF = SISQ if .
VP '
2.2
VT 0 Extractor
The proposed VT 0 extractor circuit, shown in Fig. 1, is
a variation of a self-biased current source presented in [1].
In the work of [1], both M1 and M2 were operating in weak
inversion. Here, we take a different approach on the same
circuit to extract the threshold voltage of transistors M1 and
M2.
inversion level equal to 3 (if = 3) will have a gate voltage
VG equal to the threshold voltage VT 0 . It happens because
under these conditions, the right side of (3) becomes zero.
In the circuit shown in Fig. 1, M1 is made to operate under such condition, being in the moderate inversion region.
Also in Fig. 1, M2 is designed with the same geometry of
M1, kept saturated too and sharing the same gate voltage,
but with a source voltage different from zero. Using (3) and
(4) for M2, knowing that VG2 = VG1 = VT 0 , leads to (5).
−VS2 = φt F (if 2 )
(5)
So, one can conclude that if the resulting M1 current ID1 ,
that was chosen to keep M1 operating with if 1 = 3, is also
used to control the drain current of M2 (through the M5-M6
current mirror), M2 also operates under a constant inversion
level, making F (if 2 ) constant. Thus, if a voltage proportional to φt is attached to the source terminal of M2, with
the right proportionality factor F (if 2 ) adjusted (using the
current mirror aspect relation K1), the equality of (5) can
be satisfied. A non-zero equilibrium point is then reached
in this circuit, that keeps VG1 = VG2 = VT 0 for any temperature. Since M2 operates with higher source voltage than
M1, its inversion level has to be lower, or F (if 2 ) < 0. This
means that in our circuit M2 operates in the weak inversion
region, and its PTAT source voltage can be generated by
the self-cascode topology, presented in the next section.
The temperature dependence of the threshold voltage VT 0
can be approximated by the linear equation (6).
VT 0 (T ) = VT 0(nom) + KT (T − Tnom )
(6)
Where T is the absolute temperature, VT 0(nom) is the threshold voltage at the nominal temperature Tnom and KT is the
thermal coefficient of the threshold voltage.
2.3
Self Cascode PTAT Generator
A well-known circuit used to generate a PTAT voltage
independent of process parameters is the self-cascode MOSFET, introduced by Vittoz in 1977 [18] and shown in Fig.
2.
Figure 2: Self-Cascode PTAT generator schematic.
Figure 1: Threshold voltage extractor schematic.
From (3) and (4), one can see that a saturated nMOSFET with grounded source and operating under a constant
Transistor M3 has higher drain current than M4 but smaller
aspect ratio, leading to different inversion levels on each
transistor. While M4 must be in saturation, M3 can be in
saturation or in triode. The difference between their gatesource voltages appear across the drain-source terminals of
M3. As done in [11], (3) and (4) demonstrate that this voltage is proportional to the thermal voltage. It is given by
VSC = VDS3 = φt [F (if 3 ) − F (iif 4 )]
(7)
Usually both transistors operate in weak inversion, but (7)
shows that as long as the inversion levels of both transistors
are kept constant over temperature, they generate an ideal
PTAT voltage under any inversion level [11]. This can be
achieved by biasing them with current I4 = K3 ISQ , where
K3 is constant with process and temperature. (7) then becomes
K3
K3
(K2 + 1) − F
(8)
VSC = φt F
S3
S4
VT 0 extractor of Fig. 1. Eq. (9) then becomes
K6
K4 K5 K6
−F
VDIF F = nφt F
(1 + K4 )S8
(1 + K4 )S8
(10)
This voltage is less ideal than that generated by the selfcascode (8), because the subthreshold slope n varies slightly
with process and temperature.
From (8) it is clear that the PTAT voltage generated by the
self-cascode MOSFET depends only on geometrical factors,
and not on fabrication process parameters.
The complete circuit of the proposed voltage reference can
be seen in Fig. 4. Transistors M1-M7 form the threshold
voltage extractor, being transistors M3-M4 the self-cascode
PTAT generator. The unbalanced differential pairs are made
of transistors M8-M17, and are sized exactly the same to
produce a total PTAT voltage that is twice that of a single
cell. Since we choose if 1 = 3, ID1 = 3S1 ISQ , and this
current is mirrored to bias the rest of the circuit through
pMOS transistors M5-M7, M12 and M17.
2.4
Unbalanced Differential Pair PTAT Generator
Another common PTAT generator structure is the unbalanced differential pair, introduced by Tsividis in 1978 [16],
that operates in weak inversion. This circuit is shown in Fig.
3, where K4 and K5 are the aspect ratio relations of M8-M9
and M11-M10, respectively.
2.5
Voltage Reference Circuit
Figure 4: Proposed voltage reference schematic.
The reference voltage VREF , at the gate of M13, is the
sum of a CTAT term given by (6) and twice the PTAT term
given by (9), hence:
VREF = VG1 +2VDIF F = VT 0 +2nφt [F (if 9 )−F (iif 8 )] (11)
Figure 3:
schematic.
Differential
Pair
PTAT
generator
3.
In this circuit, M8 and M9 share the same source connection, and the PTAT voltage develops across the two gates.
This is an interesting alternative that doesn’t load the previous circuit, since it is connected to a gate terminal. By
using the ACM model, it is possible to extend the operation of this circuit to all inversion levels, as was done for the
self-cascode structure. Assuming that all transistors are in
saturation and using (3) and (4), the PTAT voltage generated by the differential pair VDIF F is given by (9).
VDIF F = VG9 − VG8 = nφt [F (if 9 ) − F (if 8 )]
(9)
Eq. (9) is very similar to (7), only differing by the multiplying factor n. Since the M8-M9 pair is biased by the M10M11 mirror, one can conclude that if 9 /if 8 = K4 K5 . Thus
also this circuit generates a PTAT voltage independent of
the inversion region, as long as the inversion levels if 8 and
if 9 themselves are kept constant. Again, this is achieved by
biasing the differential pair with a current IDIF F = K6 ISQ ,
that can be obtained by mirroring the current ID1 of the
DESIGN METHODOLOGY
The design procedure starts by setting the forward inversion level of M1 if 1 = 3. A small aspect ratio for M1 and
M2 is necessary to achieve low power operation. Through
current mirror gain K1 the inversion level of M2 can be defined. A high value of K1 favors low power consumption,
but it also forces the source voltage of M2, generated by the
self-cascode pair M3-M4, to be higher. According to (8),
this can be done by increasing the ratio S4 /S3 , or by bringing M3 and M4 into moderate or strong inversion. If too
high a PTAT voltage is generated, it can put transistor M2
in triode, since its drain voltage is decreasing and its source
voltage is increasing with temperature. A good compromise
can be reached between power consumption and aspect ratio
gain by setting M5 = M6, making ID3 = 2ID4 .
Once the threshold voltage extractor is designed, differentiating (11) with respect to temperature, and equating it
to zero provides the necessary inversion level of M8-M9 and
M13-M14, together with aspect ratio and current gains K4
and K5 to make the output VREF temperature independent.
Since M8-M17 are all operating in weak inversion, to keep
the power consumption low, the value of the current mirror
gain K6 doesn’t affect heavily the PTAT voltage generated.
It is designed to guarantee that all transistors are kept in
saturation over the whole operating temperature range. The
same is true for the nMOS current mirrors M10-M11 and
M15-M16 aspect ratios. The resulting voltages and their
derivatives, simulated in Matlab, can be seen in Fig. 5.
point can be found and the loop gain can be calculated. This
is shown in Fig. 7.
Figure 7: (a) DC operating point; (b) Loop gain
versus frequency around DC operating point.
Figure 5: Analytical model. (a) Voltages versus
temperature; (b) first derivative over temperature.
The MOSFET parameters used for this demonstration
come from a standard I/O transistor from the 0.13µm process design kit library. VT 0 was extracted through simulation using the gm/id methodology described in [13], being
VT 0(nom) = 476 mV, Tnom = 27 ◦ C and KT = −500 µV/◦ C.
The constant design factors used are K1 = 6, K2 = 2,
K3 = 1, K4 = 2, K5 = 4 and K6 = 1.5, while the aspect
ratios are S1 = 1/30, S3 = 2/50, S4 = 6.6/50 and S8 = 1.
4.
There is only one crossing point of both lines, which happens for VG1 = VT 0 - Fig. 7(a). Fig. 7 (b) shows the loop
gain at the crossing point, being less than 0 dB and thus
providing a stable operating point.
Fig. 8(a) presents VT 0 over temperature estimated by the
gm/id method [13] (labeled ACM), and simulated in the VT 0
extractor circuit of Fig. 4 (labeled VTEX). The error defined
as Error(%) = 100(VT EX − VACM )/VACM is presented in
Fig. 8(b). The circuit tracks the ideal threshold with an
error inferior to 1.5% under the whole operating temperature
range.
SIMULATION RESULTS
The results presented here are for SPICE post-layout simulations, and accurately match the analytical design of section 3. The implementation takes into consideration good
matching layout practices such as common-centroid structures and dummies. The occupied silicon area is 0.0099
mm2 , as shown in Fig. 6, while the final MOSFET sizes
are presented in Table 1.
Figure 6: Layout of the proposed voltage reference
in 0.13µm CMOS.
Figure 8: (a) Proposed circuit and gm/id extracted
threshold voltage. (b) Error.
This CTAT voltage can then be added to the PTAT voltage generated by the unbalanced differential pairs, resulting in a reference voltage of 625 mV, as shown in Fig.9a.
The effective temperature coefficient, as given by (12), is
2.3 ppm/◦ C for the temperature range of -40 to 125 ◦ C,
operating at VDD = 1.2 V.
T CEF F =
Table 1: Implemented MOSFET sizing.
M1
M2
M3
M4
M5
M6
M7
M8
W (µm)
1
1
2*1
6*1.1
10
10
6*10
2*5
5
L (µm)
30
30
50
50
15
15
15
10
8.4
M17
M10
M11
M12
M13
M14
M15
M16
W (µm)
1
4*1
10
2*5
5
1
4*1
10
L (µm)
10
10
10
10
8.4
10
10
10
M9
The voltage extractor circuit employs positive feedback,
and the stability of the equilibrium point VG1 = VT 0 must
be guaranteed. Opening the loop on the gate of M1, and by
varying VG1 while observing the resulting VG2 , the operating
VREFmax − VREFmin
(Tmax − Tmin )VREF (27◦ C)
(12)
In Fig.9b the behavior of each voltage over temperature is
presented. It shows the extracted threshold voltage VT 0 , the
unbalanced differential pairs PTAT voltage 2VDIF F and the
temperature independent VREF . It also presents the PTAT
voltage VSC , generated by the self-cascode structure M3M4 used in the threshold voltage extractor circuit. Fig.9c
presents the currents in each branch over the -40 to 125 ◦ C
temperature range. The current consumption at 27 ◦ C for
the whole circuit is 33 nA, reaching a maximum of 44 nA at
125 ◦ C. This results in power consumptions of 39.6 nW and
52.8 nW respectively, for a 1.2 V supply.
Startup behavior of the circuit was simulated, having a
settling time of less than 3 ms, which is acceptable for this
proof of concept. We expect that leakage currents are enough
Figure 9: (a) VREF ; (b) VT 0 , VDIF F and VP T AT voltages; (c) Currents over temperature.
mismatch MC, the parameters of each transistor are varied
individually in each run. Both effects are taken into account
in a full variability analysis.
Fig. 11(a) shows the spread of the reference voltage, with
a σ/µ = 3.63% for mean process variation, while local mismatch, shown in Fig.11(c), yields σ/µ = 1.32%. Since both
are relevant, Fig. 11(e) also shows simulation results for
the two types of variability combined, yielding σ/µ = 4%.
Another relevant parameter that is affected by fabrication
spread is the thermal coefficient, which suffers more from
local mismatch - Fig. 11(d), than from mean process variations - Fig. 11(b). This is expected since the thermal voltage
dependence constant KT and the PTAT voltage derivative
are fairly insensitive to such mean variations. When both
local mismatch and average process are considered, the TC
reaches a maximum value of 76 ppm/◦ C - Fig. 11(f).
to start the circuit, but in real applications a startup circuit
could be necessary for faster settling.
Even though the nominal supply voltage of the process
used is 1.2 V, the proposed implementation starts operating
around 0.9 V with acceptable TC, as shown in Fig. 10b.
The circuit was designed to reach a minimum TC at 1.2 V.
Shown in Fig. 10(c), the line sensitivity of VREF is 35.2
mV/V, while the current consumption sensitivity is 21.88
nA/V, both from 0.9 V to 1.2 V supply. The power supply
rejection ratio (PSRR) measured at 100 Hz and VDD = 1.2
V is around -30 dB - Fig. 10a.
Figure 11: VREF and T CEF F Monte Carlo results.
Average process variation on (a) and (b); Local mismatch on (c) and (d); Both on (e) and (f ).
Figure 10: (a) PSRR; (b) T CEF F ; (c) VREF and
IT OT AL line sensitivities.
Table 2 presents a comparison of recently published lowpower, resistorless voltage references in different CMOS technologies. Since most of these works report experimental
data, we have selected the best case for each reference in
order to compare them with our simulation results. The
greatest advantage of our circuit topology is the low temperature coefficient over the widest temperature range, consuming low power while occupying a small silicon area. A
clear drawback of our reference resides in its high supply
sensitivity and consenquently low PSRR. These could be increased by adding cascode current sources, for example, at
the penalty of increasing the minimum supply voltage.
As noted before by other authors [9], reports of variability
results in such voltage references are still somewhat poor,
specially regarding experimental results from a significant
number of samples, and from different fabrication batches,
which would reveal the average process variability dependencies. To analyze the fabrication variability of the circuit,
Monte Carlo (MC) simulation was done separately for local mismatch effects and average process variations, with
1000 runs each. For average process MC all the transistors
have their parameters changed equally in each run. For local
The circuit has been sent to fabrication in a 0.13µm CMOS
process through the MOSIS educational program. Similar
results were obtained from simulations using other MOSFETs from the same 0.13µm technology, and re-designed on
a 0.18µm process as well.
5.
CONCLUSIONS
A novel resistorless ultra-low-power voltage reference circuit was presented. It is composed by a threshold voltage
extractor circuit and a PTAT generator working in weak inversion. Post-layout simulations for a 0.13µm CMOS technology demonstrate a reference voltage of 625 mV with a
power consumption of 40 nW under 1.2 V supply at 27 ◦ C.
The main advantage is the low temperature coefficient of
2.3 ppm/◦ C from -40 to 125 ◦ C, with an implemented silicon area of 0.0099 mm2 . Monte Carlo simulations show
that the spread of the reference voltage is σ/µ = 4% for
both process mean variation and local mismatch, while the
maximum temperature coefficient is 75 ppm/◦ C. The design
presented is a proof of concept, optimized for thermal stability. Other metrics such as silicon area, power consumption
and line sensitivity can be improved, according to the ultralow-power application requirements.
Table 2: Comparison of recent resistorless CMOS Voltage References
(+ ) experimental; (*) simulation
[3]+
[17]+
[5]+
[12]+
[20]*
[6]*
This Work*
Unit
µm
Technology
0.35
0.35
0.5
0.18
0.18
0.18
0.18
0.18
0.13
VT 0
VT 0
VEB
VT 0
VT 0
VEB
VT 0
VEB
VT 0
Temperature Range
0 – 80
-20 – 80
-40 – 120
0 – 125
-20 – 80
-40 – 120
-20 – 80
0 – 125
-40-125
Temperature Coefficient
10
7
11.8
142
176.4
114
19.4
7
2.3
ppm/◦ C
5
–
◦
C
Power @ VDDnom , 27 C
36
300
6.48·10
3.15
0.011
52.5
180
5.7
39.6
nW
VREF
670
745
1.23
263.5
328
548
633
479
625
mV
VDD
0.9 – 4
1.4 – 3
3.6
0.45 – 2
0.5 – 3.6
0.7 – 1.8
0.85 – 2.5
0.85 - 1.8
0.9 – 1.2
V
Line Sensitivity
2700
20
-
4400
440
-
0.024
2112
35200
ppm/V
PSRR @ 100 Hz
-47
-45
-31.8
-45
-49
-56
-76
-48
-30
dB
Silicon Area
0.045
0.055
0.1
0.043
0.0014
0.0246
–
0.0014
0.0099
mm2
ACKNOWLEDGMENTS
The authors gratefully acknowledge the support of CIBRASIL, MOSIS Educational Program and CNPq.
7.
[9]+
CTAT Voltage
◦
6.
[8]+
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