Data Sheet
26182.26C
5812-F
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
The UCN5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, highcurrent outputs also allow them to be used in other peripheral power driver
applications. They are improved versions of the original UCN5812A/EP.
OUT20
SERIAL
DATA OUT
LOAD
SUPPLY
LOGIC
SUPPLY
SERIAL
DATA IN
OUT 1
3
2
1
V DD 28
27
26
VBB
OUT19
4
UCN5812EPF
5
25
6
24
22
CLK
ST
15
16
17
18
CLOCK
STROBE
OUT10
OUT9
19
14
11
GROUND
20
13
10
BLANKING
21
12
9
OUT11
OUT12
OUT 2
23
LATCHES
8
REGISTER
LATCHES
7
REGISTER
OUT18
OUT 8
T
C
U
2
D
Y
1
L
8
O
6
N
R
P E O —A
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF
(32 bits).
t
D
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Dwg. PP-059-1
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ..................... 15 V
Driver Supply Voltage, VBB .................... 60 V
Continuous Output Current Range,
IOUT ................................. -40 to +15 mA
Input Voltage Range,
VIN ........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD
(UCN5812AF) ........................... 3.12 W*
(UCN5812EPF) ........................ 1.84 W†
Operating Temperature Range,
TA .................................. -20°C to +85°C
Storage Temperature Range,
TS ................................ -55°C to +150°C
The output source drivers are high-voltage pnp-npn Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
The UCN5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCN5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCN5812AF over the operating temperature range,
and the UCN5812EPF up to +75°C. All devices are also available for operation between -40°C and +85°C. To order, change the prefix from ‘UCN’ to
‘UCQ’.
* Derate at rate of 22 mW/°C above TA = +25°C
m
o
c
e
R
† Derate at rate of 15 mW/°C above TA = +25°C
FEATURES
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
■
■
■
■
■
Note that the UCN5812AF (dual in-line package)
and UCN5812EPF (PLCC package) are electrically identical and share a common terminal
number assignment.
High-Speed Source Drivers
■ Active DMOS Pull-Downs
60 V Source Outputs
■ Reduced Supply Current
To 3.3 MHz Data Input Rate
Requirements
Low Output-Saturation Voltages
■ Improved Replacement
Low-Power CMOS Logic and Latches
for TL5812
Always order by complete part number, e.g., UCN5812AF .
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
LOAD
SUPPLY
1
VBB
FUNCTIONAL BLOCK DIAGRAM
VDD
28
LOGIC
SUPPLY
SERIAL
DATA OUT
2
27
SERIAL
DATA IN
OUT 20
3
26
OUT 1
OUT 19
4
25
OUT 18
5
OUT 17
6
OUT 16
7
OUT 15
8
OUT 14
LATCHES
24
OUT 3
BLANKING
23
OUT 4
22
OUT 5
21
OUT 6
9
20
OUT 7
OUT 13
10
19
OUT 8
OUT 12
11
18
OUT 9
OUT 11
12
17
OUT 10
BLANKING
13
ST
28
16
STROBE
GROUND
14
CLK
27
15
CLOCK
LATCHES
STROBE
REGISTER
OUT 2
LATCHES
SERIAL-PARALLEL SHIFT REGISTER
REGISTER
SERIAL
DATA IN
BLNK
LOGIC
SUPPLY
V DD
CLOCK
SERIAL
DATA OUT
MOS
BIPOLAR
LOAD
SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
Dwg. PP-029-7
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
V BB
VDD
IN
OUT N
Dwg. EP-010-5
Dwg. No. A-14,219
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1988, 2000 Allegro MicroSystems, Inc.
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).
Limits @ VDD = 12 V
Min. Typ. Max.
Characteristic
Symbol
Output Leakage Current
ICEX
VOUT = 0 V, TA = +70°C
—
-5.0
-15
—
-5.0
-15
µA
Output Voltage
VOUT(1)
IOUT = -25 mA, VBB = 60 V
58
58.5
—
58
58.5
—
V
VOUT(0)
IOUT = 1 mA
IOUT = 2 mA
—
—
2.0
—
3.0
—
—
—
—
2.0
—
3.5
V
V
IOUT(0)
VOUT = 5 V to VBB
2.0
3.5
—
—
—
—
mA
VOUT = 20 V to VBB
—
—
—
8.0
13
—
mA
VIN(1)
3.5
—
5.3
10.5
—
12.3
V
VIN(0)
-0.3
—
+0.8
-0.3
—
+0.8
V
Output Pull-Down Current
Input Voltage
Input Current
Serial Data
Test Conditions
Limits @ VDD = 5 V
Mln. Typ. Max.
Units
IIN(1)
VIN = VDD
—
0.05
0.5
—
0.1
1.0
µA
IIN(0)
VIN = 0.8 V
—
-0.05
-0.5
—
-0.1
-1.0
µA
VOUT(1)
IOUT = -200 µA
4.5
4.7
—
11.7
11.8
—
V
VOUT(0)
IOUT = 200 µA
—
200
250
—
100
200
mV
3.3*
—
—
—
—
—
MHz
Maximum Clock Frequency
fclk
Supply Current
IDD(1)
All Outputs High
—
100
300
—
200
500
µA
IDD(0)
All Outputs Low
—
100
300
—
200
500
µA
IBB(1)
Outputs High, No Load
—
1.5
4.0
—
1.5
4.0
mA
IBB(0)
Outputs Low
—
10
100
—
10
100
µA
tPHL
CL = 30 pF, 50% to 50%
—
2000
—
—
1000
—
ns
tPLH
CL = 30 pF, 50% to 50%
—
1000
—
—
850
—
ns
Output Fall Time
tf
CL = 30 pF, 90% to 10%
—
1450
—
—
650
—
ns
Output Rise Time
tr
CL = 30 pF, 10% to 90%
—
650
—
—
700
—
ns
Blanking to Output Delay
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
CLOCK
A
B
DATA IN
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
D
E
F
C
STROBE
BLANKING
G
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
OUTN
Dwg. No. 12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Data Clock
Input Input
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
Output Contents
I1
I2
H
H
R1 R2 …
RN-2 RN-1
RN-1
L
L
R1 R2 …
RN-2 RN-1
RN-1
X
R1 R2 R3 …
RN-1 RN
RN
X
X
X
L
R1 R2 R3 …
RN-1 RN
PN
H
P1 P2 P3 …
PN-1 PN
L
P1 P2 P3 …
PN1 PN
X
X
H
L
L
X
I3
X
…
…
P1 P2 P3 …
L = Low Logic Level
IN-1 IN
X
PN-1 PN
H = High Logic Level
X = Irrelevant
I1
I2
X
I3
X
…
…
IN-1 IN
Blanking
X
P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
I1
I2
L
I3
L
…
…
IN-1 IN
L
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
Dimensions in Inches
(controlling dimensions)
28
0.015
0.008
15
0.700
MAX
0.580
0.485
0.600
BSC
1
2
0.070
0.030
3
14
0.100
4
1.565
1.380
BSC
0.005
MIN
0.250
MAX
0.200
0.115
0.015
MIN
0.022
0.014
Dwg. MA-003-28 in
Dimensions in Millimeters
(for reference only)
28
0.381
0.204
15
17.78
MAX
14.73
12.32
15.24
BSC
1
2
1.77
0.77
3
14
2.54
4
39.7
35.1
BSC
0.13
MIN
6.35
MAX
0.39
5.08
2.93
MIN
0.558
0.356
NOTES: 1.
2.
3.
4.
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 12 devices.
www.allegromicro.com
Dwg. MA-003-28 mm
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812EPF
Dimensions in Inches
(controlling dimensions)
18
0.013
0.021
12
19
0.219
0.191
11
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
0.020
28
1
4
0.456
0.450
0.495
0.485
MIN
0.165
0.180
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only)
18
0.331
0.533
12
19
5.56
4.85
11
0.812
0.661
11.58
11.43
12.57
12.32
1.27
INDEX AREA
BSC
5.56
4.85
25
5
26
0.51
MIN
4.57
4.20
28
1
4
11.582
11.430
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
POWER
INTERFACE DRIVERS
Function
Output Ratings*
Part Number†
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit (constant-current LED driver)
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
120 mA
250 mA
350 mA
100 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
24 V
50 V
50 V‡
50 V
5895
5821
5822
5841
5842
6275
6277
6595
6A595
6B595
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6810
12-Bit (active pull-downs)
-25 mA
60 V
5811
75 mA
17 V
6276
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
16-Bit (constant-current LED driver)
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-25 mA
350 mA
100 mA
250 mA
60 V
50 V‡
50 V
50 V
5815
5801
6B273
6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver
1.25 A
250 mA
350 mA
100 mA
450 mA
50 V‡
50 V
50 V‡
50 V
30 V
5804
6259
6A259
6B259
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
Complete part number includes additional characters to indicate operating temperature range and package style.
‡
Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000