Fuji Electric Journal
Vol.75 No.8, 2002
Multi-series Connection of
High-Voltage IGBTs
Yasushi Abe
Koji Maruyama
1. Introduction
Since power conversion equipment used by power systems,
industrial plants, and electric railways have large capacities
and operate at high voltages, devices such as the thyristor
and GTO (Gate Turn-Off) thyristor have traditionally been
used. On the other hand, for medium- to small-capacity
conversion equipment such as the general-purpose inverters,
the IGBT (Insulated Gate Bipolar Transistor) is widely used
to obtain a higher performance. The next step, which is
gaining importance, is to use the IGBT to the applications
where voltage is higher and capacity larger. Although Fuji
Electric has already marketed a press pack IGBT (2.5 kV/
1.8 kA) featuring a high withstand voltage and a large current,
a series-parallel connection technique for IGBTs that enables
operation at higher voltages is required to expand the uses of
IGBT conversion equipment.
Fig.1. Charge/discharge snubber circuit
Charge/discharge
snubber circuit
IGBT
Fig.2. Device voltage waveforms at turn-off (for two devices
connected in series)
Spike
voltage
In these circumstances, Fuji Electric is working to develop
technique that connects multiple IGBTs in series.
This paper focuses on the principle of operation of voltage
balance control technique in series connected devices,
simulation analysis, and test results.
2. Series Connection
2.1
Problems with Series Connection and Conventional
Circuitry
A major problem occurring when devices are connected in
series is that if a difference in switching timing occurs among
the devices, the voltage of each device will not be balanced,
placing too much of a burden for voltage on specific devices.
Because the switching speed of IGBTs is faster than that of
other power devices, there is a tendency for the imbalanced
device voltage to increase. In particular, during turn-off, the
transient voltage generated by interrupting the current is
superimposed on the main circuit voltage, increasing the
possibility of device damage. Controlling the balance of
device voltage is therefore a very important task when IGBTs
are connected in series.
Voltage slew rate reduction
Device voltage with earlier off timing
0
Switching timing difference
Without charge/discharge
snubber circuit
Device voltage
imbalance reduction
With charge/discharge
snubber circuit
2.2 Device Voltage Balance Circuit System
This section explains Fuji Electric's unique method for
solving the problem described above. The solution is a
simple circuit. In Fuji Electric's method, the gate wires of
IGBTs connected in series are coupled magnetically by a
core (referred to hereafter as the gate balance core) to
synchronize the timing of the gate current that flows during
switching. The result is that the device voltage can be
balanced.
Generally, a charge/discharge snubber circuit is connected
to each device, as shown in Figure 1, as an effective way to
solve this problem. The snubber circuit consists of
capacitors, diodes, and resistors. Because the voltage slew
rate at turn-off can be lowered, as shown in Figure 2, the
device voltage imbalance can be reduced. However, if the
snubber circuit is used in a high-voltage equipment, it needs
to be more complex and larger, which also increases losses.
1
Fuji Electric Journal
Vol.75 No.8, 2002
Figure 3 shows the circuit configuration of two series
connected IGBTs. The gate balance core is made up of a
secondary winding with a turn ratio of 1:1.
As shown in Figure 3, the gate balance core is inserted by
connecting each winding to the gate wire of the devices in
series. As a result, the gate wire of each series connected
device is magnetically coupled.
Fig.4. Timing chart
V i1 0
V i2 0
V g1
V g2 0
I g1
I g2 0
IGBT
GDU1
Input signal V i1
Q1
Off
On
Off
V g1
G
E
V g1
V g2
I g1
I g1
V CE1
V CE2 0
V g1
G
E
Q2
I g2
V CE1
V CE2
V CE1
V CE2
With gate balance core
GDU2
V g2
∆T (off)
∆T (on)
Rd1
Gate drive circuit
Without gate balance core
V CE2
I g2
Rd2
V T2
V g2
IC
The following explains the principle of operation of this circuit.
Figure 4 shows a timing chart. We assume that there is a
timing difference between the input signals Vi1 and Vi2 of Q1
and Q2, and that Vi1 is ∆T(on) faster at turn-on and ∆T(off) faster
at turn-off than Vi2. If there is no gate balance core Tg under
these conditions, the gate current and gate output voltage
(Ig1 and Vg1) of Q1 are ∆T(on) at turn-on or ∆T(off) at turn-off
faster than Ig2 and Vg2 of Q2, as shown in Figure 4 (it is
assumed that the signal transfer time of the gate drive circuit
GDU1 and that of GDU2 are the same). Because Q2 is in
the off state during ∆T(on) at turn-on, the device voltage VCE2
increases (indicated by the broken line). This voltage
increase is equal to the drop of VCE1. When ∆T(on) passes,
Q2 is turned on at Ta and the voltage drops, settled to a
steady state. In the same manner, because Q2 is in the on
state during ∆T(off) at turn-off, the device voltage VCE1 of Q1
that is cut off earlier increases, creating an imbalance
between VCE1 and VCE2 (indicated by the broken line).
When ∆T(off) passes, Q2 is turned off at Tb and the
unbalanced voltage converges to the normal voltage.
Next is explained the operation when a gate balance core Tg
exists. If Q1 first enters the on state during ∆T(on) at turn-on,
the gate current Ig1 starts to flow before all other currents.
However, this action causes a voltage difference between
gate drive circuits, generating a positive voltage at VT1 of the
gate balance core and a negative voltage at VT2. That is, a
voltage is generated to decrease Ig1 and to increase Ig2 so
that Ig1 = Ig2 can be expected, as indicated by the solid line in
Figure 4. This action synchronizes the gate timing. Using
a similar principle, if Q1 is first turned off, a negative voltage
is generated at VT1 and a positive voltage at VT2. A voltage
that increases Ig1 and decreases Ig2 is generated, and Ig1 = Ig2
is also achieved after turn-off.
2
Off
V CE1
I g1
V T1
Input signal V i2
On
I g2
Fig.3. Device voltage balance circuit system
Gate balance core T g
Off
2.3 Operation Analysis by Simulation
To verify the principle of operation described above, we
conducted a simulation analysis of the circuit in Figure 3.
We used a two-dimensional simulator, ISE-TCAD (ISE AG),
which can perform a coupled simulation of devices and
circuits.
Figure 5 shows the results of simulating the turn-off operation.
As the device model, we used a Fuji Electric 2.5kV press
pack IGBT. We also assumed that Q1 was 200ns faster
than Q2. From the simulation results, we can confirm that
the imbalance of device voltage can be controlled by
connecting a gate balance core.
Fig.5. Simulation results
4,000
3,000
Device voltage (V) 2,000
Device current (A)
IC
1,000
V CE1
V CE2
500 ns
0
(a) Without gate balance core
4,000
3,000
Device voltage (V) 2,000
Device current (A)
IC
V CE1, V CE2
1,000
500 ns
0
(b) With gate balance core
2.4 Prototype of the IGBT Multiseries Connected Stack
To apply the principle of operation of the gate balance core
explained above to conversion equipment, we built a
prototype stack by connecting four IGBTs in series . We
used Fuji Electric 2.5kV/1.8kA press pack IGBTs. Like a
thyristor, this IGBT has a pressure contact structure, which is
appropriate for a series connection.
Fuji Electric Journal
Figure 6 shows the gate balance core and the gate drive
circuit peripheral. The gate balance core is contained in the
gate drive circuit.
Vol.75 No.8, 2002
Fig.7. Stack and circuit configuration
Gate drive circuit
IGBT
Cooling fin
Figure 7 shows the complete stack and the circuit
configuration. This circuit configures one phase of the
2-level inverter and has a structure in which voltage is
applied by sandwiching eight IGBTs of the upper and lower
arms between the cooling fins, which are water-cooled.
Q11 - Q14 and Q21 - Q24 in the figure are IGBTs, GDU11 GDU14 and GDU21 - GDU24 are gate drive circuits, R11 - R14
and R21 - R24 are voltage dividing resistors, and Tg11 - Tg14
and Tg21 - Tg24 are gate balance cores. When the gate
balance cores are connected as shown in the figure, all gate
wires of the IGBTs that are connected in series are coupled
magnetically.
(a) Complete stack
Gate balance core
Tg11 Q11
GDU11 I g1
GDU12
R11 V CE(Q11)
Q12
I g2 Tg12
R12 V CE(Q12)
Fig.6. Gate balance core and gate drive circuit peripheral
Q13
GDU13 Tg13
I g3
GDU14
I g4 Q14
R13 V CE(Q13)
R14 V CE(Q14)
29.5
Ed
29.4
26.5
Tg21
GDU21
Q21
R21 V CE(Q21)
(Unit: mm)
(a) Gate balance core
Gate drive circuit
IGBT
GDU22
Tg22
Cooling fin
Q22
R22 V CE(Q22)
Q23
GDU23 Tg23
R23 V CE(Q23)
Q24
GDU24
R24 V CE(Q24)
DC voltage Ed = 4,000 (V), collector current Ic = 1,000 (A)
Q11 - Q24: 2.5kV/1.8kA press pack IGBT (manufactured by Fuji Electric)
(b) Circuit configuration
(b) Gate drive circuit peripheral
2.5 Prototype Test Results
We performed a turn-off test using a stack that was created
by connecting four IGBTs in series (see Figure 7). The test
conditions were a DC voltage of 4,000V, a breaking current
of 1,000A, and the upper arm (Q11 - Q14) was used to
interrupt the current. We also put forward the switching
timing of Q11 by 200ns with respect to the three other
devices.
We first measured the gate current timing with and without
gate balance cores to verify the gate current balance effect of
the gate balance core. Figure 8 shows the measurement
results. When there was no gate balance core, the gate
current Ig1 of Q11 started to flow 200ns earlier than the other
gate currents. However, as the figure makes clear, when
gate balance cores were connected, the gate currents of the
four devices started to flow at the same time.
Fig.8. Gate current measurement results
0
I g2, I g3, I g4
I g1
1 s
(a) Without gate balance core
0
I g1, I g2, I g3, I g4
1 s
(b) With gate balance core
3
Fuji Electric Journal
Vol.75 No.8, 2002
We then measured the device voltage to verify that balancing
the gate current timing can have an effect on the element
voltage sharing balance. Figure 9 shows the element
voltage waveforms of Q11 and Q12.
Fig.9. Element voltage balance measurement results
IC
It is clear from the figure that if no gate balance core exists,
the device voltage VCE (Q11) of Q11 that is turned off earlier
increases more than the device voltages of the other devices.
However, when connecting gate balance cores are
connected, the device voltage can be equalized.
V CE(Q11)
V CE(Q12)
3. Conclusion
0
1 s
This paper presents a technique that enables the series
connection of multiple high-voltage IGBTs. To promote the
miniaturization and improved performance of high-voltage
power conversion equipment such as those used in power
systems and industrial plants, we intend to continue working
on the development of high-voltage technology, which
includes series connection technology.
(a) Without gate balance core
References
(1)
IC
Eguchi, N. et al. Constituent Technologies Supporting Power
Electronics for Power and Industries. Fuji Review vol. 74,
no. 5, 2001. pp. 265-272
V CE(Q11),
V CE(Q12)
0
(2)
Abe, Y. et al. Improving Element Voltage Balance for IGBTs
Connected in Series. National Symposium of the Institute of
Electrical Engineers in 2001, 4-002, 2001
Commentary
(b) With gate balance core
VCE(Q11),VCE(Q12):500V/div
IC:500A/div
Noise terminal voltage
The noise terminal voltage is also called conduction noise.
It is a kind of wave causing electromagnetic interference
that propagate to the power wire of electronic equipment
in frequency bands at 30MHz and below, and can cause a
failure. The noise (that is, the magnitude of the
interference) can be assessed by measuring the voltage
generated in the power wire.
The limit value of the noise terminal voltage is prescribed
by CISPR Pub.22, which is an international standard. As
shown in the figure, CISPR Pub.22 is prescribed for each
frequency band in the bands from 150kHz to 30MHz.
Switching power units mounted in information technology
equipment such as PC monitors and adapters used at
home must meet CISPR Pub. 22 Class B requirements.
Class A requirements apply to equipment used in
commercial and industrial areas.
4
1 s
100
90
80
Noise 70
terminal
voltage
(dB V) 60
A
B
50
40
30
100
A : CISPR Pub.22 Class A
B : CISPR Pub.22 Class B
1,000
10,000
Frequency (kHz)
100,000