Modular Extension of ATE to 5 Gbps
D.C. Keezer1, D. Minier2, M. Paradis2, F. Binette2
(1) Georgia Institute of Technology
School of Electrical and Computer Engineering
(2) IBM Canada
Abstract
Existing digital automated test equipment (ATE) can
provide signals at about 1 Gbps or slightly higher. To
accommodate multi-GHz test needs, some ATE provide
options for a few faster channels (up to 3.6 Gbps). However,
leading-edge parts may require 100s of these signals and in
some cases at even higher speeds (5 and 10 Gbps). This paper
describes a modular approach that allows for as many as 144
multiplexing and/or sampling channels to be added to existing
ATE. The modules developed, so far include multiplexers,
demultiplexers, and high-speed samplers that each support
multiple high-speed differential signals. Production units
operating up to 2.5 Gbps were introduced in [10]. In this
paper we provide more detailed characterization of these
modules and describe new modules targeting 3.2 Gbps and 5.0
Gbps applications.
Various re-clocking techniques and
proprietary calibration methods are used in order to reduce
timing errors (especially jitter) to the sub-50ps range. The
general system configuration, and key features of the newly
developed modules are presented.
1
Introduction and Background
Since 1990 researchers have been devising methods to
extend the maximum test frequency of existing automated test
equipment [1-10].
These approaches typically involve
multiplexing of large channel count systems to obtain a
smaller number of higher-rate channels. Multi-gigahertz
testing presents numerous technical and economic challenges.
When the bit time interval is just a fraction of a nanosecond
(i.e. 400ps at 2.5 Gbps), the ATE must maintain timing
accuracies of just a few tens of picoseconds. This level of
accuracy must be maintained throughout very long test
sequences and across hundreds of channels.
In these
situations, bit error rates (BERs) must be very small to avoid
false failures.
High-channel count (above 512), moderate speed
(~1Gbps) test systems are readily available, and are used for
more routine testing needs. In this project, an Agilent 93000P1000 with about 900 channels is utilized. Using high-speed
multiplexing and sampling techniques, these systems can be
enhanced to address the needs of multi-gigahertz devices [110]. However, maintaining tight timing accuracy becomes
increasingly difficult at the higher data rates.
The use of multiplexing logic and high-speed data
sampling in order to apply gigahertz tests (500 Mbps to 1.6
Gbps) is described in [1-8]. Using a 200 Mbps automated test
system groups of 2, 4, and 8 signals are combined with simple
exclusive-OR gates to synthesize gigabit-per-second stimuli
[2,3]. The addition of high-speed flip-flops to the test
environment provides a way to sample the DUT outputs at
these same rates [3,4]. The critical issue of timing calibration
is addressed in [5]. Some refinements to the basic techniques
Paper 26.3
748
are described in [6], including an emphasis on modular
construction that facilitates calibration and re-use of the highspeed circuits. In [7], Wimmers, et al describe application to
testing at 500 MHz and higher. Application of these
techniques to a high complexity device is described in [8]
where the test frequency was between 500 and 800 MHz.
This used 5 high-speed inputs and 34 high-speed outputs.
These techniques have been refined to extend the
frequency range to 2-4Gbps [1,9,10]. In [10] the practical
realities of achieving (and maintaining) acceptable timing
accuracies during production testing have been addressed.
These include: automated methods for timing calibration,
adjustable I/O voltage levels, support for DC testing, and
water-cooling of the added electronics for thermal stability.
The control and testing of jitter effects plays a critical role in
our ability to assure timing accuracy [11,12,13].
2 Automated Test System Configuration
A top-level view of the multiplexing test system is illustrated
in Fig.1. The general approach uses multiplexing (“Driver”)
modules mounted on the load-board to produce the high-speed
stimuli signals, and sampling or demultiplexing (“Receiver”)
modules for capturing the DUT output response. The modular
approach is used so that the Driver and Receiver electronics
can be developed and fully characterized prior to assembling
to the load-board. The use of high pin-count high bandwidth
connectors between the modules and the load-board, permits
replacement or reuse of the modules. The load-board also
supports “low” speed connections to the ATE through
controlled-impedance transmission lines, and pogo pins.
Water-cooling of the modules is required for heat removal,
and more critically, for maintaining the module temperature as
the DUT is temperature-cycled (see further discussions below,
in section 6, and in [10]).
DUT Test
Socket
Application
Loadboard
Driver Modules
Cooling
Water
Connections
Receiver Modules
Fig.1 – Multiplexing test configuration that includes
multiplexing and sampling modules mounted to the bottom
side of the load board.
ITC INTERNATIONAL TEST CONFERENCE
0-7803-8580-2/04 $20.00 Copyright 2004 IEEE
In a typical application (see Fig.2), the DUT requires
several multi-GHz inputs signals and produces several highspeed outputs. The high-speed inputs are synthesized within
the Driver modules, which are themselves controlled by the
ATE using multiple data channels. The high-speed outputs
from the DUT are sampled, and in some cases demultiplexed
using Receiver modules of various types. In the figure, “DC
Channels” are provided to each module (connected to ATE
channels). These are switched within the Modules to permit
direct connection of the DUT I/O for DC parametric tests.
Other low-speed signals are connected directly to the ATE.
Driver
Module
~1 Gbps
Data
(from ATE)
Multi-GHz
Inputs
Driver
Module
DUT
Driver
Module
Driver
Module
DC Channels
(from ATE)
Multi-GHz
Outputs
“Low” Speed
I/O (to/from ATE)
Receiver
Module
Receiver
Module
Receiver
Module
~1 Gbps
Data
(to ATE)
Figures 4a and 4b shows views of five Driver Modules
mounted to the bottom of an application board. This
particular application test a device requiring over 100 multiGHz input signals, and as many outputs. For this application,
four Driver Modules each provide 24-channel, single-ended
signals at rates up to 1.8 Gbps. The fifth module produces 12
differential channels. A complimentary arrangement of 5
Receiver Modules (not shown in the figures) provides the
necessary test resources for capturing the DUT output signals.
For clarity, Fig.4a shows the Driver modules mounted in
position without their cooling plates. Only about half of the
entire DUT load-board is visible in this picture (the other half
supports the Receiver modules). The volume of space
available below the load-board is extremely limited, so each
module is carefully designed to fit within the limits of the
mechanical support structures. These limitations are even
more evident in Fig.4b that shows the five Driver modules
with their cooling plates installed. The custom-machined
cooling plates are designed to fully-exploit (and completely
fill) the available space under the load-board.
Receiver
Module
Driver
Module
PCBs
DC Channels
(to ATE)
Fig.2 – Typical application test configuration.
As illustrated in Fig.3, each module is made-up of a multilayer printed circuit board with components mounted on both
sides. The PCB measures approximately 5cm x 24cm, and has
two multi-pin connectors, which provide the signal
connections to the application load-board. For thermal
control, two water-cooled plates are machined to match the
profiles of the components on the PCB top and bottom
surfaces. When assembled, the plates and PCB are tightly
sandwiched together so that the total thickness of the module
is about 2cm. In this way as many as 12 of the modules can be
mounted in the space available below the application loadboard.
80-signal 50-Ohm
Connectors
“Bottom” Cooling Plate
Multi-layer
PCB
“Top” Cooling Plate
Cooling Water
Connections
Fig.3 – Internal construction of the modules.
DUT
Socket
Fig.4a – Photograph of application load-board (bottom
view) with five Driver Modules (cards only) installed.
Water
Hoses
Driver
Modules
Fig.4b – Photograph of application loadboard (bottom
view) with complete Driver Modules installed (including
cooling system).
Paper 26.3
749
3 Driver Modules
The basic logic implemented for each high-speed signal
is illustrated in Fig.5. Each Driver module is designed to
multiplex groups of signals from the ATE. Typically the
multiplexing factor is either 2:1,4:1, or 8:1, although 3:1 is
also useful for some applications [1]. With an ATE base
frequency of 1 Gbps, this permits the generation of multi-GHz
signals within the Driver modules.
In addition to the basic multiplexing function, the Driver
module also includes a variable-amplitude buffer, embedded
calibration logic, and high-performance relays.
The
calibration logic is used for timing alignment of the signals
produced by the multiplexer, in order to achieve the desired
time delay at the DUT input. A “Calibration Reference”
signal is distributed throughout the system and provided as
input to each module. In some Driver modules, the ATE
timing control is used to adjust the phase of the data inputs to
the multiplexer. In other versions, the phase of a mulit-GHz
clock is adjusted.
The relays contained in the Driver module permit
switching of ATE channels directly to the DUT inputs
(bypassing the multiplexing logic). This allows the DC
parametric units (PMUs) of the ATE to be used in their
normal fashion to measure characteristics such as inputleakage, continuity, and input voltage sensitivity (VIL/VIH).
RF Connectors
Amplitude
Control
D1
D2
D3
D4
MUX
Logic
RF/DC
Select
+
-
+
+
Relays
-
DC Test
Channels
(from ATE)
Multi-GHz
Clock
Calib Ref
To
DUT
Embedded
Calibration
Logic
refinements including the use of water-cooling. These
modules utilize a well-known exclusive-OR multiplexing
approach [1-10], whereby several ATE channels are encoded
and phase-delayed and presented at the inputs to an XOR gate.
The gate then decodes and multiplexes the data in real-time to
produce the desired serial bit stream. Even though suitable
XOR gates are available which can multiplex at multi-GHz
rates [1], the practical limit of this technique is driven by the
timing accuracy of the ATE signals (which is usually in the
100ps to 200ps range). The XOR output timing is directly
controlled by the ATE. This direct-control feature has both
advantages and drawbacks. The advantage is that it allows the
ATE to be iteratively reprogrammed until the optimal timing
is achieved. The drawback is that the resulting “optimal”
timing is ultimately limited by the ATE accuracy that is
usually not tight enough for serial rates above about 2 or 2.5
Gbps[10]. For faster speeds, a low-jitter clock signal is used
to separate the critical timing from the ATE data as described
below.
Table 1 – Driver Modules
Design #
Function
Driver1
4:1 XOR Mux
Driver2
4:1 XOR Mux
Driver3
4:1 ReClk Mux
Driver4
2:1 XOR Mux
Driver5
8:1 ReClk Mux
Driver6
16:1 ReClk Mux
Driver7
4:1 ReClk Mux
Driver8*
32:1 ReClk Mux
(* under development)
#Ch
8 Diff
12 Diff
12 Diff
24 SE
4 Diff
2 Diff
8 Diff
1 Diff
Fmax
2.0 Gbps
2.0 Gbps
2.5 Gbps
1.8 Gbps
3.6 Gbps
5.0 Gbps
3.2 Gbps
10.0 Gbps
An eye diagram for a 1 Gbps differential output from
Driver module “Driver2” is shown in Fig.6. The symmetric
rise and fall times on the order of 140ps contribute to a wide
eye opening. In this example, the multiplexing logic is
operated in a 1:1 mode. Some voltage distortions evident in
the figure are attributed to impedance discontinuities in the
signal path between the Driver module and the DUT inputs.
Fig.5 – Logic implemented by each of the Driver module
channels (shaded elements are shared with other channels).
To exploit the modularity of this approach, several
different Driver modules have been constructed (or are under
development), as outlined in Table 1. Each of these is
designed to optimize ATE resources while meeting specific
DUT test requirements. All implement various types of
multiplexing schemes, ranging from 2:1 XOR-based
multiplexers [1-10] to 32:1 parallel-to-serial converters. The
simpler arrangements (XOR Mux) provide maximum data
rates which are limited by the timing accuracy of the ATE to
about 2 Gbps. Higher performance (3.2 and 5.0 Gbps)
requires re-clocking the multiplexed data using a low-jitter
clock source.
The first two Driver modules (Driver1 and Driver2) have
been described in [10]. Driver1 was an 8-channel, air-cooled
prototype, while Driver2 provided 12 channels, and some
Paper 26.3
750
Fig.6 – “Driver2” 1 Gbps eye diagram of the multiplexer
output (811mV p-p) [10].
Nevertheless, the logic transitions are 2 to 3 times sharper than
those produced by the ATE alone. Furthermore, the Driver
module signals are true-differential, whereas the ATE
produces only single-ended signals.
Operating in a 4:1 mode, with the ATE running at
625 MHz, the Driver multiplexers produce 2.5 Gbps. These
signals are captured with the embedded calibration logic, and
graphically displayed using the “Shmoo plot” utility of the
ATE, as shown in Fig.7. Here the data is switching state
every 400ps. The timing resolution of this shmoo plot is 64ps
and the uncertainty of the logic transitions is about at that
resolution limit.
Fig.8 – “Driver2” multiplexed output
data eye diagram (2Gbps) [10].
Fig.7 – Example showing a 2.5Gbps data pattern as
measured with the embedded calibration circuit [10].
Fig.7 – “Driver2” 2.5Gbps clock pattern as measured using
the internal embedded calibration circuit [10].
A 2 Gbps eye diagram of a pseudorandom data
pattern at the DUT input is shown in Fig.8. Here an open eye
is obtained with a nominal signal amplitude of 800mV. The
pattern is limited primarily by jitter (about 150ps to 200ps). It
should be noted that the displayed jitter is a result of multiple
signals provided by the ATE, each including the effects of
four timing edge generators. Nevertheless the signal is
sufficient to test the high speed performance of the DUT.
The same circuit can be run at even higher speeds by
reprogramming the ATE. In Fig.9, the Driver2 ouput is
shown while producing a “clock” pattern (010101…) at 2.5
Gbps. Because of the regular nature of the pattern, relatively
good timing accuracy is achieved. The figure shows that the
timing errors are primarily due to jitter and are less than 90ps.
Cycle-to-cycle systematic timing errors can be almost entirely
eliminated since each edge is associated with a different
timing generator in the ATE. Therefore, jitter is the primary
contributer to the residual error. In the simple XOR approach
used for Drivers 1, 2, and 4, the ATE jitter passes directly to
the DUT input signal. A higher-precision TIA measurement
of jitter in Fig.10 confirms that it is about 84ps at a BER level
of 10-12.
Fig.9 – “Driver2” 2.5Gbps clock pattern.
Fig.10 – “Driver2” 2.5Gbps clock jitter TIA.
Paper 26.3
751
Despite the acceptable performance of the Driver2 module
at 2.5 Gbps using a “clock” pattern, the situation is not so
good when arbitrary data is used. An eye diagram at 2.5 Gbps
is illustrated in Fig.11. Here it can be seen that an open eye is
obtained. However, the resulting jitter in the data transitions
is measured at about 200ps (leaving about 0.5UI). This
measurement, like that of Figs.6 and 9, includes the effects of
jitter on the oscilloscope trigger input. To obtain a more
accurate measurement, a time interval analysis (TIA) method
is used as shown in Fig.12. Here the measured error is 150ps,
leaving an open eye of 0.63 UI at a BER of 10E-12.
Therefore, a usable eye opening is obtained, but the resulting
timing error of +75ps is not as good as desired for testing at
2.5 Gbps, since 0.75 UI or better is normally required.
Driver3, an external low-jitter clock source is used to re-clock
the multiplexed data. This “reclock” signal generator is
phase-locked with the ATE system master clock so that the
multiplexed signals produced by Driver3 are also locked to
the ATE. The reclocking operation is illustrated in Fig.13
where both the multiplexed data eye and the reclocking signals
are displayed for 3 data bit periods at 1.25 Gbps. The data
eyes exhibit similar jitter characteristics as in prior designs,
although these signals appear a little better because they were
measured within the module. The 3 diagonal “lines” in the
figure are actually the rising edges of 3 reclock cycles (the
falling edges are obscured by the data patterns). The clock
was measured separately and found to have random jitter of
about 1.5ps rms, or about 20ps peak-to-peak. That small
amount of jitter explains why it appears as a sharp “line” in
the figure. The difference between it and the data is strikingly
clear in the figure. Still, the data eye opening at this speed
provides plenty of timing margin for reclocking. Form this
point on within the module, the data eyes exhibit jitter
characteristics closer to that of the reclock signal.
Fig.11 – “Driver2” 2.5Gbps Data eye-diagram.
Fig.13 – “Driver3” ReClocking (1/2 channel at 1.25Gbps).
Fig.12 – “Driver2” 2.5Gbps Data jitter TIA.
In a fundamental shift from earlier work, the design
of Driver3 addresses the data-dependant jitter problem
illustrated in Driver2 above. Notice that most of the residual
timing error in Fig.12 is a result of “deterministic” jitter, while
the “random” jitter component is very small. In the design of
Paper 26.3
752
After passing through the remaining multiplexing
logic and the variable I/O buffer, the data eye is illustrated in
Fig.14a. Here the measured peak-to-peak jitter is about 100ps
(including oscilloscope trigger jitter). This signal also
includes the effects of reflections coming from the relays and
RF connectors.
After passing through the relays and
connectors, the signal (at the DUT) is illustrated in Fig.14b.
Here peak-to-peak jitter is about 128ps (including O-scope
trigger jitter). Allowing for the effects of trigger jitter, this
leaves an improved eye opening at 2.5 Gbps (as compared
with Driver2).
Despite the improvements obtained in the Driver3
design, there were several lessons learned that suggested ways
to get even better performance. One obvious weakness was in
the relay/connector arrangement. Comparison of Fig.14a and
Fig.14b clearly shows the loss in signal quality as it passes
through these structures. In later designs (see below), both the
relays and the RF connectors were replaced for this reason.
Chip Delay Characterization
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
6500
Measured Delay (ps)
6300
6100
5900
5700
5500
5300
5100
4900
100
960
920
880
840
800
760
720
680
640
600
560
520
480
440
400
360
320
280
240
200
160
80
120
0
40
4700
Delay Code
Fig.14a – “Driver3” Data-eye at 2.5Gbps as measured oncard, (before relays and connectors).
Fig.14b – “Driver3” Data-eye at 2.5Gbps as measured at
DUT input, (after relays and connectors).
A drawback to the reclocking approach used in
Driver3 is that the signals, once reclocked, are not under the
direct control of the ATE. Therefore alignment and changing
of signal delays within the Driver modules requires a
programmable delay element (IC). Luckily, such circuits are
commercially available. The one used in Driver3 provides a
10-bit digital program capability with a 10ps minimum step
size. This gives 1024 steps in a 10ns range, which is more
than adequate for multi-GHz patterns. However, the delay
circuit itself has non-ideal behavior as illustrated in Fig.15.
Here the program delay code is incremented along the
horizontal axis, with the actual measured delay plotted along
the vertical axis. The figure shows only the first 1.0ns of the
range. In the figure, 12 such plots are shown, taken from 12
channels in a Driver3 module. Each channel exhibits similar
characteristics which is mostly a linear trend with “small”
nonlinearities. If these nonlinearities are neglected, then
additional timing errors of about 50ps will be encountered.
By measuring these effects, look-up tables are constructed
which allow the errors to be corrected to within 10ps. These
added calibration steps are required for multi-GHz operation.
Fig.15 – “Driver3” delay time characterization.
Based on the lessons-learned from Driver3, a new
design (“Driver5”) was created that targets even higher speeds
(3.2 and 5.0 Gbps). The Driver5 design utilizes the
“reclocking” strategy. However, it also includes a faster
multiplexing circuit, higher-speed (SiGe) output buffers,
higher-speed relays and RF connectors.
The performance of the new, Driver6, design is
illustrated in Fig.16a. Here a data eye diagram at 2.5 Gbps is
shown. This measurement is made at the DUT input (after all
relays and connectors). The measured jitter is 51ps peak-topeak and includes the oscilloscope trigger jitter
(conservatively estimated to be 20 to 30ps). This leaves an
eye opening of at least 0.87 UI at 2.5 Gbps. The risetime of
the signal was measured separately at about 60ps (20% to
80%) including the bandwidth limitations of an 8GHz resistive
probe (the measurements shown were taken with a 5 GHz
differential FET probe). This is consistent with the expected
SiGe output transitions of about 40ps, and some (small)
risetime degradation through the relays and connectors.
Overall, the performance of this design was a great
improvement over the earlier designs at 2.5 Gbps.
In Fig.16b, the Driver6 is demonstrated at 3.2 Gbps.
Similar jitter and risetime characteristics result in a usable eye
opening of better than 0.80 UI. At 5.0 Gbps, shown in
Fig.16c, the eye open appears to be starting to closing-off.
Nevertheless, an eye opening of about 0.75 UI is still
achieved. When allowances are made for the oscilloscope
trigger jitter (about 10ps to 20ps) and the FET probe
bandwidth limits, the usable eye is expected to be above 0.80
UI.
A 5.0Gbps “clock” pattern is shown in Fig.17. The
TIA indicates total jitter of about 53ps at 10-12 BER. Of this
about 12ps is deterministic, which may be reduced by
improvements to the calibration procedure, part of which is
designed to align two 2.5 Gbps data channels used to synthesis
the 5.0 Gbps pattern. For this initial measurement, an
interactive procedure was used to emulate the planned
automated steps. We expect the automated routine will be
more accurate and reliable. Random jitter is about 3ps rms.
Paper 26.3
753
Fig.16a – “Driver6” Data-eye at 2.5Gbps.
Fig.16b – “Driver6” Data-eye at 3.2Gbps.
Fig.17 – “Driver6” Clock-pattern at 5.0Gbps.
4 Receiver Modules
The basic demultiplexing logic implemented for each of the
Receiver channels is illustrated in Fig.18. On the left side,
differential data from the DUT is directed through coaxial
relays to a differential buffer. The outputs from this buffer are
directed to demultiplexing or sampling logic circuits. The
resulting data channels are connected to the ATE, and provide
the sampled data at slower rates suitable for real-time
comparison within the ATE. As with the Driver modules, the
receivers also include relays that permit switching of the
signals directly into tester channels. These are used for DC
parametric measurements of DUT characteristics such as
output voltage sensitivity (VOL/VOH).
In
different
Receiver
modules,
various
demultiplexing or sampling methods are implemented, as
listed in Table 2. In some cases the clock signals are provided
by the ATE, while in others the clocks are generated with
external instruments which are themselves phase-locked with
the ATE. When such external clocking methods are used, it is
necessary to include programmable delay logic within the
module so that the desired clock phase can be obtained.
The ability to capture multi-GHz DUT outputs is
illustrated in Fig.19. This shows the measurement as a shmoo
plot in a fashion similar to Fig.7.
RF Connectors
RF/DC
Select
From
DUT
+
+
- Relays -
Differential
Receiver
+
-
DeMUX
+or
- Sampling
Logic
DC Test
Channels
(to ATE)
D1
D2
D3
D4
Multi-GHz
Clock
Fig.16c – “Driver6” Data-eye at 5.0Gbps.
Paper 26.3
754
Fig.18 – Logic implemented by each of the Receiver
module channels.
Table 2 – Receiver Modules
Design #
Function
#Ch
Fmax
Receiver1
1:4 deMux
8 Diff 2.0 Gbps
Receiver2
1:4 sampler
12 Diff 2.0 Gbps
Receiver3
1:4 ReClk sampler 12 Diff 2.5 Gbps
Receiver4
1:2 sampler
24 SE 1.8 Gbps
Receiver5
1:8 deMux
4 Diff 3.6 Gpbs
Receiver6
1:16 deMux
2 Diff 5.0 Gbps
Receiver7* 1:32 deMux
1 Diff 10.0 Gbps
(* under development)
by Driver6. Furthermore, the 16x multiplexing factor means
that the ATE needs to operate at only 312.5 MHz, which
provides an additional practical advantage.
The ability to accurately measure extremely short bit
periods is illustrated in Fig.20. In Fig.20a a single bit from a
3.2 Gbps serial pattern is shown using 10ps resolution. Here
the measured pulse with is 3.10ns. Likewise, Fig.20b shows a
similar measurement from a 4.0 Gbps signal (measured as
250ps). These are remarkably close to the actual values
(within the measurement resolution of 10ps).
310ps
Fig.19 – Shmoo plot illustrating the Receiver module
capturing 2 Gbps data from a DUT output [10].
Because the Receiver module designs use the same
technology as the Driver modules, the performance achieved
is similar. In some respects, the Receivers are simpler in that
data rates are immediately reduced in the first stages of
sampling or demultiplexing. Therefore most of the Receiver
module logic runs at lower frequencies. Like the Driver
modules, careful selection of high-speed relays and RF
connectors is necessary in order to preserve the DUT output
response signal integrity as it transitions to the Receiver
module. In this respect, the Driver and Receiver designs are
almost identical.
As implied by the similarity between Fig.7 and
Fig.19, the Receivers include sampling logic that is similar to
the embedded calibration logic [patent pending]. Therefore,
the ability to accurately capture sub-nanosecond data bits at
multi-Gbps rates is similar. As shown in [10], the circuits
used for Receivers1, 2, 3, and 4, are able to accurately
measure bits as short as 160ps. The new SiGe-based receivers
are expected to push this limit below 100ps.
The recently developed receiver modules are
designed to match the performance of available Drivers
modules. For example, the 1:16 demultiplexing function of
Receiver6 works to capture 5 Gbps from DUTs that are driven
Fig.20a – Shmoo plot illustrating the Receiver module
capturing 3.2 Gbps data bit using 10ps resoluton.
250ps
Fig.20b – Shmoo plot illustrating the Receiver module
capturing 4.0 Gbps data bit using 10ps resoluton.
Paper 26.3
755
5 Calibration
Clearly the need to control and measure timing of the
Driver and Receiver module signals is critical to the success of
the multi-GHz test system. As described above, each module
includes embedded logic that is dedicated for enabling the
calibration process. These logic blocks require a common
timing reference signal in order to properly deskew the multiGhz signals. At a system level, this is accomplished by using
a low-jitter clock source, phase-locked with the ATE, and
distributing it to each module as illustrated in Fig.21.
Driver
Module
Driver
Module
Driver
Module
Embedded
Calibration
Logic
DUT
Driver
Module
Low-Jitter
RF Source
Receiver
Module
Receiver
Module
Receiver
Module
Receiver
Module
Calibration
Signal
Distribution
Fig.21 – Overview of Calibration signal distribution.
Ideally this signal should be timed to be synchronous
at each module input. However, in practice, the calibration
signal itself will be skewed differently at each module. Part of
the calibration procedure then involves measurement of the
calibration signals input to each module. Once the phases of
the calibration reference signals are known, then these timing
offsets can be factored into the process of determining the
timing delay values needed for each channel. The details of
the calibration process will form the basis for a separate paper.
6 Thermal Management
The power dissipated by each module ranges from 10
to 25 Watts (depending on the logic and number of channels
within the module). Because the critical timing of logic
signals depends on the junction temperature, it is necessary to
control the module temperature to within 1oC. Inititial
prototypes were constructed using aluminum heatsinks with
forced-air construction [10]. Even though these provided the
required level of heat removal, the internal junction
temperature was found to change as the DUT was heated or
cooled. And while the multiplexing test system could be
calibrated to compensate for this effect, the amount of time
needed to reach thermal equillibrium (about 5 minutes) was
unacceptable for production testing. In the final production
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version, the forced-air approach was replaced with a watercooled system (see Fig.4b) which maintained the junction
temperature almost independent of DUT temperature. Figure
22 shows thermocouple measurements taken from the case of
one of the most temperature sensitive parts in Driver5. In
about one minute, the case temperature stablizes to within
0.2oC at about 26.2oC and maintains this throughout an
extensive test lasting a little more than a minute. Depending
on the test-flow and the loadboard design, the module power
can be left on in between parts, so that the one-minute initial
stablization time is incurred only at the beginning of a batch.
Fig.22 – Temperature stabilization for the liquid-cooled
(production) system. The top curve the case temperature of a
critical logic chip. The bottom curve is the temperature of the
returned cooling water.
7
Summary and Conclusions
This paper has presented a modular approach for testing
mulit-GHz digital devices. Furthermore, this approach is
suitable for integration with existing ATE and can provide as
many as 144 independent differential pair signals. A
production system is operational with a maximum channel
data rate of 2.5 Gbps. New designs were demonstrated at 3.2
and 5.0 Gbps. The modular nature of the approach permits
customization of the test system hardware, and optimization
for specific DUT test requirements. While not shown in this
paper, the modular nature of the approach is also suitable for
integrating mixed-signal test resources with these high-speed
digital modules.
8 Acknowledgments
This work was conducted as a joint R&D project between
Gerogia Tech and IBM Canada. The authors are grateful to
IBM engineers for their efforts in designing, constructing, and
testing the thermal management systems. The system-level
experiments were conducted using equipment at the IBM
Canada facility.
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