US 20040216081A1
(19) United States
(12) Patent Application Publication (10) Pub. N0.2 US 2004/0216081 A1
(43) Pub. Date:
Wells et al.
(54)
Oct. 28, 2004
Related US. Application Data
APPLICATION-SPECIFIC TESTING
METHODS FOR PROGRAMMABLE LOGIC
DEVICES
(63)
Continuation of application No. 10/104,324, ?led on
Mar. 22, 2002, Which is a continuation-in-part of
application No. 09/924,365, ?led on Aug. 7, 2001,
noW Pat. No. 6,664,808.
(75) Inventors: Robert W. Wells, Cupertino, CA (US);
Zhi-Min Ling, Cupertino, CA (US);
Publication Classi?cation
Robert D. Patrie, Scotts Valley, CA
(US); Vincent L. Tong, Fremont, CA
(51)
(52)
(US); Jae Cho, Saratoga, CA (US);
Shahin Toutounchi, Pleasanton, CA
Int. C1.7 ................................................... .. G06F 17/50
US. Cl. ................... .. 716/18; 716/16; 716/4; 713/1;
713/100
(Us)
(57)
ABSTRACT
Disclosed are methods for utilizing programmable logic
Correspondence Address:
XILINX, INC
devices that contain at least one localized defect. Such
devices are tested to determine their suitability for imple
menting selected designs that may not require the resources
impacted by the defect. If the FPGA is found to be unsuitable
for one design, additional designs may be tested. The test
ATTN: LEGAL DEPARTMENT
2100 LOGIC DR
SAN JOSE, CA 95124 (US)
(73) Assignee: XilinX, Inc., San Jose, CA (US)
methods in some embodiments employ test circuits derived
from a user’s design to verify PLD resources required for the
(21) Appl. No.:
10/853,981
(22) Filed:
May 25, 2004
design. The test circuits alloW PLD vendors to verify the
suitability of a PLD for a given user’s design Without
requiring the PLD vendor to understand the user’s design.
100
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Patent Application Publication Oct. 28, 2004 Sheet 1 0f 17
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GROSS FUNCTIONAL TEST
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FIG. 1
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APPLICATION-SPECIFIC TESTING METHODS
FOR PROGRAMMABLE LOGIC DEVICES
[0008] Subsequent to fabrication, the various chips on a
given semiconductor Wafer are tested for “gross” defects,
such as poWer-supply shorts, that have a high probability of
CROSS-REFERENCE TO RELATED
APPLICATIONS
rendering a PLD un?t for any customer purpose. In a test
[0001] This application claims priority under 35 U.S.C.
survive gross testing are subjected to a “readback test” to
§119(e) from US. Pat. No. 6,664,808 B2 entitled “A
METHOD OF USING PARTIALLY DEFECTIVE PRO
GRAMMABLE LOGIC DEVICES,” by Zhi-Min Ling et
al., issued on Dec. 16, 2003, Which is incorporated herein by
reference.
FIELD OF THE INVENTION
[0002] The present invention relates to programmable
logic devices, and more particularly to methods for testing
and using programmable logic devices that contain minor
defects.
BACKGROUND OF THE INVENTION
[0003] Programmable logic devices (PLDs), such as ?eld
programmable gate arrays (FPGAs), are user-programmable
integrated circuits that can be programmed to implement
user-de?ned logic circuits. In a typical architecture, an
FPGA includes an array of con?gurable logic blocks (CLBs)
surrounded by programmable input/output blocks (IOBs). A
hierarchy of programmable routing resources interconnects
the CLBs and IOBs. Loading a con?guration bitstream into
con?guration memory cells of the FPGA customiZes these
CLBs, IOBs, and programmable routing resources. Addi
tional resources, such as multipliers, memory, and applica
tion-speci?c circuits may also be included.
[0004]
PLDs are groWing ever larger as vendors attempt to
satisfy customer demand for PLDs capable of performing
ever more complex tasks. Unfortunately, as chip siZe
increases, so too does the probability of ?nding a defect on
a given chip. The process yield therefore decreases With
PLD complexity, making already expensive PLDs still more
expensive.
verify the function of the con?guration memory cells.
Defect-free chips are subjected to further testing to ensure
?aWless performance, While chips that exhibit a large num
ber or dense concentration of readback defects are rejected.
Chips With relatively feW defects are set-aside as “ASIC
candidates” and are subjected to further testing. Unlike the
general tests normally performed to verify PLD functional
ity, in one embodiment the ASIC candidates are subjected to
application-speci?c tests that verify the suitability of each
candidate to function With one or more speci?c customer
designs.
[0009] Some test methods in accordance With embodi
ments of the invention employ test circuitry derived from a
user design to verify PLD resources required for the design.
These methods verify the suitability of an FPGA for a given
design Without requiring an understanding of the design, and
therefore greatly reduce the expense and complexity of
developing design-speci?c tests for a user design. Also
advantageous, narroWing test scope to those resources
required for a given design reduces the time required for
testing and increases the number of saleable PLDS. Using
test circuits other than the user design to test the resources
required for the user design facilitates comprehensive testing
Without requiring an understanding of the user design.
[0010]
The foregoing test methods Will not forestall PLD
vendors from selling fully tested, defect-free PLDs. Cus
tomers Will still require defect-free PLDs to develop cus
tomer-speci?c designs and to bring these designs to market
quickly. HoWever, once a customer has a speci?c design, the
aforementioned test procedures can provide reduced-cost
PLDs that are physically and functionally identical to the
fully functional PLD or PLDS ?rst used to develop the
customer-speci?c design.
[0005] PLDS are not design speci?c, but instead afford
users (e.g., circuit designers) the ability to instantiate an
almost unlimited number of circuit variations. Not knoWing
in advance the purpose to Which a given PLD Will be
dedicated places a heavy burden on the quality and reliabil
ity of the PLD because PLD vendors must verify the
functionality of any feature that might be used. To avoid
disappointing customers, PLD manufacturers discard PLDS
that include even relatively minor defects.
[0006]
methodology applicable to SRAM-based FGPAs, chips that
PLD defects can be categoriZed in tWo general
areas: gross defects that render the entire PLD useless or
unreliable, and localiZed defects that damage a relatively
small percentage of the PLD. It has been found that, for
[0011] In accordance With one embodiment of the inven
tion, a customer interested in the potential cost savings
associated With recovered PLDs Will send an expression of
the customer-speci?c design (e.g., a data ?le) to the PLD
vendor. The vendor Will then use the expression to test ASIC
candidates in the manner described above. ASIC candidates
that are physically and functionally identical to the defect
free PLD ?rst used to instantiate the customer-speci?c
design can then be sold to the customer at reduced cost.
[0012] This summary does not limit the scope of the
invention, as the scope of the invention is de?ned by the
claims.
some large chips, close to tWo thirds of the chips on a given
Wafer may be discarded because of localiZed defects. Con
sidering the costs associated With manufacturing large inte
grated circuits, discarding a large percentage of PLD chips
has very signi?cant adverse economic impact on PLD
manufacturers.
SUMMARY
[0007] The present invention enables PLD manufactures
to identify PLDs that, despite some defects, can ?aWlessly
implement selected customer designs.
BRIEF DESCRIPTION OF THE FIGURES
[0013] FIG. 1 is a How chart 100 shoWing one embodi
ment of the present invention as applied to FPGAs. Subse
quent to fabrication, the various chips on a given semicon
ductor Wafer are tested for “gross” defects (step 105).
[0014] FIG. 2 is a block diagram of a conventional FPGA
200 in Which is instantiated an illustrative user design.
[0015]
FIG. 3 is a ?oWchart detailing the design-speci?c
test step 121 of FIG. 1.
Oct. 28, 2004
US 2004/0216081 A1
[0016] FIG. 4 depicts an exemplary net under test 400 and
associated signal source 405 and destination circuits 410 and
415.
standing of embodiments of the present invention. HoWever,
[0017]
invention may be practiced Without these speci?c details. In
other instances, Well-knoWn features have not been
described in detail in order to avoid obscuring the present
FIG. 5 depicts an FPGA 500 in Which the CLBs,
IOBs, and RAM block of the user design of FIG. 2 are
shaded.
[0018] FIGS. 6A through 6D depict portions of circuit
designs that can be instantiated on an FPGA to verify
RAM-block functionality.
[0019]
FIG. 7 schematically depicts a test circuit 700
adapted to verify the speed performance of a critical path
705 of a hypothetical user design.
[0020]
FIG. 8 depicts a test circuit 800 that can be used in
accordance With the invention to perform at-speed func
tional tests of FPGA resources, including internal memory
and routing resources.
[0021] FIG. 9 depicts a test circuit 900 in accordance With
another embodiment of the invention.
[0022] FIG. 10 depicts a test circuit 1000 in accordance
With yet another embodiment of the invention.
[0023] FIG. 11 schematically depicts counter 1020A of
FIG. 10 (counter 1020B is identical).
[0024] FIG. 12 schematically depicts an embodiment of
LFSR 1030A of FIG. 10 (LFSR 1030B is identical to LFSR
1030A, except that line /FE-CNT connects instead to line
/LD-CNT).
[0025]
FIG. 13 schematically depicts an embodiment of
MSB comparator 1050A of FIG. 10.
[0026] FIG. 14 depicts an example of clock generator
1010 of FIG. 10.
[0027] FIG. 15 depicts another type of clock generator
1500 for use in the present invention.
[0028] FIG. 16 depicts an embodiment of signature ana
lyZer 1040 of FIG. 10.
ci?c details are set forth to provide a more thorough under
it Will be apparent to one skilled in the art that the present
invention.
[0036] FIG. 1 is a How chart 100 shoWing one embodi
ment of the present invention as applied to FPGAs. Subse
quent to fabrication, the various chips on a given semicon
ductor Wafer are tested for “gross” defects (step 105). For
purposes of the present disclosure, “gross” defects are
defects that have a high probability of rendering a PLD un?t
for any customer purpose. Examples of gross defects include
poWer-supply shorts, opens, excessive leakage, defective
clock-management circuitry, and signi?cant numbers of
defective programmable memory cells. Chips With gross
defects are discarded (decision 107). Various tests for gross
defects are described in chapter 14 of “Application-Speci?c
Integrated Circuits,” by Michael John Sebastian Smith
(1997), Which is incorporated herein by reference.
[0037] Chips that survive decision 107 are subjected to a
“readback test” to verify the function of the con?guration
memory cells (decision 109). In this step, con?guration
memory is programmed to include various patterns of con
?guration data and then read back to verify the correct
program states of those cells. In one embodiment, chips are
rejected if they have a large number or concentration of
defects. The number considered “large” Will depend upon
the siZe of the PLD in question and the distribution of the
defects, as these parameters determine the likelihood of such
defects rendering a PLD useless for instantiating customer
designs (also referred to as “user designs”).
[0038] At decision 109, defective chips With greater than
the maximum alloWable number of defects are discarded,
chips With no defects are sent on to step 111 for compre
hensive testing, and defective chips With a number of defects
less than the maximum alloWed number are identi?ed as
“ASIC candidates”(step 113). ASIC candidates are those
FIG. 17 shoWs hoW test circuit 1000 of FIG. 10
chips that, though imperfect, may have adequate resources
can be scaled to test additional resources on a given FPGA.
to instantiate some user designs. Other embodiments might
separate ASIC candidates based on their likelihood of suc
cess at implementing a user design. For example, a device
[0029]
[0030]
FIG. 18 details MSB comparator 1050B ?rst intro
duced in FIG. 10.
[0031] FIG. 19 schematically depicts a test circuit 1900
that includes N minor test circuits 1905(1)-1905(N), each
comprised of a circuit portion 1000 and an associated MSB
With only one defect might be considered more valuable
than a device With ?ve defects.
[0039]
Those PLDs having no identi?ed defects through
decision 109 are thoroughly tested to ensure conformance to
comparator (see FIG. 10).
strict performance criteria. Circuit vendors must verify both
[0032] FIG. 20 schematically depicts a test circuit 2000
that employs M column instances 1910(1)-1910(M) to popu
functional chips are identi?ed as good devices (step 115).
late every roW and column of a VirtexTM FPGA.
These chips are then packaged (step 117) and the resulting
[0033]
FIG. 21 is a schematic diagram of a “slice”2100,
one of tWo identical slices that make up an exemplary CLB
in the VirtexTM family of devices available from Xilinx, Inc.
[0034] FIGS. 22A-22D depict four FPGA con?gurations
for instantiating test circuit 2000 of FIG. 20 on an exem
plary FPGA 2200.
DETAILED DESCRIPTION
[0035] The present invention relates to programmable
logic devices. In the folloWing description, numerous spe
speed performance and functionality of each device. Fully
PLDS are subjected to the same series of tests as Were the
unpackaged chips, beginning once again at step 105. The
tests are run again to ensure no defects Were introduced by
or during the packaging process. If a packaged chip is defect
free, the process Will eventually return to step 115 and the
packaged PLD Will be binned accordingly and sold to a
customer (step 118). Although not shoWn, the conventional
test process for PLDs additionally includes speed binning.
[0040]
Chips that are less than fully functional, but that
nevertheless survived decisions 107 and 109, are identi?ed
as “ASIC candidates” (step 113). Unpackaged ASIC candi