Christopher W. Fletcher
Contact
E-mail: cwfletch@mit.edu
Affiliation
Massachusetts Institute of Technology
Computer Science and Artificial Intelligence Lab (CSAIL)
Address
Ray and Maria Stata Center, 32-G884
32 Vassar Street, Cambridge, Massachusetts
Education
Massachusetts Institute of Technology
Website: http://cwfletcher.net
Last updated: November, 2015
2016 (Expected)
Ph.D., Electrical Engineering and Computer Science
Advisor: Srini Devadas
Massachusetts Institute of Technology
May 2013
S.M., Electrical Engineering and Computer Science
Thesis: “Ascend: An Architecture for Performing Secure Computation on Encrypted Data”
Advisor: Srini Devadas
The University of California, Berkeley
May 2010
B.S., Electrical Engineering and Computer Science
Advisor: John Wawrzynek
Viewpoint School, Calabasas
Jun 2006
{Elementary, High} School Diplomas
Awards and
Distinctions
Research
ACSC’13 Best Poster Presentation Award, Second Place
2013
CCS’13 Best Student Paper Award
2013
Ascend processor named one of ten “world changing ideas” by Scientific American
2013
National Defense Science and Engineering Graduate Fellowship
Funding years: 2012-2015
National Science Foundation Graduate Research Fellowship
Funding years: 2011
ICS’10 Best Student Paper Award
2010
UC Berkeley, graduated with High Honors (GPA: 3.91/4)
2010
Golden Key (member)
Inducted 2008
Rose Hills Science and Engineering Scholarship
2007-2008
Tau Beta Pi, UC Berkeley CA Alpha Chapter (member)
Inducted 2007
Eta Kappa Nu (invited)
2007
National Society of Collegiate Scholars
2006
UC Berkeley Edward Frank Kraft Scholarship
2006
VSSA Award (Community Service Distinction)
2006
Cum Laude Society, Honor Society (member)
Inducted 2006
CORE, Community Service Honor Society (member)
Inducted 2005
1. Research Assistant
Affiliation: MIT; CSAIL; Computation Structures Group
Advisor(s): Srini Devadas
Fall 2010 - Present
2. Undergraduate Researcher
Spring 2008 - Spring 2010
Affiliation: U.C. Berkeley; BWRC, ParLab; RAMP, Berkeley Reconfigurable Group
Advisor(s): John Wawrzynek, Garry Nolan, Greg Gibeling, Narges Asadi
Teaching
CS61A: Structure and Interpretation of Computer Programs, U.C. Berkeley
CS150: Components and Design Techniques for Digital Systems, U.C. Berkeley
6.S092: Introduction to Software Engineering in Java (IAP), M.I.T.
6.172: Performance Engineering of Software Systems, M.I.T.
1. Teaching Assistant (Student Approval Rating: 6.7/7)
6.172; under: Charles Leiserson and Saman Amarasinghe
2. Instructor
6.S092; with: Anirudh Sivaraman and Kasia Hayden
Industry
January 2012
3. Teaching Assistant (Student Approval Rating: 5/5)
CS150; under: John Wawrzynek
Spring 2010
4. Teaching Assistant (Student Approval Rating: 4.7/5)
CS150; under: John Wawrzynek
Spring 2009
5. Head Teaching Assistant (Student Approval Rating: 4.8/5)
CS150; under: Kris Pister
Fall 2008
6. Grader
CS61A; under: Brian Harvey
Fall 2007
7. Lab Assistant
CS61A; under: Brian Harvey
Spring 2007
1. Co-founder, President of Oblivilock Inc.
Sum 2015 - Present
Accepted into the inaugural class of the Cyber Security Factory, a startup accelerator run by venture
capital firm Highland Capital Partners.
2. Software Engineering Intern
Oracle Corporation; Project: JDeveloper-JIRA Connector
Volunteer
Fall 2013
Sum 2008
1. Corporate Liaison Committee Chair
The Engineers’ Joint Council
2006 - 2008
2. Mentor, Media Literacy Program Director
The Zeitgeist Community Learning Center
2005 - 2007
3. School Representative, Organizer
The ALS Association - Greater Los Angeles Chapter
2005 - 2006
Peer-Reviewed 1. S. Devadas, M. V. Dijk, C. W. Fletcher, L. Ren, E. Shi, and D. Wichs. “Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM”. Proceedings of the 13th IACR Theory of Cryptography
Publications
Conference (TCC), 2016. (Alphabetical authors, L. Ren and I shared lead author)
2. L. Ren, C. W. Fletcher, A. Kwon, E. Stefanov, E. Shi, M. V. Dijk, and S. Devadas. “Constants
Count: Practical Improvements to Oblivious RAM”. Proceedings of the 24th USENIX Security
Symposium (USENIX Security), 2015.
3. X. Yu, S. K. Haider, L. Ren, C. W. Fletcher, A. Kwon, M. V. Dijk, and S. Devadas. “PrORAM: Dynamic Prefetcher for Oblivious RAM”. Proceedings of the 42nd International Symposium
on Computer Architecture (ISCA), 2015.
4. C. W. Fletcher, L. Ren, A. Kwon, M. V. Dijk, E. Stefanov, D. Serpanos, and S. Devadas. “A
Low-Latency, Low-Area Hardware Oblivious RAM Controller”. Proceedings of the 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015.
5. C. W. Fletcher, L. Ren, A. Kwon, M. V. Dijk, and S. Devadas. “Freecursive ORAM: [Nearly]
Free Recursion and Integrity Verification for Position-based Oblivious RAM”. Proceedings of the
20th International Conference on Architectural Support for Programming Languages and Operating
Systems (ASPLOS), 2015.
6. C. W. Fletcher, L. Ren, X. Yu, M. V. Dijk, O. Khan, and S. Devadas. “Suppressing the Oblivious
RAM Timing Channel While Making Information Leakage and Program Efficiency Trade-offs”.
Proceedings of the 20th IEEE International Symposium On High Performance Computer Architecture
(HPCA), 2014.
7. E. Stefanov, M. V. Dijk, E. Shi, C. W. Fletcher, L. Ren, X. Yu, and S. Devadas. “Path ORAM: An
Extremely Simple Oblivious RAM Protocol”. Proceedings of the 20th ACM Conference on Computer
and Communications Security (CCS), 2013. Best Student Paper Award
8. X. Yu, C. W. Fletcher, L. Ren, M. V. Dijk, and S. Devadas. “Generalized External Interaction
with Tamper-Resistant Hardware with Bounded Information Leakage”. Proceedings of the 5th ACM
Cloud Computing Security Workshop (CCSW), 2013.
9. C. W. Fletcher, R. Harding, O. Khan, and S. Devadas. “A Framework to Accelerate Sequential
Programs on Homogeneous Multicores”. Proceedings of the 21st International Conference on Very
Large Scale Integration (VLSI-SoC), 2013.
10. L. Ren, C. W. Fletcher, X. Yu, M. V. Dijk, and S. Devadas. “Integrity Verification for Path
Oblivious-RAM”. Proceedings of the 17th IEEE High Performance Extreme Computing Conference
(HPEC), 2013.
11. L. Ren, X. Yu, C. W. Fletcher, M. V. Dijk, and S. Devadas. “Design Space Exploration and
Optimization of Path Oblivious RAM in Secure Processors”. Proceedings of the 40th International
Symposium on Computer Architecture (ISCA), 2013.
12. C. W. Fletcher, M. V. Dijk, and S. Devadas. “Towards an Interpreter for Efficient Encrypted Computation”. Proceedings of the 4th ACM Cloud Computing Security Workshop, held in conjunction
with CCS (CCSW), 2012.
13. C. W. Fletcher, M. V. Dijk, and S. Devadas. “A Secure Processor Architecture for Encrypted
Computation on Untrusted Programs”. Proceedings of the 7th ACM Workshop on Scalable Trusted
Computing, held in conjunction with CCS (STC), 2012.
14. P. Ren, M. Lis, M. H. Cho, K. S. Shim, C. W. Fletcher, O. Khan, N. Zheng, and S. Devadas.
“HORNET: a cycle-level multicore simulator”. Proceedings of the IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems (TCAD), 2012.
15. C. W. Fletcher, R. Harding, O. Khan, S. Devadas. “A Low-overhead Dynamic Optimization
Framework on Multicores”. Proceedings of the IEEE/ACM International Conference on Parallel
Architectures and Compilation Techniques (PACT), 2012.
16. I. Lebedev, C. W. Fletcher, S. Cheng, J. Martin, A. Doupnik, D. Burke, M. Lin, and J. Wawrzynek.
“Exploring Many-core Design Templates for FPGAs and ASICs”. Appears in the International
Journal of Reconfigurable Computing (IJRC), 2012. Invited paper.
17. M. Lis, P. Ren, M. H. Cho, K. S. Shim, C. W. Fletcher, O. Khan, and S. Devadas. “Scalable Accurate Multicore Simulation in the 1000 core era”. Proceedings of the IEEE International Symposium
on Performance Analysis of Systems and Software (ISPASS), 2011.
18. M. Lis, K. S. Shim, M. H. Cho, C. W. Fletcher, M. Kinsy, I. Lebedev, O. Khan, and S. Devadas.
“Brief Announcement: Distributed Shared Memory based on Computation Migration”. Proceedings
of the 23rd Symposium on Parallelism in Algorithms and Architectures (SPAA), 2011.
19. I. Lebedev, C. W. Fletcher, S. Cheng, J. Martin, A. Doupnik, D. Burke, M. Lin, and J. Wawrzynek.
“Exploring Many-core Design Templates for FPGAs and ASICs”. Appears in the International
Journal of Reconfigurable Computing (IJRC), 2011.
20. C. W. Fletcher, I. Lebedev, N. B. Asadi, D. Burke, J. Wawrzynek. “Bridging the GPGPU-FPGA
Efficiency Gap”. Proceedings of the 19th International Symposium on Field-Programmable Gate
Arrays (ISFPGA), 2011.
21. I. Lebedev, S. Cheng, A. Doupnik, J. Martin, C. W. Fletcher, D. Burke, M. Lin, J. Wawrzynek.
“MARC: A Many-Core Approach to Reconfigurable Computing”. Proceedings of the 6th International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2010.
22. N. B. Asadi, C. W. Fletcher, G. Gibeling, E. N. Glass, K. Sachs, D. Burke, Z. Zhou, J. Wawrzynek,
W. H. Wong, and G. P. Nolan. “ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs”. Proceedings of the 24th International Conference on Supercomputing
(ICS), 2010. Best Student Paper Award. (N. B. Asadi and I shared lead author)
Patents
1. S. Devadas, C. W. Fletcher, M. V. Dijk. “Technique for secure computation”. Patent No 8909967.
Theses
1. C. Fletcher. “Ascend: An Architecture for Performing Secure Computation on Encrypted Data”.
CSG Technical Memo 508 (CSAIL), http://csg.csail.mit.edu/pubs/publications.html. S.M. Thesis
Articles
1. G. E. Suh, C. W. Fletcher, D. Clarke, B. Gassend, M. V. Dijk, S. Devadas. “[Author Retrospective] AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing”. 25 Years of the
International Conference on Supercomputing (ICS), 2014.
2. C. W. Fletcher, M. V. Dijk, S. Devadas. “Let’s Stop Trusting Software With Our Sensitive Data”.
EEE Design and Test of ICs (D&T), 2013.
Selected Press 1. “Cybersecurity Factory nurtures early-stage startups in a tough field.” Fortune. [Article link].
2. “The Quest to Rescue Security Research From the Ivory Tower.” Wired. [Article link].
3. “Cloud security reaches silicon.” MIT News. [Article link].
4. “Hardware Trick Could Keep Cloud Data Safe.” IEEE Spectrum. [Article link].
5. “Devadas hardware disguises cloud servers memory-access patterns thwarting timing attacks.” CSAIL
News. [Article link].
6. “Protecting data in the cloud.” MIT News. [Article link].
7. “A New Type of Security Chip Guards Against Big Data Snooping.” Scientific American. [Article
link]. Ascend named one of ten “World Changing Ideas” in 2013!
Talks
1. Constants Count: Practical Improvements to Oblivious RAM.
“ORAMorama” Technical Session at the 24th Usenix Security Symposium, Washington D.C. (8/13/2015)
2. Tiny ORAM: A Low-Latency, Low-Area Hardware Oblivious RAM Controller.
“Implementation I” Technical Session at the 23rd IEEE Intl. Sym. on Field-Programmable Custom
Computing Machines, Vancouver, Canada (5/2/2015)
3. Onion ORAM: Constant Bandwidth ORAM using Additively Homomorphic Encryption.
ORAM Day at Boston University, Boston, Massachusetts (1/30/2015)
Charles River Crypto Day at Northeastern University, Boston, Massachusetts (4/17/2015)
UBC Seminar, Vancouver, Canada (5/3/2015)
4. Hardware Security in Cloud Computing.
Presented at the Annual CSAIL Alliance Program meeting, Cambridge (4/30/2014)
5. Suppressing the Oblivious RAM Timing Channel While Making Information Leakage and Program
Efficiency Trade-offs.
“Security and Cloning” Technical Session at the 20th Intl. Sym. on High Performance Computer
Architecture, Orlando, Florida (2/18/2014)
6. Towards an Interpreter for Efficient Encrypted Computation.
4th ACM Cloud Computing Security Workshop (CCSW), Raleigh, North Carolina (10/19/2012)
7. A Secure Processor Architecture for Encrypted Computation on Untrusted Programs.
7th ACM Workshop on Scalable Trusted Computing (STC), Raleigh, North Carolina (10/15/2012)
8. Techniques for Performing Secure Computation on Encrypted Data.
NSA-CSAIL visit, Cambridge, Massachusetts (9/19/2012)
MIT CSAIL security seminar series, Cambridge, Massachusetts (10/1/2012)
Northrop Grumman-CSAIL visit, Cambridge, Massachusetts (10/25/2012)
Boston University security (BUSec) seminar series, Cambridge, Massachusetts (12/10/2012)
Lincoln Laboratory talk, Lexington, Massachusetts (2/4/2013)
9. Bridging the GPGPU-FPGA Efficiency Gap.
“FPGA Arch. and Tech.” Tech. Session at the 19th ISFPGA, Monterey, California (2/28/2011)
10. ParaLearn: A massively parallel, scalable system for learning interaction networks on FPGAs.
“Applications” Technical Session at the 24th ICS, Tsukuba, Japan (6/2/2010)
11. Scalable Bayesian Network Discovery with Reconfigurable Hardware.
RAMP Winter Retreat, U.C. Santa Cruz (1/28/2010)
BWRC Winter Retreat, Lake Tahoe (1/10/2010)
12. Reconfigurable Computing & Bayesian Networks.
GSRC Annual Research Symposium, San Jose (9/3/2009)
13. Introduction to GateLib & MCMC on the BEE3.
Nolan Lab “All Hands Meeting”, Stanford (6/15/2009)
Posters
1. Onion ORAM: A Constant Bandwidth Blowup Oblivious RAM.
Cybersecurity@CSAIL Annual Meeting, Cambridge (9/29/2015)
2. Ascend: An Architecture for Performing Secure Computation on Encrypted Data.
International Conferences on ASPLOS, Istanbul (3/12/2015)
Annual CSAIL Alliance Program meeting, Cambridge (4/30/2014)
ACSC Annual Conference, Boston (11/12/2013) Best Poster Presentation Award, Second Place.
3. A Low-overhead Dynamic Optimization Framework on Multicores.
International Conference on VLSI-SoC, Istanbul (10/6/2013)
IEEE/ACM International Conference on PACT, Minneapolis (9/20/2012)
4. Bridging the GPGPU-FPGA Efficiency Gap.
International Symposium on FPGAs, Monterey (2/28/2011)
5. Scalable FPGA Solutions for Learning Bayesian Networks.
BWRC Summer Retreat, U.C. Berkeley (6/6/2010)
BWRC Winter Retreat, Lake Tahoe (1/10/2010)
6. Curing Cancer with RCBIOS.
RAMP Summer Retreat, U. T. Austin (6/23/2009)
7. flint.
RAMP Winter Retreat, U.C. Berkeley (1/10/2009)
References
Srinivas Devadas (advisor)
Edwin Sibley Webster Professor of EECS at MIT
Founder, Chief Technology Officer and Board Member at Verayo
devadas@mit.edu
Charles Leiserson
Edwin Sibley Webster Professor of EECS at MIT
cel@mit.edu
Elaine Shi
Associate Professor of CS at Cornell University
elaine@cs.cornell.edu
Marten van Dijk
Associate Professor of ECE at the UConnecticut, Storrs
vandijk@engr.uconn.edu
David Wentzlaff
Assistant Professor of EE at Princeton University
wentzlaf@princeton.edu
Daniel Wichs
Assistant Professor of CS at Northeastern University
wichs@ccs.neu.edu