APPLIED PHYSICS LETTERS
VOLUME 84, NUMBER 26
28 JUNE 2004
Mobility studies of field-effect transistor structures based
on anthracene single crystals
A. N. Aleshina)
School of Physics and Condensed Matter Research Institute, Seoul National University,
Seoul 151-747, Korea and A. F. Ioffe Physical-Technical Institute, Russian Academy of Sciences,
St. Petersburg 194021, Russia
J. Y. Lee, S. W. Chu, J. S. Kim, and Y. W. Park
School of Physics and Condensed Matter Research Institute, Seoul National University,
Seoul 151-747, Korea
(Received 5 February 2004; accepted 5 May 2004; published online 17 June 2004)
The charge carrier transport in anthracene single crystals has been studied by means of field-effect
transistor 共FET兲 structure. The FET mobility 共␮FET兲 revealed the nonmonotonous, reliant on
gate-voltage 共Vg兲, temperature dependence with the maximum ␮FET ⬃ 0.02 cm2 / V s at T
⬃ 170– 180 K and Vg ⬃ −30 V. At temperatures below 180 K the mobility decreases and becomes
thermally activated with the Vg-dependent activation energy Ea ⬃ 40– 70 meV governed by shallow
traps. The space-charge-limited current is the dominant transport mechanism in FET structures
based on anthracene single crystals. © 2004 American Institute of Physics.
[DOI: 10.1063/1.1767282]
parent crystals with a typical size ⬃1 ⫻ 2 mm and thickness
of around 10– 30 ␮m are selected for mobility studies. The
substrates used for the FET structures are highly doped
n-type Si wafers with a ⬃200-nm-thick thermally grown
SiO2 layer. Gold electrodes are deposited on top of the SiO2
by means e-beam lithography with the channel length
- 5 ␮m and the channel width - 4 cm. SiO2 is cleaned prior
to placing the anthracene single crystal on top of the substrate. To improve the electrical contact between the gold
pads and the molecular crystal, the substrate is treated in a
solution of 10 mM nitrobenzenethiol in acetonitrile. Such
treatment significantly reduces the contact resistance, which
is crucial for the low-temperature measurements.15 After the
surface treatment anthracene single crystal is placed on top
of the substrate, covered with polymer dielectric film—
poly(dimethyl silaxan) 共PDMS兲—to protect from air and
pressed by screw to establish the best electrical contact. The
schematic of a FET structure fabricated following this procedure is shown in the inset to Fig. 1. The current–voltage
Organic field-effect transistors 共FET兲 based on thin-film
technologies have received considerable attention within the
last decades.1,2 As a result the room temperature field-effect
mobility 共␮FET兲 for the best organic thin film transistors
achieved ␮FET ⬃ 1.5 cm2 / V s,3 which is comparable with
that of amorphous silicon FETs.4 Since FET mobility increases with increasing crystallinity in thin-film FETs, there
is every reason to expect that FETs made on the surface of
free-standing single crystals of organic molecules is the
promising route to produce high-mobility devices suitable
for practical applications. However, unlike thin film FETs,
the investigation of single crystal organic FETs is still rare.
Only a few results on tetracene, pentacene, and rubrene molecular crystals FETs have been reported recently.5–12 At the
same time such typical molecular crystal as anthracene is
still out of this activity. Anthracene C14H10 is a molecular
solid with a band energy gap Eg ⬃ 3.9 eV composed of molecules which held together by weak van der Waals forces,
thus it has rather low melting point 共⬃217 ° C兲 and poor
electrical conductivity.13 The mobility behavior obtained
from FET structures based on anthracene single crystals
could provide a important information for a general understanding of charge carrier transport in molecular crystals.
In this letter we report on fabrication and characterization of FET structures based on anthracene single crystals.
The field-effect mobility studied over the temperature range
T = 100– 310 K has nonmonotonous temperature dependence
and reaches the maximum value ␮FET ⬃ 0.02 cm2 / V s at T
⬃ 170– 180 K, which is comparable to those reported for
regular thin films organic FETs. The observed low temperature mobility behavior is consistent with the thermally activated transport governed by shallow traps.
Anthracene single crystals were grown by means of
physical vapor deposition in the vertical furnace in a helium
atmosphere similar to that described in Ref. 14. The temperatures of anthracene powder and crystal zone were 170 and
100 ° C, respectively. The heating time was 24 h. The trans-
FIG. 1. log ISD versus log VSD at 220 K at different gate bias for the FET
structure based on anthracene single crystal; arrows indicate VTFL. Inset
shows the schematic of a single crystal anthracene FET.
a)
Electronic mail: aleshin@phya.snu.ac.kr
0003-6951/2004/84(26)/5383/3/$20.00
5383
© 2004 American Institute of Physics
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5384
Appl. Phys. Lett., Vol. 84, No. 26, 28 June 2004
共I – V兲 characteristics are measured in vacuum ⬃10−5 Torr
within the temperature range 100– 310 K with a Keithley
SCS4200 semiconductor characterization system. The gateinduced leakage current of gold electrodes prior to anthracene single crystal attachment is found to be ⬃10−10 A. To
increase the accuracy, source, drain, and gate, is shorted before each measuring cycle.
Figure 1 shows the typical plot of log ISD versus log VSD
for anthracene single crystal measured at 220 K along the c
axis at different gate voltages Vg. The I – V characteristics at
220 K are superlinear and similar to those at 300 K, but the
ISD at 220 K is much higher (see the following for details).
n
As can be seen from Fig. 1, for our samples ISD ⬃ VSD
, where
n is strongly gate-voltage dependent and varies from
n ⬃ 16.4 at Vg = 0 V down to n ⬃ 6.1 at Vg = −40 V. It means
that the observed I – V behavior is characteristic of a trapfilled regime of the space-charge-limited current 共SCLC兲
transport mechanism.13–16 This I – V behavior coincides with
the previous results for pristine anthracene single crystals,
where SCLC transport has been considered as the main
one.13 SCLC theory predicts the crossover from the Ohmic
regime (at low voltages) to the rather narrow SCLC regime
governed by a shallow-traps 共I ⬃ Vn , n ⬃ 2兲 and finally to a
trap-filled regime 共I ⬃ Vn , n Ⰷ 2兲 with an increase of bias
voltage. In our case the two former regimes are apparently
under the leakage current limit, whereas the latter regime
manifests itself clearly. The voltage of the trap-filling limit is
given by VTFL = 2eL2Nt / 3␧r␧0, where ␧0 is the permittivity of
free space and ␧r is the relative dielectric constant of the
active layer (for anthracene crystal ␧r = 3.2),13 Nt is the trap
concentration, and L is the distance between electrodes. The
trap concentration at 300 K obtained for our samples from
the VTFL value at Vg = 0 V is of the order Nt ⬃ 1014 cm−3
which is reasonable for the pristine anthracene crystal. As
can be seen from Fig. 1, application of negative gate voltage
affects VTFL significantly. Namely, negative Vg shifts the
VTFL at 220 K to the lower values that implies the decrease
from
3 ⫻ 1014 cm−3共Vg = 0 V兲
down
to
of
Nt
13
−3
5 ⫻ 10 cm 共Vg = −40 V兲 as a result of gating. It means that
the SCLC mechanism in the trap-filled regime remains the
dominant one at both room and low temperatures. One may
suggest that the sharp rise of ISD at VTFL cannot be attributed
to simply bulk trap filling. The high field can also produce
trap-emptying results in some finite slop of I – V curves.
The obtained data demonstrate that the ISD increases significantly due to hole injection by the negative Vg, whereas
positive gate voltage does not affect it so much. The effect of
negative gate voltage becomes more pronounced as temperature decreases down to ⬃200 K [Fig. 2(a)] but it decreases
gradually below 200 K [Fig. 2(b)]. The inset to Fig. 2(b)
shows the low temperature 共T ⬍ 200 K兲 dependence of
log ISD versus Vg at VSD = 50 V for the same FET structure.
The on/off ratio calculated within the whole temperature
range as the ratio between the source–drain current at
Vg = −30 V (on) and at Vg = 10 V (off) is shown in the inset to
Fig. 2(a). Despite the on/off values and the sharpness at room
temperature being rather low, one may note that they rise to
higher values up to ⬃104 at T ⬍ 200 K. As can be seen from
the inset to Fig. 2(b), the field-effect onset at T ⬍ 200 K has
occurred at both positive (at T = 200 K) and negative (at T
= 110 K) Vg. Thereby the quality of the insulator/
semiconductor interface can be characterized by the sharp-
Aleshin et al.
FIG. 2. ISD vs Vg at T ⬎ 200 K (a) and T ⬍ 200 K (b). Insets show the on/off
ratio vs T (a) and log ISD vs T at T ⬍ 200 K (b) for the same SC FET
structure.
ness of the field-effect onset, S = dVg / d共log ISD兲, and by the
normalized slope, Si = SCi, which takes into account the capacitance of the insulator layer per unit area Ci. Our anthracene single crystal FET exhibits a subthreshold slope S
⬃ 6.6 V / decade at T = 170 K, which corresponds to Si
⬃ 79 V nF/ decade cm2 共Ci ⬃ 12 nF/ cm2兲.17 This value is
comparable to that found for the pentacene thin film and
single crystal FETs- Si ⬃ 15– 80 V nF/ decade cm2 at
300 K.5,11,18
The charge carrier mobility is obtained at each temperature from the transconductance, gm, characteristics: gm
= 共⳵ISD / ⳵Vg兲兩VSD=const = −共Z / L兲␮FETCiVSD. Z is the channel
width, L is the channel length, and Ci is the capacitance per
unit area.17 Typical temperature dependencies of the FET
mobility, ␮FET共T兲, at different gate voltages are shown in
Fig. 3(a). As can be seen the temperature dependence of FET
mobility is nonmonotonous and strongly gate-voltagedependent. The mobility increases reaching the maximum at
T ⬃ 170– 250 K (depends on Vg) and then decreases with further temperature decrease. The maximum of ␮FET
⬃ 0.02 cm2 / V s is obtained at T ⬃ 170– 180 K at sufficiently
large gate voltage Vg = −30 V. The same data plotted as
log ␮FET versus 103 / T are presented in Fig. 3(b). It is noteworthy that such nonmonotonous ␮FET共T兲 dependence is
similar to that reported recently for tetracene single crystal
FETs5,6 and moreover at T ⬎ 200 K it is typical of band-like
transport in organic crystals. At the same time ␮FET共T兲 is not
consistent with that usually observed in organic thin film
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Aleshin et al.
Appl. Phys. Lett., Vol. 84, No. 26, 28 June 2004
5385
quasicontinuous trap distribution to the imperfection of the
crystal structure. One may suggest that both chemical and
structural traps are present to some extent in anthracene crystals. However because we did not introduce any specific impurities or dopants into the crystals, one can expect that
structural traps related to some irregularities of the lattice are
dominant and affect I – V characteristics. Further improvement of the anthracene crystal quality and the anthracene–
SiO2 interface may result in more pronounced I – V characteristics and higher mobility values.
In conclusion, we have studied the charge carrier transport in anthracene single crystals by means of field-effect
transistor structure. The FET mobility revealed the nonmonotonous temperature dependence with the maximum
mobility ␮FET ⬃ 0.02 cm2 / V s at T ⬃ 170– 180 K and
Vg ⬃ −30 V. At temperatures below 180 K the mobility decreases and becomes thermally activated with Vg-dependent
activation energy Ea ⬃ 40– 70 meV governed by shallow
traps. The space-charge-limited current is the dominant
transport mechanism in FET structures based on anthracene
single crystals.
The authors are grateful to M. Schaer for help with anthracene crystals storage. This work was supported by
KISTEP, under Contract No. M6-0301-00-0005, Korea. Support from the Brain Pool Program of Korean Federation of
Science and Technology Societies for A.N.A. is gratefully
acknowledged.
1
FIG. 3. Mobility vs T (a) and 1000/ T (b) at different Vg for anthracene SC
FET. Inset shows Ea vs Vg at T ⬍ 200 K for the same structure.
FETs, where the mobility decreases with decreasing temperature within an entire temperature range.1,2 The observed
␮FET共T兲 at T ⬍ 200 K is qualitatively similar to the one expected for the organic crystals in the presence of shallow
traps, which is given by ␮FET ⬃ T−mexp共−Ea / kBT兲.13,19 The
activation energy Ea, estimated from the slope of the
log ␮FET versus 103 / T plot, is higher than kBT at room temperature and decreases with increasing Vg [inset to Fig. 3(b)].
Note that both Ea values and Ea versus Vg behavior are similar to those obtained for the large-grain pentacene thin film
FET.20 At higher temperatures T ⬃ 180– 280 K the mobility
increases very sharply, ␮FET ⬃ T−m with m ⬃ 10 at Vg ⬃ −20
to −30 V. This power exponent is much higher than that
expected for anthracene crystals 共m ⬃ 1 – 2兲 and reflects the
strong influence of traps which resulted in a strong gate voltage dependence.13
Thus all the above-mentioned experimental data will
show that shallow traps play the major role in handling of
mobility values. As regards the nature of these traps, one
may note that traps created by all types of imperfections are
always present in molecular crystals and interact with injected carriers from the contacts. Two types of carrier trap
distributions have been reported for anthracene crystals: (a)
traps confined in discrete energy levels in the band gap, and
(b) traps with a quasicontinuous distribution of energy levels
(exponential or Gaussian) having a maximum trap density
near the band edges.16 Despite the physical nature of traps
still being discussion, one can relate the discrete trap levels
to chemical impurities introduced into the lattice, and the
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